16 Mosfet I-V and C-V

8/9/2019 16 Mosfet I-V and C-V

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The channel current is: I = V (q nS μ W) /L = V q μ W (ci/q) × (VGS – VT) /L

MOSFET I-V characteristics:general consideration

The current through the channelis

V I

R=

where V is the DRAIN – SOURCE voltage

Here, we are assuming that V


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Key factors affecting FET performance (for any FET type):

In most MOSFET applications, an input signal is the gate voltage VGand the output is the drain current Id.

The ability of MOSFET to amplify the signal is given by the

output/input ratio: the transconductance, g m = dI/dV GS.

MOSFET transconductance

L I and gm

High carrier mobility and short gate length L are the key features of FETs

I = W ci (VGS – VT) V /L

gm = V W ci /L

(V is the Drain – Source voltage)

From this:

μ I and gm


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Modern submicron gate FET

V-groove quantum wire transistor

Source Drain

Gate

Operating frequency – up to 300 GHz

2 μm


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When no drain voltage V is applied, the entire channel has the same potential as the Source, i.e. VCH = 0.

In this case, as we have seen, nS = (ci/q) × (VGS – VT)

Drain current saturation in MOSFET

-+ G

Semiconductor

The gate length L

DS

+-

V

VGS

where VGS is the gate – source voltage and VT is the threshold voltage

When the drain voltage V is applied, the channel potential changesfrom VCH = 0 on the Source side to VCH= V on the drain side.In this case, the induced concentration in the channel also depends

on the position.


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-+ G

Semiconductor

The gate length L

DS

+-

V

VGS

With the drain voltage V is applied, the actual induced concentration inany point x of the channel depends on the potential difference between

the gate and the channel potential V(x) at this point.This is because this local potential difference defines the voltage thatcharges the elementary gate – channel capacitor.On the source end of the channel (x=0, V

CH=0):

nS(0) = (ci/q) × (VGS – VT).On the drain end of the channel (x=L, VCH= V):nS(L) = (ci/q) × (VGS – VT - V) < nS(0)

At any point between source and drain,nS(L) < nS(x) = (ci/q) × [VGS – VT – V(x)] < nS(0)


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L

nS

V=0

VGS > VT

x


V1 > 0

V2 > V1

V3 = VGS-VT

G

Semiconductor

DS

VVGS

Id

V


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MOSFET Modeling

1. Constant mobility modelAssuming a constant electron mobility,μn, using the simple charge control

model the absolute value of the electronvelocity is given by,

vn = μnF = μndV

dx

With the gate voltage above the threshold, the drain current, I d , is given by

I d = WqμndV

dxns Where W is the device width

Rewriting,Where V GT = V GS – V T .

d

n i GT

I dV dx

W c V V ( )μ =

−

dV vs dx dependence represents a series connection of the elementary

parts of MOSFET channel(for the series connection, voltages add up whereas current is the same).


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Integrating along the channel, from x=0 (V=0) to x=L (V=VDS), we obtain:

I d

=W μn ci

L V

GT V DS

I d = W μnci

LV GT −

V DS

2

⎛⎝⎜

⎠⎟ V DS

For, V DS


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Channel pinch off and current saturation

Pinch off occurs when VG

– VCH

= VT

at the drain end;nS (L) =0; the current Id saturates

When,

V DS = V SAT = V GS −V T

where V SAT is the saturation voltage.

The saturation (pinch off) current,

I d = I sat = W μnci2 LV GT 2

I d = W μnci

L

V GT − V DS

2

⎛

⎝

⎜ ⎞

⎠

⎟ V DS

From the Id – V dependence,at VDS=VSAT = VGT,


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Transconductance

Defined as

gm =dI

d

dV GS

V DS

From the equations for the drain current, I d , derived above, we find that

gm =

βV DS , for V DS V SAT

⎧

⎨⎩ β = μnciW

Lwhere

High transconductance is obtained with high values ofthe low field electron mobility, thin gate insulator layers(i.e., larger gate insulator capacitance ci = εi/d i), and

large W / L ratios.


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2. Velocity saturation model

In semiconductors, electric field F accelerates electrons, i.e. the drift velocity of

electron increases: v=μ F

However, at high electric fields this velocitysaturates

In modern short channel devices with channellength of the order of 1 µm or less, the electricfield in the channel can easily exceed the

characteristic electric, Fs field of the velocitysaturation

F s =

vs

μ n


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Electric field in the channel

the electric field in the channel in the direction parallel to the semiconductor-insulator interface

F =

I d

qμ nns V ( )W

0

0.2

0.4

0.6

0.8

1

1.2

0 1 2 3 4 5

P o t e n t i a l ( V )

Distance (µm)

1

1.2

0

2

4

6

8

10

1214

16

18

0 1 2 3 4 5

E l e c t r i c F i e l d ( k V / c m

)

Distance (µm)

1

1.2

0 1 2 3 4 5 S u r f a c e C o n c e n t r a t i o n ( 1 0 1 2

1 / c m

2 )

Distance (µm)

1

1.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Potential, electric field, and surface electron concentration in the channel of a Si MOSFET for V DS = 1 and1.2 V. L = 5 µm, di = 200 Å, µn = 800 cm2/Vs, VGS = 2 V, VT = 1 V.

vn= μ

nF = μ

n

dV

dx


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Once the electric field at the drain side of the channel (where the electric fieldis the highest) exceeds Fs, the electron velocity saturates, leading to the currentsaturation.

In short-channel MOSFETs, this occurs at the drain bias smaller than the pinch-off voltage V DS = V GT .

Field at drain

Saturation condition, F s

= I SAT

μ nci V GT − V SAT ( )W

d

n i GT

I dV dx

W c V V ( )μ =

−

d x L

n i GT DS

I dV F L

dx W c V V ( )

( )μ == = −


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Saturation current versus gate-to-source voltage for 0.5 µm gate and 5 µm gate

MOSFETs. Dashed lines: constant mobility model, solid lines: velocity

saturation model.


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MOSFET saturation current accounting for velocity saturation:

I sat = gchV GT

1+ 1+ V GT

V L

⎛⎝⎜

⎞ ⎠⎟

2

where V L = F s L and the channel conductance g ch = q µ n n s W / L,

where n s=ci V GT /q

When FS L >> VGT (MOSFET with long gate or no velocity saturation):

I sat = g

chV

GT

1+ 1+ V GT

V L

⎛

⎝⎜

⎞

⎠⎟

22ch

sat GT g I V ≈ I d = I sat =

W μnci2 L

V GT 2

(Expression obtained before on slide 9)

When FS L


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Source and drain series resistances.

Source and drain parasitic series resistances, Rs and Rd , play an important role,

especially in short channel devices where the channel resistance is smaller.

Gate

DrainSource

I Rs I R

d + V + DS

Rs

Rd

d d V =ds

V GS = V gs − I d Rs

V DS = V ds − I d Rs + Rd ( )


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The measured transconductance(extrinsic)

gm = dI d

dV gs V ds

=const

The intrinsic transconductance(VGS and VDS being intrinsicvoltages)

gmo = dI d

dV GS V DS =const

Where gd0 is the drain conductance gdo =

dI d

dV DS V GS =const

These parameters are related as gm = gmo

1 + gmo R s + gdo R s + Rd ( )

Similarly, extrinsic drain conductance can be written as,

gd

=g

do

1 + gmo R s + gdo Rs + Rd ( )

In the current saturation region (VDS > VSAT), gd0 ≈ 0


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The saturation current in MOSFET with parasitic resistances:

I sat =

gchoV gt

1+ gcho Rs + 1+ 2gcho Rs + V gt / V L( )2

0

20

40

60

80

100

120

140

160

0 0.5 1 1.5 2 2.5

D r a i n C u r r e n t ( m A )

Drain-to-Source Voltage (V)

0

20

40

60

80

100

120

140

160

0 0.5 1 1.5 2 2.5

D r a i n C u r r e n t

( m A )

Drain-to-Source Voltage (V)

MOSFET output characteristics calculated for zero parasiticresistances and parasitic resistances of 5 Ω. Gate length is 1 µm

where V L = F s L and gcho = ciV gt µnW / L.

MOSFET i l h i i


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MOSFET capacitance-voltage characteristics

To simulate MOSFETs in electronic circuits, we need to have models for boththe current-voltage and the capacitance-voltage characteristics.

As MOSFETs is a three terminal device, we need three capacitances: Cgs, Cgdand Cds.

Capacitance (differential) is defined as C = dQ/dV . For example,C gs = dQ s /dV gs (where Qs is the channel charge between S and G)

Therefore, the total channel charge Q N has to be divided (partitioned) betweenthe source and drain charges. How should we partition Q N between Qs and Qd ?

It is clear from the device symmetry that at zero drain bias Qs = Qd . If the totalchannel charge is Q N, then Qs = 0.5 Q N and Qd = 0.5 Q N.

G

Semiconductor

DS

VVGS

MOSFET it lt h t i ti


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In this case, we let Qs = F pQ N and Qd = (1 – F p)Q N ,where F p is the partitioning factor. In saturation, F p > 0.5

The challenge using this model is to determine F p as a function of Vgs and V

In the saturation regime, the charge distribution is no longer symmetrical: Q s > Q d

MOSFET capacitance-voltage characteristics

M d l f MOSFET it


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Meyer model for MOSFET capacitance(used in SPICE)

22

13 2

GT DS gs i f

T DS

V V C C C

V V

⎡ ⎤⎛ ⎞−⎢ ⎥= − +⎜ ⎟−⎢ ⎥⎝ ⎠⎣ ⎦

C i = ci × W × L is the channel capacitance

The capacitance C f is the fringing capacitance.

C f ≈ βc εsW where βc ≈ 0.5

22

13 2

GT gd i f

T DS

V C C C

V V

⎡ ⎤⎛ ⎞⎢ ⎥= − +⎜ ⎟−⎢ ⎥⎝ ⎠⎣ ⎦

In saturation, VDS has to be replaced by VSAT (where VSAT = VGT)

This results in CGS SAT = (2/3) Ci+Cf ;CGd SAT = Cf

Meyer model for MOSFET capacitance


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Meyer model for MOSFET capacitance(used in SPICE)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VDS/VSAT

CGD/Ci

CGS/Ci

C / C

i

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VDS/VSAT

CGD/Ci

CGS/Ci

C / C

i

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16 Mosfet I-V and C-V