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Back-end technology

Wire the active devices into specific circuitconfigurations

Interconnect layers, contacts, vias and

dielectric layers contacts

Connect to an active region/device in the Si

substrate

Interconnects Connect different contacts/devices

Can be local or global

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Back-end technology

Local interconnects Connect gates, sources, and drains in MOS, and emitters,

bases, and collectors in BJT

Must withstand high temperatures (poly-Si, Silicides, refractorymetals)

Global interconnects Must be low resistance materials (Al, Cu)

Dielectric layer Separate active regions, usually SiO2 IMD (inter-metal dielectrics) separate interconnects

Via-s Metallic connections between two levels of global interconnects

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Back-end technology

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Back-end technology

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Back-end technology

Interconnect Delay

RC Time delay associated with an

interconnect

L =0.89RC, by treating it asa distributed unterminated transmission

line

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Line resistance of an interconnect

Total capacitance associated with the

line

Assumed that lines are surrounded

by oxide on all sides

WH

LR

S

ox

ox

ox

L

HLK

x

WLKC

00

Interconnect Delay

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Interconnect Delay

Total RC delay

KI: empirical constant

for fringing fields

Sox

oxIL

WLHx

LKK11

89.02

0

As chip speed increases

limits the speed.Small desirable

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All dimensions equals minimum feature sizeFmin. With KI=2,the delay is given by

For local interconnects L usually shrinks as Fminshrinks. Hence the delay remains unchanged.

But for global interconnects L usually increases

A is the chip area

Interconnect Delay

2

min

2

0.56.3

F

LK

ox

2max

AL

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Interconnect Delay

Delay associated with a global interconnect is

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Problems

Planarity poor

Al spiking

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Al spiking

Solubility and diffusion of Si in Al is important.

solubility is 0.5 atomic percent at 450oC and 1

atomic percent at 500oC.

Large amounts of Si absorbed by Al.

Creates voids in Si, which are penetrated by

Al. Short circuits shallow junctions.

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Alternative--Use barrierLayers

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Metal ion motion by a wind effect.

Reduces interconnect cross section in certain

regions.

Can cause pile up of metals in some regions

or void formation.

Restrict the current density to about 105A/cm2

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Multilevel interconnections

Larger area

Cross-over possible in two planes,

flexibility in interconnect layout

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Multilevel interconnections

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Planarization

Use W plugs.

Use passivating layers.

Chemical Mechanical polishing.