15978 Unit 4 Clocked Flip Flops

8/2/2019 15978 Unit 4 Clocked Flip Flops

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Digital ElectronicsDigital Electronics

Flip-Flops


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Objectives:

Given input logice levels, state the output of an RS

NAND and RS NOR.

Given a clock signal, determine the PGT and NGT.

Define Edge Triggered and Level Triggered.

Draw a Clocked F/F with and Edge Triggered

clock input and a Level Triggered clock input.


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Logic circuits are classified into two groups:

Combinational logic circuits

Sequential logic circuits

Basic building

blocks include:

Basic building blocks

include FLIP-FLOPS:

LOGIC CIRCUITS

Logic gates make decisions

Flip Flops have memory


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FLIP-FLOPS

S

R

Q

Q

Memory device capable of storing one bit

Memory means circuit remains in onestate after condition that caused the state

is removed.Two outputs designated Q and Q-Not thatare always opposite or complimentary.

When referring to the state of a flip flop,referring to the state of the Q output.


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FLIP-FLOPS

To SET a flip flop means tomake Q =1

To RESET a flip flop means tomake Q = 0

S

R

Q

Q

R

Q=0

No change

S Q

1

Invalid

1

0 0

1

1Q=1

0

MODE

0RESETSET

Symbol

Truth Table

SET

RESET


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FLIP-FLOPS

OUTPUT

Q

OUTPUT

NOT Q

reset

input

set

input

+V5V

NPNNPN

1k1k

1k1k

1k1k

1k1k

The flip flop is a bi-stable multivibrator; it has two stable states.

The RS flip flop can be implemented with transistors.


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R-S FLIP-FLOP

Symbols:

Truth Table:

Set

Reset

S

R

Q

Q

Normal

Comple-

mentary

FF

Mode of Operation Inputs OutputsS R Q Q

Prohibited 0 0 1 1Set 0 1 1 0Reset 1 0 0 1Hold 1 1 Q Q

NOTE: Active-LOW inputs


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R-S FLIP-FLOP

Active-Low

Q NOT

Q

RESET

SET

7400

7400

NAND LATCH

DEMORGANIZED NAND LATCH

NAND LATCH Q

Q NOT

RESET

SET


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ACTIVE-LOW R-S FLIP-FLOP

TIMING DIAGRAMS

0

R

Q=1

1 No change

S Q

10

Invalid00Q=0

11

S

R

Q

Q

R

S

Q

RS

Q

R

S

Q

R

S

Q


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Q

Q

SET

RESET

S

R

Q

Q

S Q

1

No changeQ=1Q=00 1

R

0 01 0

1 Invalid

R-S FLIP-FLOP

Active-High


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ACTIVE-HIGH R-S FLIP-FLOPTIMING DIAGRAMS

S Q

1

No changeQ=1Q=00 1

R

0 01 0

1 Invalid

S

R

Q

Q

R

S

Q

R

S

Q

R

S

Q

R

S

Q


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1. Logic gates make decisions, flip flops have ____________________?

2. One flip flop can store how many bits?

3. What are the two outputs of a flip flop?

4. When referring to the state of a flip flop, were referring to the state

of which output?

5. What does it mean to SET a flip flop?

6. What does it mean to RESET a flip flop?

TEST

Memory

1

Q Q-NOT

Q

Q = 1

Q = 0


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What is the mode of operation of the R-S flip-flop (set, reset or hold)?

What is the output at Q from the R-S flip-flop (active LOW inputs)?

Mode of operation = ?

?H

L

Low

Reset

TEST


?L

H


?H

H

High

High

Hold

Set


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CLOCKED R-S FLIP-FLOP

Set

Reset

S

R

Q

Q

FF

ASYNCHRONOUS

Outputs of logic circuit can

change state anytime one ormore input changes

Set

Reset

S

R

Q

Q

FF

ClockCLK

SYNCHRONOUS

Clock signal determines exact

time at which any output canchange state


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Astable

multivibrator

Clock

Digital signal in the form of a rectangular

or square wave

A clocked flip flop changes state only when

permitted by the clock signal


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TRIGGERING OF FLIP-FLOPS

Level-triggering is the transfer of data from input tooutput of a flip-flop anytime the clock pulse is proper

voltage level.

Edge-triggering is the transfer of data from input to

output of a flip-flop on the rising edge (L-to-H) or fallingedge (H-to-L) of the clock pulse. Edge triggering may be

either positive-edge (L-to-H) or negative-edge (H-to-L).

Level triggering

Positive-edge triggering

Negative-edge triggering

H

Ltime

NGT-Negative Going TransitionPGT-Positive Going Transition


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CLOCKED R-S FLIP-FLOP

Symbols:

Truth Table:

Mode of operation Inputs OutputsClk S R Q Q

Hold + pulse 0 0 no changeReset + pulse 0 1 0 1Set + pulse 1 0 1 0Prohibited 1 1 0 0

NOTE: Active-High inputs

Set

Reset

S

R

Q

Q

Normal

Comple-

mentary

FF

ClockCLK


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What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?

What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?

H

^

L Mode of operation = ?

?

L

^

LMode of operation = ?

?

L

^

HMode of operation = ?

?

High

Set

High

Low

Hold

Reset

TEST


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CLOCKED R-S FLIP-FLOPTIMING DIAGRAMS

S

C

Q

QR

R Q

1

No change

S

X X

1

1

1

1

1

C

0 0

0

0

1

1

1

0

No change

0

Illegal

C

R

S

Q

C

R

S

Q

C

R

S

Q

S

C

Q

QR


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POSITIVE EDGE TRIGGERED

R-S FLIP-FLOPSymbols:

Truth Table:

Q NOT

Q

SET

RESET

CLOCK

CLK R S

0

Q

X X

1

NO CHG

X X

0

X

0

NO CHG

X NO CHG

0 NO CHG

1

1 0

11

SET

RESET

ILLEGAL

S

R

CLK

Q

Q


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POSITIVE EDGE TRIGGERED

R-S FLIP-FLOPTIMING DIAGRAMS

S

R

CLK

Q

Q

0

0

0 NO CHG

1

1 0

1 1

SETRESET

ILLEGAL

CLK R S Q

C

R

SQ


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NEGATIVE EDGE TRIGGERED

R-S FLIP-FLOPSymbols:

Truth Table:

Q NOT

Q

SET

RESET

CLOCK

CLK R S

0

Q

X X

1

NO CHG

X X

0

X

0

NO CHG

X NO CHG

0 NO CHG

1

1 0

11

SET

RESET

ILLEGAL

S

R

CLK

Q

Q

EDGE

DETECTOR


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NEGATIVE EDGE TRIGGERED

R-S FLIP-FLOPTIMING DIAGRAMS

0

0

0 NO CHG

11 0

1 1

SETRESET

ILLEGAL

CLK R S Q

C

R

SQ

S

R

CLK

Q

Q


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TEST

1. Type of flip flop where the outputs of circuit can change state anytime

one or more input changes? ASYNCHRONOUS

2. Type of flip flop where the clock signal controls when any output can

change state? SYNCHRONOUS

3. What do we call a digital signal in the form of a repetitive pulse or square wave?

CLOCK

4. Which is easier to design and troubleshoot, clocked or not clocked flip flops?

Clocked flip flops are easier to troubleshoot because we canstop the clock and examine one set of input and outputconditions.

Documents

15978 Unit 4 Clocked Flip Flops