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The World Leader in High-Performance Signal Processing Solutions
Understanding and Applying DACs
DACs: Not Just For Level Setting Anymore
Conduit from Digital to AnalogApplications
Communications –Wireless, OpticalConsumer – Audio, VideoIndustrial – Controls, InterfaceInstrumentation – Settings, Signals
TopicsWhat they are / doHow they workCare and Feeding
SpecificationsSelectionApply
Applications
MSB
LSB
VREF
N-BITDAC
+FS
0 OR –FS
RANGE(SPAN)
ANALOGOUTPUT
DIGITALINPUTN-BITS
Basic DAC with External Reference(ANALOG)
REFERENCEINPUTVDD
DIGITALINPUT DAC
VSS
VREF
ANALOGOUTPUT
GROUND(MAY BE INTERNALLY CONNECTED TO VSS)
Transfer Function: Ideal Unipolar 3-bit DAC
DAC’s create a correspondence between Digital Input and Analog OutputUnipolar or BipolarLinear or Non-LinearQuantization UncertaintyMonotonic
DIGITAL INPUT (STRAIGHT BINARY)
ANALOGOUTPUT
000 001 010 011 100 101 110 111
FS
0
7/8
3/4
5/8
QuantizationUncertainty
1/23/81/4
1/8
Offset and Gain Error
ACTUAL
OFFSETERROR
WITH GAIN ERROR:OFFSET ERROR = 0ZERO ERROR RESULTSFROM GAIN ERROR
ACTUAL
IDEAL IDEAL
ZERO ERROR ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
–FS –FS
+FS+FS
DAC Integral Linearity Errors(Same Converter on Both Graphs)
END POINT METHOD BEST STRAIGHT LINE METHOD
LINEARITYERROR ≈ X/2
INPUT
OUTPUT
LINEARITYERROR = X
INPUT
DAC Differential Nonlinearity
DIGITAL INPUT
ANALOGOUTPUT
FS
d
d
1 LSB,DNL = 0
2 LSB,DNL = +1 LSB
1 LSB,DNL = 0
–1 LSB,DNL = –2 LSB
1 LSB,DNL = 0
1 LSB,DNL = 0
2 LSB,DNL = +1 LSB
NON-MONOTONIC IFDNL < –1 LSB
BIT 2 IS 1 LSB HIGHBIT 1 IS 1 LSB LOW
000 001 010 011 100 101 110 111DIGITAL INPUT
ANALOGOUTPUT
FS
000 001 010 011 100 101 110 111
NON- MONOTONIC
DAC’s are a Sampled Data System
LPFORBPF
N-BITADC DSP N-BIT
DAC
LPFORBPF
fs fs
fa
AMPLITUDEQUANTIZATION
DISCRETETIME SAMPLING
fa
1fs
ts=
t
Alias Images in the Time DomainSignal (A) = fa SIGNAL (B) (= fs – fa )
1fs t
NOTE: fa IS SLIGHTLY LESS THAN fs
DAC sin x/x Roll Off(Amplitude Normalized)
SAMPLEDSIGNAL
t
0.5fc fc 1.5fc 2fc 2.5fc 3fc
A = sin π f
fcπ ffc
f
A
1–3.92dB
RECONSTRUCTEDSIGNAL
1fc
t
IMAGESIMAGES
IMAGES
0
DAC Settling Time
DEADTIME
RECOVERYTIME
LINEARSETTLING
SLEWTIME
t = 0
ERROR BAND
ERROR BAND
SETTLING TIME (INPUT TO OUTPUT)
SETTLINGTIME (OUTPUT)
DAC Transitions (Showing Glitch)
IDEAL TRANSITIONTRANSITION WITHUNIPOLAR (SKEW)
GLITCH
t
TRANSITION WITHDOUBLET GLITCH
t t
Calculating Net Glitch Impulse Area
+V1
A1
A2 t–V2
t1 t2
V1· t12
PEAK GLITCH IMPULSE AREA = A1 ≈
V2· t22
V1· t12
NET GLITCH IMPULSE AREA = A1 – A2 ≈ –
Effect of Code-Dependent Glitches on Spectral Output
+ FULL SCALE
fO = 3MHz
fS = 10MSPSMIDSCALE
– FULL SCALE
0 1 2 3 4 5 6 7 8 9 10
fS
2fOfS – 2fO
AMPLITUDECANNOTBE FILTEREDfO fS – fO
FREQUENCY (MHz)fS2
Typical DAC DNL Errors(Exaggerated)
OUT OUT
IN IN
MIDSCALE DNL 1/4FS, 3/4FS DNL
(A) (B)
The World Leader in High-Performance Signal Processing Solutions
DAC Architectures
Voltage Output Thermometer DAC: The Kelvin Divider ("String DAC")
Switches are Basic DAC Building BlockEqual ResistancesMonotonicity is Inherent
3-TO-8DECODER
3-BITDIGITALINPUT
ANALOGOUTPUT
V REF
8TO
SWITCHES
R
R
R
R
R
R
R
R
A Slight Modification to a String DACYields a "Digital Potentiometer"
3-TO-8DECODER
3-BITDIGITALINPUT
TAP
8
TOSWITCHES
TERMINAL A
R
R
R
R
R
R
R
TERMINAL B
High Speed Thermometer DAC with Complementary Current Outputs
3-BITDIGITALINPUT
3-TO-7DECODER
I I I I I II
CURRENTOUTPUTSMAY HAVE
COMPLIANCEOF 1 OR 2 V
OUTPUT OUTPUT
A B C D E F G
TOSWITCHES
7
PMOS Transistor Current Switches
RL
+VS
RL
Voltage-Mode Binary Weighted Resistor DAC
R/8 R/4 R/2 R
V
V
REF
OUT
MSBLSB
Adapted from: B. D. Smith, "Coding by Feedback Methods," Proceedings of the I. R. E., Vol. 41, August 1953, pp. 1053-1058
Current-Mode Binary Weighted DACs(A) RESISTOR (B) CURRENT SOURCE
I/2 I/4 I/8
LSB
IVREF
MSB LSB
R 2R 4R 8R
VREF
MSB LSB
R 2R 4R 8R
MSB
DIFFICULT TO FABRICATE IN ICFORM DUE TO LARGE RESISTOR OR CURRENT RATIOS FOR HIGH RESOLUTIONS
CURRENT OUTPUTSINTO VIRTUAL GROUNDS
Voltage-Mode R-2R Ladder Network DAC
2R
R R R
2R 2R 2R 2R
V
V
REF
OUT
MSBLSB
Adapted from: B. D. Smith, "Coding by Feedback Methods," Proceedings of the I. R. E., Vol. 41, August 1953, pp. 1053-1058
Current-Mode R-2R Ladder Network Resistor-Based DAC
2R
RRR
2R2R2R2R
VREF
MSB LSB
CURRENTOUTPUT
INTOVIRTUALGROUND
<< R
*
* GAIN TRIM IF REQUIRED
VREF can be AC allowing 4 quadrant Multiplication
3-Bit Switched Capacitor DAC
_
+C/ 4C/ 2C C/ 4
AIN
VREF
SIN
SC
S1 S2 S3 S4
BIT1(MSB)
BIT2 BIT3(LSB)
A
CTOTAL = 2C
SWITCHES SHOWN IN TRACK (SAMPLE) MODE
Equal Current Sources Switchedinto an R-2R Ladder Network
I I I I
OUTPUT
MSB
R R R
2R 2R 2R 2R2R
LSB
Adapted from: Bernard M. Gordon and Robert P. Talambiras, "Signal Conversion Apparatus,"U.S. Patent 3,108,266, filed July 22, 1955, issued October 22, 1963
Binary-Weighted Current SourcesSwitched into a Load
R (CAN BE EXTERNAL)
OUTPUT
I I/2 I/4 I/8
MSB LSB
Segmented Voltage Output DACsKELVIN-VARLEY DIVIDER
("STRING DAC")VREF
(A)
VREF
OUTPUT
KELVIN DIVIDER ANDR-2R LADDER NETWORK
NOTE:MSB OF R-2R LADDER
ON RIGHT
IF THE R-2R LADDER NETWORKIS MONOTONIC, THE
WHOLE DAC ISMONOTONIC
OUTPUT
(B)
A
B
A
B
A
B
A
B
A
A
B A
B
Segmented Unbuffered String DACs Use Patented Architecture
R
R
R
R
R
R
R
R
R8
VREF
6364
VREF
5564
VREF
5464
VREF
5364
VREF
5264
VREF
5164
VREF
5064
VREF
4964
VREF
4864
VREF
4064
VREF
3264
VREF
2464
VREF
1664
VREF
864
VREF
R
5564
VREF
4864
VREF
R
R OUTPUT
R
R
R
R
Dennis Dempsey and Christopher Gorman, "Digital-to-Analog Converter,"U.S. Patent 5,969,657, filed July 27, 1997, issued October 19, 1999.
Segmented Current Output DACs:(A) Resistor-Based, (B) Current-Source Based
R R R R R R R 2R2R 2R 2R 2R
R R RVREF
-3-BIT MSB THERMOMETER DAC 4-BIT R-2R DAC
CURRENTOUTPUT
CURRENT
I I I I I I I I4
I2
I8
I16
-3-BIT MSB THERMOMETER DAC 4- BIT BINARY DAC
OUTPUT
(A)RESISTOR
BASED
IOUT
IOUT
IOUT
(B)CURRENT-SOURCEBASED
IOUT
AD9775 TxDAC™ 14-Bit CMOS DAC Core
CLOCK
14-BITLATCH
51-BITLATCH
31CURRENTSWITCHES
15CURRENT
5 BINARYCURRENTSWITCHES
BITS 1-5DECODE
5-TO-31
BITS 6-9DECODE
4-TO-15
5 5
15154
31 315
14
CURRENTOUTPUT
FS =2mA-20mA
SWITCHES
I = 512 LSB
I = 32 LSB
I = 1 LSB
5
NOTE: Differential Outputs Not Shown
Analog Filter Requirements for fo = 10MHZ: fc = 30MSPS, and fc = 60MSPS
fCLOCK = 30MSPS
dB
IMAGE
10 20 30 40 50 60 70 80
fo
ANALOG LPF
10 20 30 40 50 60 70 80
IMAGE
ANALOGLPF
FREQUENCY (MHz)
IMAGEIMAGEIMAGE
IMAGE
fo
fCLOCK = 60MSPS
dB
A
B
Oversampling Interpolating DAC
DIGITALINTERPOLATION
FILTERDAC
ANTI-IMAGINGFILTER
N-BITS@ fs
N-BITS@ K fs
(FROM PLL CLOCK MULTIPLIER)Kfs
ANALOGOUTPUT
fsfs2
(B): OVERSAMPLINGWITH INTERPOLATION
Anti-imaging Filter Response(A):NYQUIST
ffKfsKfs
2
Example of 2x LowPass Interpolation
Sigma-Delta DACsSINGLE BIT
N-BITS @ fsN-BITS @ K fs ANALOG SIGNAL:
2 LEVELS
ANALOGOUTPUTDIGITAL
INTERPOLATIONFILTER
DIGITALΣ∆
MODULATOR
1-BITDAC
ANALOGOUTPUTFILTER
1- BIT @ KfS
MULTIBIT
N-BITS @ fsN-BITS @ K fs ANALOG SIGNAL:
2M LEVELS
ANALOGOUTPUTDIGITAL
INTERPOLATIONFILTER
DIGITAL
Σ∆
MODULATOR
M-BITDAC
ANALOGOUTPUTFILTER
M- BITS @ KfS
MULTIBIT
Double-Buffered DAC Permits ComplexInput Structures and Simultaneous Update
OUTPUTDIGITALINPUT INPUT STRUCTURE:
MAY BE SERIAL,PARALLEL, BYTE-WIDE,
ETC.
OUTPUT LATCHTRANSFERS DATA
TO DAC -TIMING IS
INDEPENDENT OFINPUT
DAC
OUTPUT STROBE -MAY GO TO MANY DACs
fc = SAMPLING FREQUENCY
The World Leader in High-Performance Signal Processing Solutions
DAC Applications
LCD Backlight Adjustment using Digital Potentiometer
ADCAmbient
Light Sensor
Micro-controller
TIA
AD5245 ADM8846White LED
Driver
Rset
uC
Power Supplies
Inlet Fan Side
SMBus
VoltageMonitoring
2.5V
5V
1.2V5V ON1.2V ON
uC RESETuC WDI
12V
Power Brick ON
Back-Plane 3.3V
48V
Zone 2Thermal
Exhaust Fan Side
Zone 1Thermal
ADM1060 Sequencer
Digital Pots Used To Margin Supplies
Digital Pots Used To Margin Supplies
Power Supply Margining Using Digital Potentiometers
Dynamic Biasing of DSP Core Voltage
Output Voltage of ADP3051
FB Pin of ADP3051
Rbot
Rtop Rdigipot
Rin AD525850kΩ ± 30%
25kΩ ± 1%
22kΩ±1%
Adding Rtop to improve system tolerance
Min MaxStartup Voltage 1.112 1.220Adjustment Range 0.800 1.326
Streaming Digital Video Distribution System
DSP or Video
Processor
6-CHVideo DAC
Host CPU with digital video
storage
PCI Bus
SDRAM FLASH
EMIFADV7322
VideoAmp
VideoAmp
VideoAmpVideo
Port
VideoAmp
VideoAmp
VideoAmp
SDTV
HDTV
AD8061
Component YPrPb
Y
Pr
Pb
AD8061
AD8061
AD8061
AD8061
AD8061
Automatic Gain Control of VGA for RF Transmitter
AD5620
Thermal & System Management:Wireless Transmitter
0
90 ∑
BPFBPFMIXER RF AMP
LPF
TxDAC
TxDAC
VC_TCXO
ADT7516
AD8349 I/Q MODULATORLPF
ADL 5330IF AMP
DACA
DACB
DACC
AIN1
Fundamental DDS Architecture
Angleto
AmplitudeConverter
D-bitsDAC
Accumulator
TuningWord
IN
SampledSineWave
P-bitsN-bits
N-bits
CLOCK
Fundamental DDS ArchitectureSine Wave Synthesis
TuningWord
IN
Angleto
AmplitudeConverter
D-bits DAC
Accumulator
SampledSineWave
Phase Truncated Phase Quantized Amplitude Sampled Sine Wave
Phas
e
- Amplitude +
Angle to AmplitudeTransformation
P-bitsN-bits
N-bits
2N
0
Phas
e
2P
0
Fo = FsT / 2N
Fundamental DDS Architecture
The “Phase Wheel” Concept:C = 32
Accumulator capacity
T = 5Tuning word value
N = 5Accumulator bits
For this particular case, one revolution around the phase wheel requires 6.4 clock cycles (C/T=6.4).
0
32 = 2N = C
1
2
4
31
T2T
3T
8
16
24
4T5T
6T
3
5
7T
0
+1
-1
A M
P L
I T
U D
E
P H A S E
Instantaneous value ofthe accumulator output.
DDS as a Building BlockClock Generator
DAC
Clock IN (f)
DDS Core
(digital)Tuning Word
COS
SIN
PLL(M)
M x f
ReconstFilter
DC Reference
Clock OUT
COMPARATOR
FrequencyReference
SINEWAVE: - High frequency resolution - Programmable
CLOCK: - Precise frequency - Low jitter
DDS as a Building BlockDigital Modulator
FSK Modulator
DAC
Clock IN (f)
DDS Core
(digital)
Tuning Word #1(f1)
COS
SIN
PLL(M)
M x f
FrequencyReference
FSK Out
MUX
FSK Data(0,1)
f1
f2
Tuning Word #2(f2)
0
1
DDS as a Building BlockDigital Quadrature Modulator
DAC
Clock IN(f)
DDS Core
(digital)Tuning Word(carrier=ωc)
COS(ωc)
PLL(M)
M x f
FrequencyReference
ModulatedOutput
Digital Modulator
SIN(ωc)
Sampler
"I" Signal
"Q" Signal
Frequency Sweep/Burst GeneratorsAD5930 – Low Power DDS
FSTART
FSTART
FSTART
10G Optical Transceiver
10G LDDAND
LASER
PIN/APDAND TIA
IRXP
IMODMON
IMPD
IBIASMON
AINMUX
SDA
VLSRBIASVLSRPWRMON
VXLOPMON
IBIAS
IMOD
SCL
REFOUT/REFIN
AD539x-3AVDD
DVDD AVDD
REFIN
AD7994
12-BITADC
TIAs
I2CBUS
3V
CONTROLLERSDA SCL
0377
3-0-
062
Industrial PLC I/O card
High Voltage MEMs Actuator
DAC’s Abound
DAC’s are EverywhereADI has the broadest and deepest selectionTools, education, etc. on ADI website – www.analog.com
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