137-Ball NAND Flash with LPDDR MCP · 2020. 9. 21. · NAND Flash with Mobile LPDDR 137-Ball MCP MT29C2G24MAAAAKAKD-5 IT, MT29C2G24MAABAKAKD-5 IT, MT29C2G24MAAAAKAHH-5 AIT Features

NAND Flash with Mobile LPDDR137-Ball MCPMT29C2G24MAAAAKAKD-5 IT, MT29C2G24MAABAKAKD-5 IT,MT29C2G24MAAAAKAHH-5 AIT

Features• Micron® NAND Flash and LPDDR components• RoHS-compliant, “green” package• Separate NAND Flash and LPDDR interfaces• Space-saving multichip package• Low-voltage operation (1.70–1.95V)• Industrial temperature range: –40°C to +85°C

NAND Flash-Specific FeaturesOrganization• Page size

– x8: 2112 bytes (2048 + 64 bytes)– x16: 1056 words (1024 + 32 words)

• Block size: 64 pages (128K + 4K bytes)

Mobile LPDDR-Specific Features• No external voltage reference required• No minimum clock rate requirement• 1.8V LVCMOS-compatible inputs• Programmable burst lengths• Partial-array self refresh (PASR)• Deep power-down (DPD) mode• Selectable output drive strength• STATUS REGISTER READ (SRR) supported1

Notes: 1. Contact factory for remapped SRR output.2. For physical part markings, see Part Num-

bering Information (page 2).

Figure 1: MCP Block Diagram

NAND FlashDeviceNAND FlashPower

NAND FlashInterface

LPDRAM Power LPDRAMInterface

LPDRAMDevice

Table 1: Part Number References

MCP NAND Discrete NAND READ ID Parameter

MT29C2G24MAAAAKAKD-5 IT MT29F2G08ABBEA 2Gb, x8, 1.8V

MT29C2G24MAAAAKAHH-5 AIT MT29F2G08ABBEA 2Gb, x8, 1.8V

MT29C2G24MAABAKAKD-5 IT MT29F2G16ABBEA 2Gb, x16, 1.8V

Note: 1. While this is the NAND 1.8V device, the lock pin is not supported, and the LOCK feature does not apply.

Micron Confidential and Proprietary

137-Ball NAND Flash with LPDDR MCPFeatures

PDF: 09005aef840b16af137ball_nand_lpddr_j41L.pdf – Rev. G 11/15 EN 1

Micron Technology, Inc. reserves the right to change products or specifications without notice.© 2010 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Part Numbering Information

Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoPpart numbering guide is available at www.micron.com/numbering.

Figure 2: Part Number Chart

MT 29C 1G 12M A A C A KC -6 IT ES

Production StatusBlank = Production

ES = Engineering sample

Operating Temperature RangeAIT = Automotive grade industrial (–40° to +85° C)

IT = Industrial (–40° to +85° C)

WT = Wireless (–25° to +85° C)

Special OptionsBlank = Standard

LPDRAM Access Time-5 = 200 MHz CL3

-6 = 166 MHz CL3

-75 = 133 MHz CL3

-48 = 208 MHz

Package CodesKC = 107-ball TFBGA (10.5 x 13 x 1.1 mm), SAC105, MCP

MD = 130-ball VFBGA (8 x 9 x 1 mm), SAC105, MCP

MR = 130-ball VFBGA (8 x 9 x 1 mm), SAC302, MCP

KS = 137-ball VFBGA (10.5 x 13 x 1 mm), SAC105, MCP

HK = 137-ball VFBGA (10.5 x 13 x 1 mm), SAC302, MCP

KD = 137-ball TFBGA (10.5 x 13 x 1.1 mm), SAC105, MCP

HH = 137-ball TFBGA (10.5 x 13 x 1.1 mm), SAC302, MCP

ML = 153-ball VFBGA (8 x 9 x 0.9 mm), LF35, MCP

KE = 160-ball VFBGA (15 x 15 x 1 mm), SAC105, PoP

KB = 168-ball WFBGA (12 x 12 x 0.8 mm), SAC105, PoP

JG = 168-ball VFBGA (12 x 12 x 0.9 mm), SAC105, Pop

JV = 168-ball VFBGA (12 x 12 x 1 mm), SAC105, Pop

Chip Count CE#, CS# Chip Count

A 1, 1 1 NAND, 1 LPDRAM

C 1, 2 1 NAND, 2 LPDRAM

D 1, 2 2 NAND, 2 LPDRAM

Micron Technology

Product Family29C = NAND + LPDRAM MCP/PoP

NAND Density1G = 1 Gb

2G = 2 Gb

4G = 4 Gb

8G = 8 Gb

LPDRAM Density12M = 512 Mb

24M = 1024 Mb

48M = 2048 Mb

56M = 256 Mb

96M = 4096 Mb

Operating Voltage RangeA = 1.8 V (1.70–1.95 V)

NAND Flash Configuration Width Density Generation

D x16 1 Gb First

Y x8 4 Gb Second

Z x16 4 Gb Second

AA x8 2 Gb Third

AB x16 2 Gb Third

AC x8 1 Gb Third

AD x16 1 Gb Third

AG x8 4 Gb Fourth

AI x8 1 Gb Fourth

AJ x16 1 Gb Fourth

LPDRAM Configuration Type Width Density Generation

L DDR x32 1 Gb First

V DDR x16 512 Mb Third

Z SDR x16 256 Mb First

AA DDR x16 256 Mb First

AE SDR x16 512 Mb Third

AF SDR x32 512 Mb Third

AH DDR x16 1 Gb Second

AK DDR x32 1 Gb Second

AP DDR x32 2 Gb First

AU DDR x32 256 Mb First

BA DDR x32 2 Gb Second

BB DDR x32 2 Gb Third

Device Marking

Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks arecross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at www.micron.com/csn.





http://www.micron.com/numberinghttp://www.micron.com/decoderhttp://www.micron.com/csn

ContentsMCP General Description ............................................................................................................................... 11Ball Assignments and Descriptions ................................................................................................................. 12Electrical Specifications .................................................................................................................................. 17Device Diagrams ............................................................................................................................................ 18Package Dimensions ....................................................................................................................................... 192Gb: x8, x16 NAND Flash Memory ................................................................................................................... 20

Features ..................................................................................................................................................... 20General Description ....................................................................................................................................... 21Architecture ................................................................................................................................................... 22Device and Array Organization ........................................................................................................................ 23Asynchronous Interface Bus Operation ........................................................................................................... 25

Asynchronous Enable/Standby ................................................................................................................... 25Asynchronous Commands .......................................................................................................................... 25Asynchronous Addresses ............................................................................................................................ 27Asynchronous Data Input ........................................................................................................................... 28Asynchronous Data Output ......................................................................................................................... 29Write Protect# ............................................................................................................................................ 30Ready/Busy# .............................................................................................................................................. 31

Device Initialization ....................................................................................................................................... 35Command Definitions .................................................................................................................................... 36Reset Operations ............................................................................................................................................ 39

RESET (FFh) ............................................................................................................................................... 39Identification Operations ................................................................................................................................ 40

READ ID (90h) ............................................................................................................................................ 40READ ID Parameter Tables .............................................................................................................................. 41READ PARAMETER PAGE (ECh) ...................................................................................................................... 43Parameter Page Data Structure Tables ............................................................................................................. 44READ UNIQUE ID (EDh) ................................................................................................................................ 48Feature Operations ......................................................................................................................................... 49

SET FEATURES (EFh) .................................................................................................................................. 50GET FEATURES (EEh) ................................................................................................................................. 51

Status Operations ........................................................................................................................................... 54READ STATUS (70h) ................................................................................................................................... 55READ STATUS ENHANCED (78h) ................................................................................................................ 55

Column Address Operations ........................................................................................................................... 57RANDOM DATA READ (05h-E0h) ................................................................................................................ 57RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 58RANDOM DATA INPUT (85h) ...................................................................................................................... 59PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 60

Read Operations ............................................................................................................................................. 62READ MODE (00h) ..................................................................................................................................... 64READ PAGE (00h-30h) ................................................................................................................................ 64READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 65READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 66READ PAGE CACHE LAST (3Fh) .................................................................................................................. 68READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 69

Program Operations ....................................................................................................................................... 71PROGRAM PAGE (80h-10h) ......................................................................................................................... 72PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 72PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 75





Erase Operations ............................................................................................................................................ 77ERASE BLOCK (60h-D0h) ............................................................................................................................ 77ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 78

Internal Data Move Operations ....................................................................................................................... 79READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 80PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 81PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 82

Block Lock Feature ......................................................................................................................................... 83WP# and Block Lock ................................................................................................................................... 83UNLOCK (23h-24h) .................................................................................................................................... 83LOCK (2Ah) ................................................................................................................................................ 86LOCK TIGHT (2Ch) ..................................................................................................................................... 87BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 88

One-Time Programmable (OTP) Operations .................................................................................................... 90Legacy OTP Commands .............................................................................................................................. 90OTP DATA PROGRAM (80h-10h) ................................................................................................................. 91RANDOM DATA INPUT (85h) ...................................................................................................................... 92OTP DATA PROTECT (80h-10) ..................................................................................................................... 93OTP DATA READ (00h-30h) ......................................................................................................................... 95

Two-Plane Operations .................................................................................................................................... 97Two-Plane Addressing ................................................................................................................................ 97

Interleaved Die (Multi-LUN) Operations ......................................................................................................... 106Error Management ........................................................................................................................................ 107Internal ECC and Spare Area Mapping for ECC ............................................................................................... 109Electrical Specifications ................................................................................................................................. 111Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 113Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 115Electrical Specifications – Program/Erase Characteristics ................................................................................ 118Asynchronous Interface Timing Diagrams ...................................................................................................... 1191Gb: x16, x32 Mobile LPDDR SDRAM ............................................................................................................. 131

Features .................................................................................................................................................... 131General Description .................................................................................................................................. 132

Functional Block Diagrams ............................................................................................................................ 133Electrical Specifications ................................................................................................................................. 135Electrical Specifications – IDD Parameters ....................................................................................................... 139Electrical Specifications – AC Operating Conditions ........................................................................................ 145Output Drive Characteristics .......................................................................................................................... 150Functional Description .................................................................................................................................. 153Commands ................................................................................................................................................... 154

DESELECT ................................................................................................................................................ 155NO OPERATION ........................................................................................................................................ 155LOAD MODE REGISTER ............................................................................................................................ 155ACTIVE ..................................................................................................................................................... 155READ ........................................................................................................................................................ 156WRITE ...................................................................................................................................................... 157PRECHARGE ............................................................................................................................................. 158BURST TERMINATE .................................................................................................................................. 159AUTO REFRESH ........................................................................................................................................ 159SELF REFRESH .......................................................................................................................................... 160DEEP POWER-DOWN ................................................................................................................................ 160

Truth Tables .................................................................................................................................................. 161State Diagram ............................................................................................................................................... 166





Initialization ................................................................................................................................................. 167Standard Mode Register ................................................................................................................................. 170

Burst Length ............................................................................................................................................. 171Burst Type ................................................................................................................................................. 171CAS Latency .............................................................................................................................................. 172Operating Mode ........................................................................................................................................ 173

Extended Mode Register ................................................................................................................................ 174Temperature-Compensated Self Refresh ..................................................................................................... 174Partial-Array Self Refresh ........................................................................................................................... 175Output Drive Strength ............................................................................................................................... 175

Status Read Register ...................................................................................................................................... 176Bank/Row Activation ..................................................................................................................................... 178READ Operation ............................................................................................................................................ 179WRITE Operation .......................................................................................................................................... 190PRECHARGE Operation ................................................................................................................................. 202Auto Precharge .............................................................................................................................................. 202

Concurrent Auto Precharge ........................................................................................................................ 202AUTO REFRESH Operation ............................................................................................................................ 209SELF REFRESH Operation .............................................................................................................................. 210Power-Down ................................................................................................................................................. 212

Deep Power-Down .................................................................................................................................... 213Clock Change Frequency ............................................................................................................................... 215Revision History ............................................................................................................................................ 216

Rev. G – 11/15 ............................................................................................................................................ 216Rev. F – 11/14 ............................................................................................................................................ 216Rev. E, Production – 03/14 .......................................................................................................................... 216Rev. D, Production – 01/11 ......................................................................................................................... 216Rev. C, Production – 1/11 ........................................................................................................................... 216Rev. B, Preliminary – 6/10 ........................................................................................................................... 216Rev. A, Preliminary – 6/10 .......................................................................................................................... 216





List of FiguresFigure 1: MCP Block Diagram .......................................................................................................................... 1Figure 2: Part Number Chart ............................................................................................................................ 2Figure 3: 137-Ball TFBGA (NAND x8/x16; LPDDR x32) Ball Assignments .......................................................... 12Figure 4: 137-Ball TFBGA (NAND x8/x16; LPDDR x16) Ball Assignments .......................................................... 13Figure 5: 137-Ball Functional Block Diagram (LPDDR) .................................................................................. 0Figure 6: 137-Ball TFBGA (Package Code: KD, HH) .......................................................................................... 19Figure 7: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 22Figure 8: Array Organization – MT29F2G08 (x8) .............................................................................................. 23Figure 9: Array Organization – MT29F2G16 (x16) ............................................................................................ 24Figure 10: Asynchronous Command Latch Cycle ............................................................................................ 26Figure 11: Asynchronous Address Latch Cycle ................................................................................................ 27Figure 12: Asynchronous Data Input Cycles .................................................................................................... 28Figure 13: Asynchronous Data Output Cycles ................................................................................................. 29Figure 14: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 30Figure 15: READ/BUSY# Open Drain .............................................................................................................. 32Figure 16: tFall and tRise (3.3V VCC) ................................................................................................................ 32Figure 17: tFall and tRise (1.8V VCC) ................................................................................................................ 33Figure 18: IOL vs. Rp (VCC = 3.3V VCC) .............................................................................................................. 33Figure 19: IOL vs. Rp (1.8V VCC) ....................................................................................................................... 34Figure 20: TC vs. Rp ....................................................................................................................................... 34Figure 21: R/B# Power-On Behavior ............................................................................................................... 35Figure 22: RESET (FFh) Operation .................................................................................................................. 39Figure 23: READ ID (90h) with 00h Address Operation .................................................................................... 40Figure 24: READ ID (90h) with 20h Address Operation .................................................................................... 40Figure 25: READ PARAMETER (ECh) Operation .............................................................................................. 43Figure 26: READ UNIQUE ID (EDh) Operation ............................................................................................... 48Figure 27: SET FEATURES (EFh) Operation .................................................................................................... 50Figure 28: GET FEATURES (EEh) Operation .................................................................................................... 51Figure 29: READ STATUS (70h) Operation ...................................................................................................... 55Figure 30: READ STATUS ENHANCED (78h) Operation ................................................................................... 56Figure 31: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 57Figure 32: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 58Figure 33: RANDOM DATA INPUT (85h) Operation ........................................................................................ 59Figure 34: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 61Figure 35: READ PAGE (00h-30h) Operation ................................................................................................... 65Figure 36: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 65Figure 37: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 66Figure 38: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 67Figure 39: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 68Figure 40: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 70Figure 41: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 72Figure 42: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 74Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 74Figure 44: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 76Figure 45: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 77Figure 46: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 78Figure 47: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 80Figure 48: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 80Figure 49: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 81Figure 50: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 81





Figure 51: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 81Figure 52: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 82Figure 53: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 82Figure 54: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 84Figure 55: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 84Figure 56: UNLOCK Operation ....................................................................................................................... 85Figure 57: LOCK Operation ............................................................................................................................ 86Figure 58: LOCK TIGHT Operation ................................................................................................................. 87Figure 59: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 88Figure 60: BLOCK LOCK READ STATUS .......................................................................................................... 88Figure 61: BLOCK LOCK Flowchart ................................................................................................................ 89Figure 62: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 92Figure 63: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 93Figure 64: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 94Figure 65: OTP DATA READ ........................................................................................................................... 95Figure 66: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 96Figure 67: TWO-PLANE PAGE READ .............................................................................................................. 98Figure 68: TWO-PLANE PAGE READ with RANDOM DATA READ .................................................................... 99Figure 69: TWO-PLANE PROGRAM PAGE ....................................................................................................... 99Figure 70: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 100Figure 71: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 101Figure 72: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 102Figure 73: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 103Figure 74: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 104Figure 75: TWO-PLANE BLOCK ERASE ......................................................................................................... 105Figure 76: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 105Figure 77: Spare Area Mapping (x8) ............................................................................................................... 109Figure 78: Spare Area Mapping (x16) ............................................................................................................. 110Figure 79: RESET Operation .......................................................................................................................... 119Figure 80: READ STATUS Cycle ..................................................................................................................... 119Figure 81: READ STATUS ENHANCED Cycle .................................................................................................. 120Figure 82: READ PARAMETER PAGE ............................................................................................................. 120Figure 83: READ PAGE .................................................................................................................................. 121Figure 84: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 122Figure 85: RANDOM DATA READ .................................................................................................................. 123Figure 86: READ PAGE CACHE SEQUENTIAL ................................................................................................ 124Figure 87: READ PAGE CACHE RANDOM ...................................................................................................... 125Figure 88: READ ID Operation ...................................................................................................................... 126Figure 89: PROGRAM PAGE Operation .......................................................................................................... 126Figure 90: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 127Figure 91: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 127Figure 92: PROGRAM PAGE CACHE .............................................................................................................. 128Figure 93: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 128Figure 94: INTERNAL DATA MOVE ............................................................................................................... 129Figure 95: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 129Figure 96: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................. 130Figure 97: ERASE BLOCK Operation .............................................................................................................. 130Figure 98: Functional Block Diagram (x16) .................................................................................................... 133Figure 99: Functional Block Diagram (x32) .................................................................................................... 134Figure 100: Typical Self Refresh Current vs. Temperature ................................................................................ 144Figure 101: ACTIVE Command ..................................................................................................................... 156Figure 102: READ Command ........................................................................................................................ 157





Figure 103: WRITE Command ....................................................................................................................... 158Figure 104: PRECHARGE Command ............................................................................................................. 159Figure 105: DEEP POWER-DOWN Command ................................................................................................ 160Figure 106: Simplified State Diagram ............................................................................................................ 166Figure 107: Initialize and Load Mode Registers .............................................................................................. 168Figure 108: Alternate Initialization with CKE LOW ......................................................................................... 169Figure 109: Standard Mode Register Definition .............................................................................................. 170Figure 110: CAS Latency ............................................................................................................................... 173Figure 111: Extended Mode Register ............................................................................................................. 174Figure 112: Status Read Register Timing ........................................................................................................ 176Figure 113: Status Register Definition ............................................................................................................ 177Figure 114: READ Burst ................................................................................................................................ 180Figure 115: Consecutive READ Bursts ............................................................................................................ 181Figure 116: Nonconsecutive READ Bursts ...................................................................................................... 182Figure 117: Random Read Accesses ............................................................................................................... 183Figure 118: Terminating a READ Burst ........................................................................................................... 184Figure 119: READ-to-WRITE ......................................................................................................................... 185Figure 120: READ-to-PRECHARGE ................................................................................................................ 186Figure 121: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) ................................................. 187Figure 122: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) ................................................. 188Figure 123: Data Output Timing – tAC and tDQSCK ........................................................................................ 189Figure 124: Data Input Timing ...................................................................................................................... 191Figure 125: Write – DM Operation ................................................................................................................. 192Figure 126: WRITE Burst ............................................................................................................................... 193Figure 127: Consecutive WRITE-to-WRITE .................................................................................................... 194Figure 128: Nonconsecutive WRITE-to-WRITE .............................................................................................. 194Figure 129: Random WRITE Cycles ............................................................................................................... 195Figure 130: WRITE-to-READ – Uninterrupting ............................................................................................... 196Figure 131: WRITE-to-READ – Interrupting ................................................................................................... 197Figure 132: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................. 198Figure 133: WRITE-to-PRECHARGE – Uninterrupting .................................................................................... 199Figure 134: WRITE-to-PRECHARGE – Interrupting ........................................................................................ 200Figure 135: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ....................................................... 201Figure 136: Bank Read – With Auto Precharge ................................................................................................ 204Figure 137: Bank Read – Without Auto Precharge ........................................................................................... 206Figure 138: Bank Write – With Auto Precharge ............................................................................................... 207Figure 139: Bank Write – Without Auto Precharge .......................................................................................... 208Figure 140: Auto Refresh Mode ..................................................................................................................... 209Figure 141: Self Refresh Mode ....................................................................................................................... 211Figure 142: Power-Down Entry (in Active or Precharge Mode) ........................................................................ 212Figure 143: Power-Down Mode (Active or Precharge) ..................................................................................... 213Figure 144: Deep Power-Down Mode ............................................................................................................ 214Figure 145: Clock Stop Mode ........................................................................................................................ 215





List of TablesTable 1: Part Number References ..................................................................................................................... 1Table 2: x8, x16 NAND Ball Descriptions ......................................................................................................... 14Table 3: x16, x32 LPDDR Ball Descriptions ...................................................................................................... 15Table 4: Non-Device-Specific Descriptions ..................................................................................................... 16Table 5: Absolute Maximum Ratings .............................................................................................................. 17Table 6: Recommended Operating Conditions ................................................................................................ 17Table 7: Chip-Select Signal Assignments per Chip-Count Configuration .......................................................... 18Table 8: Array Addressing – MT29F2G08 (x8) .................................................................................................. 23Table 9: Array Addressing – MT29F2G16 (x16) ................................................................................................. 24Table 10: Asynchronous Interface Mode Selection .......................................................................................... 25Table 11: Command Set ................................................................................................................................. 36Table 12: Two-Plane Command Set ................................................................................................................ 38Table 13: READ ID Parameters for Address 00h ............................................................................................... 41Table 14: READ ID Parameters for Address 20h ............................................................................................... 42Table 15: Parameter Page Data Structure ........................................................................................................ 44Table 16: Feature Address Definitions ............................................................................................................. 49Table 17: Feature Address 90h – Array Operation Mode ................................................................................... 50Table 18: Feature Addresses 01h: Timing Mode ............................................................................................... 52Table 19: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 53Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 53Table 21: Status Register Definition ................................................................................................................ 54Table 22: Block Lock Address Cycle Assignments ............................................................................................ 85Table 23: Block Lock Status Register Bit Definitions ........................................................................................ 88Table 24: Error Management Details ............................................................................................................. 107Table 25: Absolute Maximum Ratings ............................................................................................................ 111Table 26: Recommended Operating Conditions ............................................................................................. 111Table 27: Valid Blocks ................................................................................................................................... 111Table 28: Capacitance ................................................................................................................................... 112Table 29: Test Conditions .............................................................................................................................. 112Table 30: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 113Table 31: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 114Table 32: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 115Table 33: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 115Table 34: AC Characteristics: Normal Operation (3.3V) .................................................................................. 116Table 35: AC Characteristics: Normal Operation (1.8V) .................................................................................. 116Table 36: Program/Erase Characteristics ....................................................................................................... 118Table 37: Configuration Addressing ............................................................................................................... 131Table 38: Absolute Maximum Ratings ............................................................................................................ 135Table 39: AC/DC Electrical Characteristics and Operating Conditions ............................................................ 135Table 40: AC/DC Electrical Characteristics and Operating Conditions ............................................................ 137Table 41: Capacitance (x16, x32) ................................................................................................................... 138Table 42: IDD Specifications and Conditions, –40°C to +85°C (x16) .................................................................. 139Table 43: IDD Specifications and Conditions, –40°C to +85°C (x32) .................................................................. 140Table 44: IDD Specifications and Conditions, –40°C to +105°C (x16) ................................................................. 141Table 45: IDD Specifications and Conditions, –40°C to +105°C (x32) ................................................................. 142Table 46: IDD6 Specifications and Conditions ................................................................................................. 143Table 47: Electrical Characteristics and Recommended AC Operating Conditions ........................................... 145Table 48: Target Output Drive Characteristics (Full Strength) .......................................................................... 150Table 49: Target Output Drive Characteristics (Three-Quarter Strength) ......................................................... 151Table 50: Target Output Drive Characteristics (One-Half Strength) ................................................................. 152





Table 51: Truth Table – Commands ............................................................................................................... 154Table 52: DM Operation Truth Table ............................................................................................................. 155Table 53: Truth Table – Current State Bank n – Command to Bank n ............................................................... 161Table 54: Truth Table – Current State Bank n – Command to Bank m .............................................................. 163Table 55: Truth Table – CKE .......................................................................................................................... 165Table 56: Burst Definition Table .................................................................................................................... 171





MCP General DescriptionMicron MCP products combine NAND Flash and Mobile LPDRAM devices in a singleMCP. These products target mobile applications with low-power, high-performance,and minimal package-footprint design requirements. The NAND Flash and MobileLPDRAM devices are also members of the Micron discrete memory products portfolio.

The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces(no shared address, control, data, or power balls). This bus architecture supports an op-timized interface to processors with separate NAND Flash and Mobile LPDRAM buses.The NAND Flash and Mobile LPDRAM devices have separate core power connectionsand share a common ground (that is, VSS is tied together on the two devices).

The bus architecture of this device also supports separate NAND Flash and MobileLPDRAM functionality without concern for device interaction.


137-Ball NAND Flash with LPDDR MCPMCP General Description



Ball Assignments and Descriptions

Figure 3: 137-Ball TFBGA (NAND x8/x16; LPDDR x32) Ball Assignments

1

NC

VSS

VDD

A6

A12

DNU

VDD

VSS

WE#

A1

VDD

I/O0

RFU

DNU

2

DNU

CKE1

A4

A5

A8

A11

RAS#

CAS#

CS0#

BA1

A2

VSS

I/O1

I/O8

DNU

3

RE#

WP#

A7

CKE0

CS1#

DQ15

DQ20

BA0

A10

A3

A13

I/O2

I/O9

4

CLE

ALE

A9

DQ18

DQ17

DQ16

DQ21

DQ14

A0

DQ0

RFU

I/O10

I/O11

5

VCC

VSS

DQ25

DQS3

DQ19

DQS1

DQ13

DQ11

DQ7

DQ1

I/O3

VCC

I/O12

6

CE#

R/B#

DQ27

DQ22

DQ24

DM1

DQ12

DQ10

DQ8

DQ2

I/O5

I/O6

VSS

7

WE#

DQ31

DQ29

DM3

DQ23

DQ9

DQS2

DQS0

DQ6

DQ3

I/O14

I/O13

I/O4

8

VDD

DQ30

DQ28

DQ26

DM2

CK

CK#

DM0

DQ4

DQ5

I/O7

I/O15

VDD

9

DNU

VSS

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VSS

VSSQ

VDDQ

VDDQ

VSSQ

VDDQ

VSS

DNU

10

DNU

NC

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VDD

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

LOCK

DNU

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Top View – Ball Down

NAND LPDDR Supply Ground


137-Ball NAND Flash with LPDDR MCPBall Assignments and Descriptions



Figure 4: 137-Ball TFBGA (NAND x8/x16; LPDDR x16) Ball Assignments

1

NC

VSS

VDD

A6

A12

DNU

VDD

VSS

WE#

A1

VDD

I/O0

RFU

DNU

2

DNU

CKE1

A4

A5

A8

A11

RAS#

CAS#

CS0#

BA1

A2

VSS

I/O1

I/O8

DNU

3

RE#

WP#

A7

CKE0

CS1#

DQ7

DQ12

BA0

A10

A3

A13

I/O2

I/O9

4

CLE

ALE

A9

DQ10

DQ9

DQ8

DQ13

DQ6

A0

RFU

RFU

I/O10

I/O11

5

VCC

VSS

RFU

RFU

DQ11

LDQS

DQ5

DQ3

RFU

RFU

I/O3

VCC

I/O12

6

CE#

R/B#

RFU

DQ14

RFU

LDM

DQ4

DQ2

DQ0

RFU

I/O5

I/O6

VSS

7

WE#

RFU

RFU

RFU

DQ15

DQ1

UDQS

RFU

RFU

RFU

I/O14

I/O13

I/O4

8

VDD

RFU

RFU

RFU

UDM

CK

CK#

RFU

RFU

RFU

I/O7

I/O15

VDD

9

DNU

VSS

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VSS

VSSQ

VDDQ

VDDQ

VSSQ

VDDQ

VSS

DNU

10

DNU

NC

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VDD

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

LOCK

DNU

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Top View – Ball Down

NAND LPDDR Supply Ground





Table 2: x8, x16 NAND Ball Descriptions

Symbol Type Description

ALE Input Address latch enable: When ALE is HIGH, addresses canbe transferred to the on-chip address register.

CE# Input Chip enable: Gates transfers between the host systemand the NAND device.

CLE Input Command latch enable: When CLE is HIGH,commands can be transferred to the on-chipcommand register.

LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCKfunction is enabled. To disable BLOCK LOCK,connect LOCK to VSS during power-up, or leave itunconnected (internal pull-down).

RE# Input Read enable: Gates information from the NANDdevice to the host system.

WE# Input Write enable: Gates information from the host systemto the NAND device.

WP# Input Write protect: Driving WP# LOW blocks ERASE andPROGRAM operations.

I/O[7:0](x8)

I/O[15:0](x16)

Input/output

Data inputs/outputs: The bidirectional I/Os transferaddress, data, and instruction information. Data isoutput only during READ operations; at other timesthe I/Os are inputs.I/O[15:8] are RFU1 for NAND x8 devices.

R/B# Output Ready/busy: Open-drain, active-LOW output thatindicates when an internal operation is in progress.

VCC Supply VCC: NAND power supply.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not beused. Contact factory for details.





Table 3: x16, x32 LPDDR Ball Descriptions


A[13:0] Input Address inputs: Specifies the row or column address.Also used to load the mode registers. The maximumLPDDR address is determined by density andconfiguration. Consult the LPDDR product data sheetfor the maximum address for a given density andconfiguration. Unused address balls become RFU.1

BA0, BA1 Input Bank address inputs: Specifies one of the 4 banks.

CAS# Input Column select: Specifies which command to execute.

CK, CK# Input CK is the system clock. CK and CK# are differentialclock inputs. All address and control signals aresampled and referenced on the crossing of the risingedge of CK with the falling edge of CK#.

CKE0, CKE1 Input Clock enable.CKE0 is used for a single LPDDR product.CKE1 is used for dual LPDDR products and isconsidered RFU for single LPDDR MCPs.

CS0#, CS1# Input Chip select:CS0# is used for a single LPDDR product.CS1# is used for dual LPDDR products and isconsidered RFU for single LPDDR MCPs.

UDM, LDM(x16)

DM[3:0](x32)

Input Data mask: Determines which bytes are writtenduring WRITE operations.For x16 LPDDR, unused DM balls become RFU.

RAS# Input Row select: Specifies the command to execute.

WE# Input Write enable: Specifies the command to execute.

DQ[15:0](x16)

DQ[31:0](x32)

Input/output

Data bus: Data inputs/outputs.DQ[31:16] are RFU for x16 LPDDR devices.

UDQS, LDQS(x16)

DQS[3:0](x32)

Input/output

Data strobe: Coordinates READ/WRITE transfersof data; one DQS per DQ byte.For x16 LPDDR, unused DQS balls become RFU.

VDD Supply VDD: LPDDR power supply.

VDDQ Supply VDDQ: LPDDR I/O power supply.

VSSQ Supply VSSQ: LPDDR I/O ground.






Table 4: Non-Device-Specific Descriptions


VSS Supply VSS: Shared ground.


DNU – Do not use: Must be grounded or left floating.

NC – No connect: Not internally connected.

RFU1 – Reserved for future use.






Electrical Specifications

Table 5: Absolute Maximum Ratings

Parameters/Conditions Symbol Min Max Unit

VCC, VDD, VDDQ supply voltagerelative to VSS

VCC, VDD,VDDQ

–1.0 2.4 V

Voltage on any pinrelative to VSS

VIN –0.5 2.4 or (supply voltage1 +0.3V), whichever is less

V

Storage temperature range –55 +150 °C

Note: 1. Supply voltage references VCC, VDD, or VDDQ.

Stresses greater than those listed under “Absolute Maximum Ratings” may cause per-manent damage to the device. This is a stress rating only, and functional operation ofthe device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute maximum rating condi-tions for extended periods may affect reliability.

Table 6: Recommended Operating Conditions

Parameters Symbol Min Typ Max Unit

Supply voltage VCC, VDD 1.70 1.80 1.95 V

I/O supply voltage VDDQ 1.70 1.80 1.95 V

Operating temperature range – –40 – +85 °C


137-Ball NAND Flash with LPDDR MCPElectrical Specifications



Device Diagrams

Figure 5: 137-Ball Functional Block Diagram (LPDDR)

CE#

CLE

ALE

RE#

WE#

WP#

LOCK

CS0#

CK

CK#

CKE0

RAS#

CAS#

WE#

Address,

BA0, BA1

VCC

I/O

R/B#

VSS

VDDVDDQDM

DQ

DQS

VSSVSSQ

NAND Flash

LPDDR

Table 7: Chip-Select Signal Assignments per Chip-Count Configuration

Chip Count DRAM Die 0 DRAM Die 1 Notes

1 NAND, 1 LPDRAM CS0#, CKE0 n/a

1 NAND, 2 LPDRAM CS0#, CKE0 CS1#, CKE1 1

2 NAND, 2 LPDRAM CS0#, CKE0 CS1#, CKE1 1, 2

Notes: 1. All other signals are shared between both DRAM devices.2. When multiple NAND chips are included, they share a single CE signal.


137-Ball NAND Flash with LPDDR MCPDevice Diagrams



Package Dimensions

Figure 6: 137-Ball TFBGA (Package Code: KD, HH)

Ball A1 ID

1 ±0.1

13 ±0.1

Ball A1 ID(covered by SR)

0.8 TYP

0.8 TYP

10.5 ±0.1

Seatingplane

A

11.2 CTR

7.2 CTR

0.1 A

137X Ø0.45Dimensions applyto solder balls post-reflow on Ø0.4SMD ball pads.

0.25 MIN

10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Notes: 1. All dimensions are in millimeters.2. Package code KD uses solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu).3. Package code HH uses solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).


137-Ball NAND Flash with LPDDR MCPPackage Dimensions



2Gb: x8, x16 NAND Flash Memory

Features

• Open NAND Flash Interface (ONFI) 1.0-compliant1

• Single-level cell (SLC) technology• Organization

– Page size x8: 2112 bytes (2048 + 64 bytes)– Page size x16: 1056 words (1024 + 32 words)– Block size: 64 pages (128K + 4K bytes)– Plane size: 2 planes x 1024 blocks per plane– Device size: 2Gb: 2048 blocks

• Asynchronous I/O performance– tRC/tWC: 20ns (3.3V), 25ns (1.8V)

• Array performance– Read page: 25μs 2

– Program page: 200μs (TYP: 1.8V, 3.3V)2

– Erase block: 700μs (TYP)• Command set: ONFI NAND Flash Protocol• Advanced command set

– Program page cache mode3

– Read page cache mode 3

– One-time programmable (OTP) mode– Two-plane commands 3

– Interleaved die (LUN) operations– Read unique ID– Block lock (1.8V only)– Internal data move

• Operation status byte provides software method for detecting– Operation completion– Pass/fail condition– Write-protect status

• Ready/Busy# (R/B#) signal provides a hardware method of detecting operation com-pletion

• WP# signal: Write protect entire device• First block (block address 00h) is valid when shipped from factory with ECC; for mini-

mum required ECC, see Error Management• Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000• RESET (FFh) required as first command after power-on• Alternate method of device initialization (Nand_Init) after power-up (contact factory)• Internal data move operations supported within the plane from which data is read• Quality and reliability

– Data retention: 10 years JEDEC JESD47G-compliant– Endurance: 100,000 PROGRAM/ERASE cycles

• Operating voltage range– VCC: 2.7–3.6V– VCC: 1.7–1.95V

• Operating temperature– Commercial: 0°C to +70°C– Industrial (IT): –40ºC to +85ºC

Notes: 1. The ONFI 1.0 specification is available at www.onfi.org.


137-Ball NAND Flash with LPDDR MCP2Gb: x8, x16 NAND Flash Memory



http://www.onfi.org

2. See Electrical Specifications – Program/Erase Characteristics (page 118) for tR_ECC andtPROG_ECC specifications.

3. These commands supported only with ECC disabled.

General DescriptionMicron NAND Flash devices include an asynchronous data interface for high-perform-ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfercommands, address, and data. There are five control signals used to implement theasynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals controlhardware write protection and monitor device status (R/B#).

This hardware interface creates a low pin-count device with a standard pinout that re-mains the same from one density to another, enabling future upgrades to higher densi-ties with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one ormore NAND Flash die. A NAND Flash die is the minimum unit that can independentlyexecute commands and report status. A NAND Flash die, in the ONFI specification, isreferred to as a logical unit (LUN). There is at least one NAND Flash die per chip enablesignal. For further details, see Device and Array Organization.

This device has an internal 4-bit ECC that can be enabled using the GET/SET features.See Internal ECC and Spare Area Mapping for ECC for more information.


137-Ball NAND Flash with LPDDR MCPGeneral Description



ArchitectureThese devices use NAND Flash electrical and command interfaces. Data, commands,and addresses are multiplexed onto the same pins and received by I/O control circuits.The commands received at the I/O control circuits are latched by a command registerand are transferred to control logic circuits for generating internal signals to control de-vice operations. The addresses are latched by an address register and sent to a row de-coder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or wordby word (x16), through a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operationsand is erased using block-based operations. During normal page operations, the dataand cache registers act as a single register. During cache operations, the data and cacheregisters operate independently to increase data throughput. The status register reportsthe status of die operations.

Figure 7: NAND Flash Die (LUN) Functional Block Diagram

Address register

Data register

Cache register

ECC

Status register

Command register

CE#

VCC VSS

CLE

ALE

WE#

RE#

WP#

LOCK1

I/Ox

Controllogic

I/Ocontrol

R/B#

Ro

w d

eco

de

Column decode

NAND Flasharray

(2 planes)

Note: 1. The LOCK pin is used on the 1.8V device.


137-Ball NAND Flash with LPDDR MCPArchitecture



Device and Array Organization

Figure 8: Array Organization – MT29F2G08 (x8)

Cache Register

Data Register

1024 blocksper plane

2048 blocksper device

1 block 1 block

1 page = (1K + 32 words)

1 block = (1K + 32) words x 64 pages = (64K + 2K) words

1 plane = (64K + 2K) words x 1024 blocks = 1056Mb

1 device = 1056Mb x 2 planes = 2112Mb

Plane of even-numbered blocks

(0, 2, 4, 6, ..., 2044, 2046)

Plane of odd-numbered blocks

(1, 3, 5, 7, ..., 2045, 2047)

321024 32

1056 words

DQ0

DQ15

1056 words

32321024

1024

1024

Table 8: Array Addressing – MT29F2G08 (x8)

Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW CA11 CA10 CA9 CA8

Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Fifth LOW LOW LOW LOW LOW LOW LOW BA16

Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-dress; PAx = page address; BAx = block address.

2. If CA11 is 1, then CA[10:6] must be 0.3. BA6 controls plane selection.


137-Ball NAND Flash with LPDDR MCPDevice and Array Organization



Figure 9: Array Organization – MT29F2G16 (x16)

Cache Register

Data Register

1024 blocksper plane

2048 blocksper device

1 block 1 block

1 page = (1K + 32 words)

1 block = (1K + 32) words x 64 pages = (64K + 2K) words

1 plane = (64K + 2K) words x 1024 blocks = 1056Mb

1 device = 1056Mb x 2 planes = 2112Mb

Plane of even-numbered blocks

(0, 2, 4, 6, ..., 2044, 2046)

Plane of odd-numbered blocks

(1, 3, 5, 7, ..., 2045, 2047)

321024 32

1056 words

DQ0

DQ15

1056 words

32321024

1024

1024

Table 9: Array Addressing – MT29F2G16 (x16)

Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00

First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8

Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Fifth LOW LOW LOW LOW LOW LOW LOW LOW BA16

Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-dress; PAx = page address; BAx = block address.

2. If CA10 = 1, then CA[9:5] must be 0.3. BA6 controls plane selection.


137-Ball NAND Flash with LPDDR MCPDevice and Array Organization



Asynchronous Interface Bus OperationThe bus on the device is multiplexed. Data I/O, addresses, and commands all share thesame pins. I/O[15:8] are used only for data in the x16 configuration. Addresses andcommands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address inputcycles, and one or more data cycles, either READ or WRITE.

Table 10: Asynchronous Interface Mode Selection

Mode1 CE# CLE ALE WE# RE# I/Ox WP#

Standby2 H X X X X X 0V/VCCCommand input L H L H X H

Address input L L H H X H

Data input L L L H X H

Data output L L L H X X

Write protect X X X X X X L

Notes: 1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIHor VIL.

2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGHand the device enters standby mode. The memory will enter standby if CE# goes HIGHwhile data is being transferred and the device is not busy. This helps reduce power con-sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-chronous memory bus as other Flash or SRAM devices. Other devices on the memorybus can then be accessed while the NAND Flash is busy with internal operations. Thiscapability is important for designs that require multiple NAND Flash devices on thesame bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signalsignifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, somecommands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), areaccepted by die (LUNs) even when they are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a commandis issued.


137-Ball NAND Flash with LPDDR MCPAsynchronous Interface Bus Operation



Figure 10: Asynchronous Command Latch Cycle

WE#

CE#

ALE

CLE

I/Ox COMMAND

tWP

tCHtCS

tALH

tDHtDS

tALS

tCLHtCLS

Don’t Care





Asynchronous Addresses

An asynchronous address is written from I/O[7:0] to the address register on the risingedge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.

Bits that are not part of the address space must be LOW (see Device and Array Organiza-tion). The number of cycles required for each command varies. Refer to the commanddescriptions to determine addressing requirements.

Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, someaddresses are accepted by die (LUNs) even when they are busy; for example, like ad-dress cycles that follow the READ STATUS ENHANCED (78h) command.

Figure 11: Asynchronous Address Latch Cycle

WE#

CE#

ALE

CLE

I/Ox Coladd 1

tWP tWH

tCS

tDHtDS

tALStALH

tCLS

Coladd 2

Rowadd 1

Rowadd 2

Rowadd 3

Don’t Care Undefined

tWC





Asynchronous Data Input

Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the risingedge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.

Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data iswritten to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,and the device is not busy.

Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.

Figure 12: Asynchronous Data Input Cycles

WE#

CE#

ALE

CLE

I/Ox

tWP tWP tWP

tWH

tALS

tDHtDS tDHtDS tDHtDS

tCLH

tCH

DIN M+1 DIN N

Don’t Care

tWC

DIN M





Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supportedfollowing a READ operation from the NAND Flash array. Data is output from the cacheregister of the selected die (LUN) to I/O[7:0] on the falling edge of RE# when CE# isLOW, ALE is LOW, CLE is LOW, and WE# is HIGH.

If the host controller is using a tRC of 30ns or greater, the host can latch the data on therising edge of RE# (see the figure below for proper timing). If the host controller is usinga tRC of less than 30ns, the host can latch the data on the next falling edge of RE#.

Using the READ STATUS ENHANCED (78h) command prevents data contention follow-ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-HANCED (78h) command, to enable data output, issue the READ MODE (00h) com-mand.

Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-er, it is possible to output data from the status register even when a die (LUN) is busy byfirst issuing the READ STATUS or READ STATUS ENHANCED (78h) command.

Figure 13: Asynchronous Data Output Cycles

CE#

RE#

I/Ox

tREHtRP

tRR tRC

tCEA

tREA tREA tREA

Don’t Care

tRHZ

tCHZ

tRHZ

tRHOH

RDY

tCOH

DOUT DOUT DOUT





Figure 14: Asynchronous Data Output Cycles (EDO Mode)

DOUT DOUT DOUT

CE#

RE#

I/Ox

RDY

tRR

tCEA

tREA

tRP tREH

tRC

tRLOH

tREA

tRHOH

tRHZ

tCOH

tCHZ

Don’t Care

Write Protect#

The write protect# (WP#) signal enables or disables PROGRAM and ERASE operationsto a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. WhenWP# is HIGH, PROGRAM and ERASE operations are enabled. When WP# is LOW or tog-gled LOW during a READ operation, read will be performed as normal. It is recommen-ded that the host drive WP# LOW during power-on until V CC is stable to prevent inad-vertent PROGRAM and ERASE operations (see Device Initialization for additional de-tails).

If WP# is toggled during PROGRAM or ERASE (while RB# is LOW), then the followingwill occur

• The PROGRAM or ERASE operation is aborted• In asynchronous mode, toggling WP# LOW during a NAND PROGRAM or ERASE op-

eration will act like a RESET (FFh) command. In synchronous mode, it will act like aSYNCHRONOUS RESET (FCh) command

• The data that was being programmed or erased (targeted page or block) is not validanymore

• The status register will be set to 60h until a RESET, new operation, or new power upcommand is given

After a command sequence is complete and the target is ready, WP# can be transi-tioned. After WP# is transitioned, the host must wait tWW before issuing a new com-mand.

The WP# signal is always an active input, even when CE# is HIGH. This signal shouldnot be multiplexed with other signals.





Ready/Busy#

The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-get is ready or busy. A target is busy when one or more of its die (LUNs) are busy(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because eachdie (LUN) contains a status register, it is poss

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137-Ball NAND Flash with LPDDR MCP · 2020. 9. 21. · NAND Flash with Mobile LPDDR 137-Ball MCP MT29C2G24MAAAAKAKD-5 IT, MT29C2G24MAABAKAKD-5 IT, MT29C2G24MAAAAKAHH-5 AIT Features