2004 35lh Annual IEEE Power Elecrronics Specialisrs Conference Aachen. Germany, 2004

A New Four-Level PWM Inverter Topology for Hihg Power Applications-Effect of Switching Strategies on Power Losses Distribution

G.S.Perantzakis, F.H. Xepapas, S.N.Manias

NATIONAL TECHNICAL UNIVERSITY OF ATHENS Department of Electrical and Computer Engineering Laboratory of Electrical Machines

Athens Greece1 Tel.:+301-772-3503, Fax.: +301-772-3593 Email: manias@central.ntua.gr

Absfract-In this paper a novel four-level Pulse Width Modulation (PWM) hybrid inverter topology is proposed which is composed of a conventional two-level and a three-level Neutral Point Clamped (NPC) inverter suitable for high- voltage power applications. The proposed topology when it is compared to the conventional four-level NPC PWM inverter exhibits the following advantages: (a) ability of changing the losses distribution profile among the devices by selecting the suitable switching strategy, (b) reduction of total inverter power semiconductor device losses, (e) ability of bidirectional operation of all switches, (d) series connected clamping diodes are not needed and (e) flexibility of using existing power semiconduetor modules that makes simple the implementation of the proposed power topology. Moreover, the effect of different switching strategies on the conduction and switching losses profde of the proposed inverter is examined by varying the index modulation depth and the load power factor. A suitable losses calculation method for hybrid multilevel inverter is used and a comparison of losses distribution profiles between the proposed inverter and the conventional four -level inverter is carried out. Finally, the theoretical results are confirmed by simulation and experimental resnlts.

I. INTRODUCTION The transformerless multilevel inverters when are

compared with the conventional two-level inverters exhibit higher output voltage with the same device ratings, lower harmonic content and lower EM1 (ElectroMagnetic Interference) levels [ l]-[3]. The proposed four-level PWM inverter (fig. 1) is a combination of a conventional two-level inverter and a three-level NPC inverter, which can be used in HVDC transmission systems, AC drives and renewable energy conversion systems.

As it can be seen from fig. 1, the clamped diodes of the NPC part have been replaced by active switches (IGBTs, MCTs, GTOs, e.t.c.), thus giving the ability of bidirectional operation of all switches. Selecting the suitable switching strategy a well-distributed losses dissipation among the devices can be obtained. This fact allows better utilization of power devices permitting greater power supply per switch. This ability of alternative switching strategies is an inherent advantage of the proposed inverter. In addition, by using the proposed scheme a reduction of total power semiconductor losses is achieved under the same load and dc-bus voltage, when it is compared with the conventional NPC four-level inverter. The problem of selecting clamped diodes with higher reverse voltage blocking rating, as it is required for conventional NPC inverter, is avoided because clamping diodes are not needed in the proposed topology.

phase -a phase-b phase- iwener

Fig. I. Thc proposcd thrcc-phasc 4-lcvel hybrid invcrlcr.

11. OPERATION

Each phase leg of the proposed inverter is composed of eight active switches (IGBTs), thus ensuring bidirectional operation in all positions. The switches SXI to Sx6 are used for the implementation of a conventional three-level NPC inverter, while the switches Sxi and Sx8 are used for the implementation of a conventional two-level inverter, where x = a,b,c, are the three phases. The input dc-bus voltage is split into four bulk capacitors C,, C1, C,, C4 and each capacitor is charged to a voltage V,,l4. The modulation method used in the proposed inverter is a carrier-based Sinusoidal PWM (SPWM), which is shown in fig. 2. As it can be seen from fig. 2, the three high frequency triangular carrier waveforms are contiguous in-phase disposition arrangement, while the three sine modulating waves v, are phase shifted to each other by 120 degrees and are expressed by the following equation

= mod. index 5 I (2) Am

4,” + 4 . m + Ac,l Where: m, =

m f = 2 = frequency ratio =39 (3)

A,= modulating wave peak-to-peak amplitude fm= modulating wave frequency = SO Hz

A,, , , A,,, A , , = upper, medium and lower carrier waves peak-to-peak amplitudes

f , = carrier wave frequency = 1950 Hz.

0-7803-8399-0/04/$20.00 02004 IEEE. 4398

2004 351h Annual IEEE Power Electronics Specialisrs Conference

When the modulating wave is compared with the upper triangle signal, transitions between voltage levels (+Vd&’) and (+V&) are obtained, while when it is compared with middle and lower triangles transitions between (+V&), (- V&) and (- Vd&) , (- Vd&’) are respectively obtained. In the proposed inverter there is a freedom of selecting different switching pattern combinations, thus allowing different losses distribution profiles on the devices to be achieved.

.- . iW-1,* ~.._I-”..I re,* ..___ ~

Fig. 2. Thc proposed 4-lcvcl multilevel invcrter carrier bands and modulation wave for Dhasc a.

Table 1 presents the possible alternative switch combinations in order to achieve a particular voltage level. Note that there exist four combinations for obtaining the middle voltage levels (+I’d&, - V&), thus giving freedom as to which combination can be used. From these combinations, eighteen different switching strategies are obtained which are presented in Appendix I.

TABLE I ALTERNATIVE SWITCH COMBINATIONS

The main concern is to find out the switching strategy that will exhibit the smallest losses standard deviation value among the inverter devices. According to fig. 3, this is the 9Ih switching strategy which has a standard deviation value of 8.09 (W). From here on, this switching strategy will be used for taking simulation and experimental results. For the same load, modulation index and dc bus voltage, the conventional NPC four-level inverter exhibits a losses standard deviation value of 17.94 (W), which is about twice the value of the proposed inverter.

~

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Switch Pair Losses Standart Deviation Per Switcing Strategy 20.00 >

1 2 3 4&Ri& &&@l 12 13 14 15 16 17 18

Fig. 3. Standard deviation of device losscs values oer switching shateev.

For comparison reasons, the per phase losses profiles of the proposed inverter and the conventional one are presented in figs. 4 and 5 respectively. Examining figs. 4 and 5 , it can he seen that the proposed topology has a better losses distribution profile than the conventional NPC four-level inverter.

Switching strategy 9 - 60 I

Fig. 4. Losses distribution profile of the proposed inverter using switching strategy 9.

4-level conventional NPC inverter

Fig. 5. Losses dislribution profile of the conventional NPC four-level inverter.

111. INVERTER LOSSES

lo. multilevel inverters, unlike two-level inverters, the losses of each semiconductor device is different fkom one another and depends on the duty ratio of the device, the number of output voltage level and the depth of modulation index [4].

The switching states for each phase of the proposed hybrid and conventional NPC four-level inverters are presented in Tables I1 and 111 respectively. Moreover, fig. 6 shows a phase leg of the conventional NPC four-level inverter.

In the under consideration four-level inverters there are three voltage regions, which are defined by the adjacent output voltage levels. That is, the regions 1, 2 and 3 are located between the voltage levels Vdct2 and V,, , vdd4 and - Vdd4 , -Vddg and -Vdc/2 respectively. Using fig. 7, the switch duty ratio for each region and voltage level can be calculated and the results are summarized in Table IV.

2004 35lh A n n u l IEEE Power Electronics Specialisrs Conference Aachen, Germany, 2 w 4

-vdIp

TABLE I1 SWITCHIN0 STATES OF THE PROPOSED 4-LEVEL INVERTEX g on

off

TABLE 111 SWITCHING STATES OF THE CONVENTIONAL NPC &LEVEL MVERTER

V d W I I

.e a

0

TABLEIV SWITCH DUTY RATIOS FOR EACH VOLTAGE LEVEL A N 0 REGION

Voltage Switch Duty Ratios

(+Vdd,) DR,,dc12 = - l + 2 m a cos0

LCVCl

The conduction and switching losses are initially calculated analytically and then are verified by simulation results. For power losses calculation, the static characteristics of the inverter semiconductor devices are considered and the current is assumed to be sinusoidal, which is an accepted approximation when the frequency ratio is greater than 15 (here is S,=39)[4]. The average conduction (Pcond.) and switching (Pxw.) losses of a device are calculated using the following equations

Where:

iL = Imaxmu cos ( - 1 0 'p (6 ) = the fundamental load current

(7)

+-w I Fig. 1. Switch duty ratio dctcrmination for each voltage lcvcl

= the fundamental output phase voltage Oc,, O,, = the angles that define the beginning and

e,,, e,, =the angles that define the beginning and

Vdb = the device blocking voltage D = the duty ratio of the output phase voltage pulse I,-= the maximum load current V, , r, = the threshold voltage and the dynamic

T,. I,, too= the inverter switching period and the

the end of an interval with conduction losses

the end of an interval with switching losses

resistance of the device respectively

turn-on- and turn-off times of the device respectively

e = w, f = 2nf,1 p = the load power factor angle

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2004 351k Annual IEEE Power Electronics Specialists Conference A a c k n , Germany, 2004

The duty ratio of each conducting device depends on the values of the load power factor, the modulation index a?d the output voltage level. Fig. 8 shows an example of determining the conducting devices in relation to fundamental output phase voltage and load current for cosrp=0.2 and m,=0.6. Similar diagrams are constructed for each load power factor and modulation index separately, in order to determine the conducting devices and their corresponding duty ratios.

I . ' '1 *"'a ' ' v, ' ' WF.=."asl

Fig. 8. Conducting dcvices for one fundamental period with m,=0.6 and eosrp-0.2.

IV. SIMULATION, THEORETICAL AND EXPERIMENTAL RESULTS

A . Simulation and theoretical results of device losses As it was shown in Section 11, under the same load and

dc-bus voltage conditions, the losses distribution among the devices of the proposed inverter is more uniform than the conventional NPC four-level inverter. Referring to fig. 5, it is recognized that in the conventional inverter the 65% of total device losses are exclusively created by the switches (So2 +DJ, (S, CO3), (Sa4 +D4) and (So> +Dj), while the remaining amount is created by the switches (Sa/ +DI), (So( +Dd), (0,) and (D,O/. This is due to the fact that the switches 2 to 5 (fig. 6) conduct during all the four output voltage levels, while the switches I and 2 conduct only during the voltage levels +Vd& and -VdJ2. On the contrary, in the proposed inverter (fig. 4) the 35% of total losses are created by the switches (S, +DJ and (S, +DJ, while the remaining losses amount is nearly uniformly distributed among the rest devices.

The power semiconductor losses of the proposed inverter have been calculated by considering inductive load power factors : 0.0, 0.2, 0.5, 0.8 and 1.0, while the modulation index is changed from 0.1 to 1 .O. The working parameters are listed in Table V. The theoretical and simulation results

TABLE V WORKING PARAMETERS FOR THEORETICAL AND

SIMULATION RESULTS I .. I ^^^ ,. .,

a 5 Ohms

I

for switches (S,,+D,), (Sa~+D2), (S03+D3), (S03+Dj) and (S,,+D7) are presented in Appendix 11. As it can be seen, the theoretical results are in good agreement with the simulation results and thus the losses calculation method used for the proposed hybrid multilevel inverter is verified. From the results it is concluded that: (a) for power factors from 0.0 to 0.8 and modulation index smaller than 0.6, the device losses increase with increasing the modulating index, while it is independent fiom the power factor value, (h) for modulation index greater than 0.6 the losses vary from device to device and are depended on the power factor value, (c) for unity power factor the losses increase with increasing the modulation index for switches Sal to Sa4, while remain nearly unchanged for all the other switches.

A comparison of the device losses between the proposed and the conventional NPC four-level inverter for 0.8 inductive power factor is presented in fig. 9. From fig. 9, it is noticed that the conventional inverter for modulation index greater than 0.6 exhibits higher semiconductor losses than the proposed inverter, which reaches to 18% for unity modulation index.

Total losses comparison

400,O -1

ma +Hybrid inv. +Conv.inv.

Fig. 9. Comparison of total power semiconductor losses between thc proposcd and Le convcntional inverters

for cosp4.8 (ind.).

B. Simulation and experimental results of output waveforms The operation of the proposed hybrid inverter is

confirmed by a single phase laboratory prototype. The proposed inverter was implemented using IGBTs type HGTGIONIZOBND, the dc-bus voltage of 400 (V), modulation index 0.8 and inductive load 160 (Ohms) with power factor 0.9. The gating signals are implemented in Matlab and contact with real time by an VO card of Quancer (MultiQ-3). Fig. 10 presents the simulation results.

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2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004

............. *j .... .. .&. ................ ........... iL .......... i,

(b)

~#

1- ._

-. .... /._ /”.. *.”. ..~. I . 0 . ,y . .._. ,_. ..~, ”- . ”,,- .-,

Fig. IO. Simulation resulls oE (a) outpuf phase voltage, (b) line-to-line

specmm ofthe proposcd invertw (m,=l.O, m ~ 3 9 ) . outpul voltagc and load eumnt, (c) line-tdine output volegc

. .

(b) Fig. 11. Expximental results of: (a) output phase volwge,@) load

eumnt of the proposed invcncr ( 100 Vldiv, 0.5 Ndiv).

As expected, harmonics are centered around the switching frequency and the triple harmonics in the line-to- line voltage has been disappeared (and thus the harmonic at 1950 Hz).

: . . . . . . . . . : :

: :

. . . ”.

. . .

(4 ............................................... .” . . . . . . . . . . . . . . . . . .

( 4 Fig. 12. Experimcnlal rcsults of the blocking volragc

and eolleclor current for IGBTs Sa? (a,b) and S,, (c,d)(100 Vidiv, I Aldiv).

The peak line-to-line fundamental voltage is given by the same equation as in conventional inverter

The experimental results of output phase voltage and load current are presented in Fig. 1 I , while a sample of blocking voltage and collector current for IGBTs So, and S, are shown in Fig. 12. By referring to Figure 11, we can see that there is agreement between simulation and experimental results, while the correct switch operation of the prototype is verified from the sample waveforms in Fig. 12.

v. CONCLUSION

In this paper was presented a novel four-level PWM hybrid inverter topology composed of a conventional two-

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2004 35rk Annual IEEE Power Elecrronics Specialisrs Conference Aachen. Cermny. 2004

level and a conventional three-level NPC inverter. The proposed scheme, which is suitable for high-voltage high- power applications, was compared to the conventional NPC four-level inverter and it was found that exhibits the following advantages: (a) better losses distribution profile among the power semiconductor devices, (b) up to 18% lower semiconductor devices losses when operating with modulation index above 0.6, ( c ) ability of bidirectional operation of all power semiconductor devices, thus permitting the inverter to operate with Zero Current Switching (ZCS) and (d) there is no need for clamping diodes. However, the proposed inverter uses two additional active switches. It was verified that the theoretical results, obtained using the power losses calculation method for the

simulation ones. Finally, there was a good agreement between experimental and simulation resulls of the proposed

APPENDIX I(Continued)

APPENDIX I I

Losses of S a l + D l +wsphi=

-0-wsphi=

proposed hybrid inverter, were in close agreement with the 1.0

0.6 60.0 .^ ~ 1 inverter.

APPENDIX I

SWITCH COMBINATIONS OF POSSIBLE SWITCHING STRATEGIES

Volt. Lev. SalSa2

I

g 4U.U +wsphi=

0.0 %cosphi=

2 20.0 0.5

0.2 -. 0. 9 -. oi 0 0 0 0 0

-*Cmsphi= 0.0 ma

Losses of Sa2+D2 80.0 3

60.0 40.0

0.0 = 20.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.6 0.9 1

ma

Losses of Sa3+D3

60.0 % 40.0 5 20.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.6 0.9 1

ma

Losses of Sa5+D5

60.0 7 2 40.0

0.0 I 20.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.6 0.9 1 ma

'ig. 13 . Theoretical results ofpower losscs afdevices (S,,+DJ, (SL+DJ. (S,,+Dr), (S.,+DJ and (S.,+D,)of thc prapased invcrtcr.

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2004 35rk A n n u l IEEE Power Elecrronics Speciolisrs Conjerunce Aachen. Germany. 2004

Losses of Sa7+D7

3 40.0 60’o 3

I s 20.0

O . O . , , , I I , , , , 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

ma

60.0

g 40.0

E 20.0

0.0

Losses of Sa5+D5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ma

Fig. 13. (Continued)

Losses of Sa7+D7

Losses of Sal+Dl -cosphi- r n . -

60.0 -cosphi=

2 20.0 -cosphi=

0.0 *cosphi=

g 40.0 0.8

0.5

0.2 -. 0. -. c. 9 0 0 0 0 0

ma

Losses of Sa2+D2

-cosphi= 0.0

en n ~

60.0 q 40.0

0.0

2 2 20.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ma

Losses of Sa3+D3

8 60.0 I6 40.0

0.0 2 20.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ma

60.0

y) 40.0 E 9 20.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

ma

Fig. 14. (Continucd)

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