128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAMglacier.lbl.gov/.../MT48V4M32LFFC-8-128Mbx16x32.pdf · 2003. 4. 1. · 128Mb: x16, x32 MOBILE SDRAM 09005aef808ebf65 Micron Technology,

128Mb: x16, x32MOBILE SDRAM

SYNCHRONOUS DRAM

09005aef808ebf65128Mbx16x32.fm - Rev. G 3/03 EN 1

MT48LC8M16LFFF, MT48V8M16LFFF - 2 MEG X 16 X 4 BANKS MT48LC4M32LFFC, MT48V4M32LFFC - 1 MEG X 32 X 4 BANKS

For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds

FEATURES• Temperature Compensated Self Refresh (TCSR)• Fully synchronous; all signals registered on positive

edge of system clock• Internal pipelined operation; column address can

be changed every clock cycle• Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page• Auto Precharge, includes CONCURRENT auto

precharge, and Auto Refresh Modes• Self Refresh Mode; standard and low power• 64ms, 4,096-cycle refresh• LVTTL-compatible inputs and outputs• Low voltage power supply• Partial Array Self Refresh power-saving mode

Part Number Example:

MT48V8M16LFFF-8

*CL = CAS (READ) latency

OPTIONS MARKING

• VDD/VDDQ3.3V/3.3V LC2.5V/2.5V or 1.8V V

• Configurations8 Meg x 16 (2 Meg x 16 x 4 banks) 8M164 Meg x 32 (1 Meg x 32 x 4 banks) 4M32

• Package/Ball out54-ball FBGA (8mm x 9mm )1

NOTE:

1. x16 Only.

FF54-ball FBGA (8mm x 9mm )1 Lead-Free BF90-ball FBGA (11mm x 13mm)2

2. x32 Only.

FC90-ball FBGA (11mm x 13mm)2 Lead-Free BC

• Timing (Cycle Time)8ns @ CL = 3 (125 MHz) -810ns @ CL = 3 (100 MHz) -10

• TemperatureCommercial (0°C to +70°C) NoneIndustrial (-40°C to +85°C) IT

8 Meg x 16 4 Meg x 32

Configuration 2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks

Refresh Count 4K 4K

Row Addressing 4K (A0–A11) 4K (A0–A11)

Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1)

Column Addressing 512 (A0–A8) 256 (A0–A7)

KEY TIMING PARAMETERS

SPEEDGRADE

CLOCKFREQUENCY

ACCESS TIME

tRCD tRPCL=1* CL=2* CL=3*

-8 125 MHz – – 6ns 20ns 20ns-10 100 MHz – – 6ns 20ns 20ns-8 100 MHz – 7ns – 20ns 20ns

-10 83 MHz – 7ns – 20ns 20ns-8 50 MHz 18ns – – 20ns 20ns

-10 40 MHz 18ns – – 20ns 20ns

A

B

C

D

E

F

G

H

J

1 2 3 4 5 6 7 8

Top View(Ball Down)

VSS

DQ14

DQ12

DQ10

DQ8

UDQM

NC/A12

A8

VSS

DQ15

DQ13

DQ11

DQ9

NC

CLK

A11

A7

A5

VSSQ

VDDQ

VSSQ

VDDQ

VSS

CKE

A9

A6

A4

VDDQ

VSSQ

VDDQ

VSSQ

VDD

CAS#

BA0

A0

A3

DQ0

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

A1

A2

VDD

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

VDD

9

Figure 1: PIN ASSIGNMENT (Top View)54-Ball FBGA

©2003 Micron Technology, Inc.

http://www.micron.com/dramds


Figure 2: 90-Ball FBGA Pin Assignment (Top View)

1 2 3 4 6 7 8 95

DQ26

DQ28

VSSQ

VSSQ

VDDQ

VSS

A4

A7

CLK

DQM1

VDDQ

VSSQ

VSSQ

DQ11

DQ13

DQ24

VDDQ

DQ27

DQ29

DQ31

DQM3

A5

A8

CKE

NC

DQ8

DQ10

DQ12

VDDQ

DQ15

VSS

VSSQ

DQ25

DQ30

NC

A3

A6

NC

A9

NC

VSS

DQ9

DQ14

VSSQ

VSS

VDD

VDDQ

DQ22

DQ17

NC

A2

A10

NC

BA0

CAS#

VDD

DQ6

DQ1

VDDQ

VDD

DQ21

DQ19

VDDQ

VDDQ

VSSQ

VDD

A1

A11

RAS#

DQM0

VSSQ

VDDQ

VDDQ

DQ4

DQ2

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

A0

BA1

CS#

WE#

DQ7

DQ5

DQ3

VSSQ

DQ0

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Ball and Array

09005aef808ebf65 Micron Technology, Inc., reserves the right to change products or specifications without notice.128Mbx16x32.fm - Rev. G 3/03 EN 2 ©2003 Micron Technology. Inc.


General DescriptionThe Micron® 128Mb SDRAM is a high-speed

CMOS, dynamic random-access memory containing134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signalsare registered on the positive edge of the clock signal,CLK). Each of the x16’s 33,554,432-bit banks is orga-nized as 4,096 rows by 512 columns by 16 bits. Each ofthe x32’s 33,554,432-bit banks is organized as 4,096rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst ori-ented; accesses start at a selected location and con-tinue for a programmed number of locations in aprogrammed sequence. Accesses begin with the regis-tration of an ACTIVE command, which is then fol-lowed by a READ or WRITE command. The addressbits registered coincident with the ACTIVE commandare used to select the bank and row to be accessed(BA0, BA1 select the bank; A0-A11(x16) or A0-A10(x32)select the row). The address bits registered coincidentwith the READ or WRITE command are used to selectthe starting column location for the burst access.

The SDRAM provides for programmable read orwrite burst lengths of 1, 2, 4, or 8 locations, or the fullpage, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed rowprecharge that is initiated at the end of the burstsequence.

The 128Mb SDRAM uses an internal pipelinedarchitecture to achieve high-speed operation. Thisarchitecture is compatible with the 2n rule of prefetcharchitectures, but it also allows the column address tobe changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bankwhile accessing one of the other three banks will hidethe precharge cycles and provide seamless high-speed,random-access operation.

The 128Mb SDRAM is designed to operate in 3.3V or2.5V low-power memory systems. An auto refreshmode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-com-patible.

SDRAMs offer substantial advances in DRAM oper-ating performance, including the ability to synchro-nously burst data at a high data rate with automaticcolumn-address generation, the ability to interleavebetween internal banks in order to hide prechargetime and the capability to randomly change columnaddresses on each clock cycle during a burst access.

Table 1: 128Mb SDRAM Part Numbers

PART NUMBER VDD/VDDQ ARCHITECTURE PACKAGE

MT48LC8M16LFFF-xx 3.3V / 3.3V 8 Meg x 16 54-BALL FBGAMT48V8M16LFFF-xx 2.5V / 2.5V - 1.8V 8 Meg x 16 54-BALL FBGAMT48LC4M32LFFC-xx 3.3V / 3.3V 4 Meg x 32 90-BALL FBGAMT48V4M32LFFC-xx 2.5V / 2.5V - 1.8V 4 Meg x 32 90-BALL FBGA



Figure 3: Functional Block Diagram 8 Meg x 16 SDRAM

12

RAS#

CAS#

ROW-ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROLLOGIC

COLUMN-ADDRESSCOUNTER/

LATCH

MODE REGISTER

9

CO

MM

AN

D

DEC

OD

E

A0-A11,BA0, BA1

DQML,DQMH12

ADDRESSREGISTER

14

512(x16)

4096

I/O GATINGDQM MASK LOGICREAD DATA LATCH

WRITE DRIVERS

COLUMNDECODER

BANK0MEMORY

ARRAY(4,096 x 512 x 16)

BANK0ROW-

ADDRESSLATCH

&DECODER

4096

SENSE AMPLIFIERS

BANKCONTROL

LOGIC

DQ0-DQ15

16

16DATAINPUT

REGISTER

DATAOUTPUTREGISTER

16

12

BANK1BANK2

BANK3

12

9

2

2 2

2

REFRESHCOUNTER

BA1 BA0 Bank0 0 00 1 11 0 21 1 3



Figure 4: Functional Block Diagram 4 Meg x 32 SDRAM

12

RAS#

CAS#

CLK

CS#

WE#

CKE

8

A0–A11,BA0, BA1

DQM0–DQM3

14

256(x32)

8192

I/O GATINGDQM MASK LOGICREAD DATA LATCH

WRITE DRIVERS

COLUMNDECODER

BANK0MEMORY

ARRAY(4,096 x 256 x 32)

BANK0ROW-

ADDRESSLATCH

&DECODER

4096

SENSE AMPLIFIERS

BANKCONTROL

LOGIC

DQ0– DQ31

32

32DATAINPUT

REGISTER

DATAOUTPUTREGISTER

32

BANK1BANK0

BANK2BANK3

12

8

2

4 4

2

REFRESHCOUNTER

12

12

MODE REGISTER

CONTROLLOGIC

CO

MM

AN

D

DEC

OD

E

ROW-ADDRESS

MUX

ADDRESSREGISTER

COLUMN-ADDRESSCOUNTER/

LATCH

BA1 BA0 Bank0011

0101

0123



Table 2: Ball Descriptions: 54-Ball FBGA

54-BALL FBGA SYMBOL TYPE DESCRIPTION

F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

F3 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

G9 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

F7, F8, F9 CAS#, RAS#,WE#

Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered.

E8, F1 LDQM, UDQM

Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same state when referenced as DQM.

G7, G8 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command

H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2

A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2,

C1, B2, B1, A2

DQ0–DQ15 I/O Data Input/Output: Data bus

E2, G1 NC – No Connect: These pins should be left unconnected.G1 is a no connect for this part but may be used as A12 in future designs.

A7, B3, C7, D3 VDDQ Supply DQ Power: Isolated DQ power on the die to improve noise immunity.A3, B7, C3, D7, VSSQ Supply DQ Ground: Isolated DQ power on the die to improve noise immunity.

A9, E7, J9 VDD Supply Power Supply: Voltage dependant on option.A1, E3, J1 VSS Supply Ground.



Table 3: Ball Descriptions: 90-Ball FBGA

90-BALL FBGA SYMBOL TYPE DESCRIPTION

J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

J2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

J8 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

J9, K7, K8 RAS#, CAS#, WE#

Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

K9, K1, F8, F2 DQM0–3 Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. DQM0-3 are considered same state when referenced as DQM.

J7, H8 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command

G8, G9, F7, F3, G1, G2,G3, H1, H2, J3, G7, H9

A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2,

D3, E2

DQ0–DQ31 I/O Data Input/Output: Data bus

E3, E7, H3, H7, K2, K3 NC – No Connect: These pins should be left unconnected. H7 is a no connect for this part but may be used as A12 in future designs.

B2, B7, C9, D9, E1,L1, M9, N9, P2, P7

VDDQ Supply DQ Power: Isolated DQ power on the die to improve noise immunity.

B8, B3, C1, D1, E9,L9, M1, N1, P3, P8

VSSQ Supply DQ Ground: Isolated DQ power on the die to improve noise immunity.

A7, F9, L7, R7 VDD Supply Power Supply: Voltage dependant on option.A3, F1, L3, R3 VSS Supply Ground.



Functional DescriptionIn general, the 128Mb SDRAMs (2 Meg x16 x 4 banks

and 1 Meg x 32 x 4 banks) are quad-bank DRAMs thatoperate at 3.3V or 2.5V and include a synchronousinterface (all signals are registered on the positive edgeof the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by16 bits. Each of the x32’s 33,554,432-bit banks is orga-nized as 4,096 rows by 256 columns by 32bits.

Read and write accesses to the SDRAM are burst ori-ented; accesses start at a selected location and con-tinue for a programmed number of locations in aprogrammed sequence. Accesses begin with the regis-tration of an ACTIVE command, which is then fol-lowed by a READ or WRITE command. The addressbits registered coincident with the ACTIVE commandare used to select the bank and row to be accessed(BA0 and BA1 select the bank, A0-A11 select the row).The address bits ( x16: A0-A8; x32: A0-A7; ) registeredcoincident with the READ or WRITE command areused to select the starting column location for theburst access.

Prior to normal operation, the SDRAM must be ini-tialized. The following sections provide detailed infor-mation covering device initialization, registerdefinition, command descriptions and device opera-tion.

InitializationSDRAMs must be powered up and initialized in a

predefined manner. Operational procedures otherthan those specified may result in undefined opera-tion. Once power is applied to Vdd and VddQ (simulta-neously) and the clock is stable (stable clock is definedas a signal cycling within timing constraints specifiedfor the clock pin), the SDRAM requires a 100µs delayprior to issuing any command other than a COM-MAND INHIBIT or NOP. Starting at some point duringthis 100µs period and continuing at least through theend of this period, Command Inhibit or NOP com-mands should be applied.

Once the 100µs delay has been satisfied with at leastone Command Inhibit or NOP command having beenapplied, a PRECHARGE command should be applied.All banks must then be precharged, thereby placingthe device in the all banks idle state.

Once in the idle state, two AUTO refresh cycles mustbe performed. After the AUTO refresh cycles are com-plete, the SDRAM is ready for mode register program-ming. Because the mode register will power up in anunknown state, it should be loaded prior to applyingany operational command.

Register Definition

Mode RegisterIn order to achieve low power consumption, there

are two mode registers in the Mobile component,Mode Register and Extended Mode Register. For thissection, Mode Register is referred to. Extended Moderegister is discussed on 11. The mode register is usedto define the specific mode of operation of theSDRAM. This definition includes the selection of aburst length, a burst type, a CAS latency, an operatingmode and a write burst mode, as shown in Figure 5.The mode register is programmed via the LOADMODE REGISTER command and will retain the storedinformation until it is programmed again or the deviceloses power.

Mode Register bits M0-M2 specify the burst length,M3 specifies the type of burst (sequential or inter-leaved), M4-M6 specify the CAS latency, M7 and M8specify the operating mode, M9, M10, and M11 shouldbe set to zero. M12 and M13 should be set to zero toprevent extended mode register.

The mode register must be loaded when all banksare idle, and the controller must wait the specifiedtime before initiating the subsequent operation. Vio-lating either of these requirements will result inunspecified operation.

Burst LengthRead and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, asshown in Figure 5. The burst length determines themaximum number of column locations that can beaccessed for a given READ or WRITE command. Burstlengths of 1, 2, 4, or 8 locations are available for boththe sequential and the interleaved burst types, and afull-page burst is available for the sequential type. Thefull-page burst is used in conjunction with the BURSTTERMINATE command to generate arbitrary burstlengths.

Reserved states should not be used, as unknownoperation or incompatibility with future versions mayresult.

When a READ or WRITE command is issued, a blockof columns equal to the burst length is effectivelyselected. All accesses for that burst take place withinthis block, meaning that the burst will wrap within theblock if a boundary is reached. The block is uniquelyselected by A1-A8 (x16) or A1-A7 (x32) when the burstlength is set to two; by A2-A8 (x16) or A2-A7 (x32)when the burst length is set to four; and by A3-A8 (x16)



or A3-A7 (x32) when the burst length is set to eight.The remaining (least significant) address bit(s) is (are)used to select the starting location within the block.Full-page bursts wrap within the page if the boundaryis reached.

Burst TypeAccesses within a given burst may be programmed

to be either sequential or interleaved; this is referred toas the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-mined by the burst length, the burst type and the start-ing column address, as shown in Table 1.

Figure 5: Mode Register Definition

NOTE:1. For full-page accesses: y = 512 (x16), y = 256 (x32).2. For a burst length of two, A1-A8 (x16) or A1-A7 (x32)

select the block-of-two burst; A0 selects the starting col-umn within the block.

3. For a burst length of four, A2-A8 (x16) or A2-A7 (x32) select the block-of-four burst; A0-A1 select the starting column within the block.

4. For a burst length of eight, A3-A8 (x16) or A3-A7 (x32) select the block-of-eight burst; A0-A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and A0-A8 (x16) or A0-A7 (x32) select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

7. For a burst length of one, A0-A8 (x16) or A0-A7 (x32) select the unique column to be accessed, and mode reg-ister bit M3 is ignored.

10

M3 = 0

1

2

4

8

Reserved

Reserved

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

Standard Operation

All other states reserved

0

-

0

-

Defined

-

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

1

2

3

Reserved

Reserved

Reserved

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9 7 6 5 4 38 2 1 0

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6-M0M8 M7

Op Mode

A10

Reserved* WB

0

1

Write Burst Mode

Programmed Burst Length

Single Location Access

M9

*Should programM10 = “0, 0”

to ensure compatibilitywith future devices.

BA0BA1

M9 M7 M6 M5 M4 M3M8 M2 M1 M0M10

11

A11

M11M12M13

LMR

13 12

Load Mode Register

Program Mode Register

All other states reserved

0

-

0

-

M13 M12

Table 4: Burst Definition

BURSTLENGTH

ORDER OF ACCESSES WITHIN A BURST

STARTING COLUMN ADDRESS

TYPE = SEQUENTIAL

TYPE = INTERLEAVED

2 A00 0-1 0-1

1 1-0 1-04 A1 A0

0 0 0-1-2-3 0-1-2-30 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-11 1 3-0-1-2 3-2-1-0

8 A2 A1 A00 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-70 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-60 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-50 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-41 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-31 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-21 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-11 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page (y)

n = A0-A11/9/8

(location 0-y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...…Cn - 1,

Cn…

Not Supported



CAS LatencyThe CAS latency is the delay, in clock cycles,

between the registration of a READ command and theavailability of the first piece of output data. The latencycan be set to one, two, or three clocks.

If a READ command is registered at clock edge n,and the latency is m clocks, the data will be availableby clock edge n + m. The DQs will start driving as aresult of the clock edge one cycle earlier (n + m - 1),and provided that the relevant access times are met,the data will be valid by clock edge n + m. For example,assuming that the clock cycle time is such that all rele-vant access times are met, if a read command is regis-tered at T0 and the latency is programmed to twoclocks, the DQs will start driving after T1 and the datawill be valid by T2, as shown in Figure 6. Table 5 indi-cates the operating frequencies at which each CASlatency setting can be used.

Reserved states should not be used as unknownoperation or incompatibility with future versions mayresult.

Figure 6: CAS Latency

CLK

DQ

T2T1 T3T0

CAS Latency = 3

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP

T4

NOP

DON’T CARE

UNDEFINED

CLK

DQ

T2T1T0

CAS Latency = 1

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

CLK

DQ

T2T1 T3T0

CAS Latency = 2

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP



Operating ModeThe normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of valuesfor M7 and M8 are reserved for future use and/or testmodes. The programmed burst length applies to bothread and write bursts.

Test modes and reserved states should not be usedbecause unknown operation or incompatibility withfuture versions may result.

Figure 7: Extended Mode Register Table

NOTE: 1. E13 and E12 (BA1 and BA0) must be “1, 0” toselect the Extended Mode Register (vs. the baseMode Register).

2. RFU: Reserved for Future Use.

Extended Mode RegisterThe Extended Mode Register controls the functions

beyond those controlled by the Mode Register. Theseadditional functions are special features of the Mobiledevice. They include Temperature Compensated SelfRefresh (TCSR) Control, and Partial Array Self Refresh(PASR).

The Extended Mode Register is programmed via theMode Register Set command (BA1=1,BA0=0) andretains the stored information until it is programmedagain or the device loses power.

The Extended Mode Register must be programmedwith M5 through M11 set to “0”. The Extended ModeRegister must be loaded when all banks are idle and nobursts are in progress, and the controller must wait thespecified time before before initiating any subsequentoperation. Violating either of these requirementsresults in unspecified operation.

Temperature Compensated Self RefreshTemperature Compensated Self Refresh (TCSR)

allows the controller to program the Refresh intervalduring SELF REFRESH mode, according to the casetemperature of the Mobile device. This allows greatpower savings during SELF REFRESH during mostoperating temperature ranges. Only during extremetemperatures would the controller have to select aTCSR level that will guarantee data during SELFREFRESH.

Every cell in the DRAM requires refreshing due tothe capacitor losing its charge over time. The refreshrate is dependent on temperature. At higher tempera-tures a capacitor loses charge quicker than at lowertemperatures, requiring the cells to be refreshed moreoften. Historically, during Self Refresh, the refresh ratehas been set to accomodate the worst case, or highesttemperature range expected.

Thus, during ambient temperatures, the power con-sumed during refresh was unnecessarily high, becausethe refresh rate was set to accommodate the highertemperatures. Setting M4 and M3, allow the DRAM toaccomodate more specific temperature regions duringSELF REFRESH. There are four temperature settings,which will vary the SELF REFRESH current accordingto the selected temperature. This selectable refreshrate will save power when the DRAM is operating atnormal temperatures.

Table 5: CAS Latency

SPEED

ALLOWABLE OPERATING FREQUENCY (MHZ)

CASLATENCY = 1

CASLATENCY = 2

CASLATENCY = 3

- 8 � 50 � 100 � 125- 10 � 40 � 83 � 100

Maximum Case TempA4 A3

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended ModeRegister (Ex)

Address Bus

9 7 6 5 4 38 2 1 0

A10A11

101112

PASRTCSR0

13

1 All must be set to "0"

BA0

M9 M7 M6 M5 M4 M3M8 M2 M1 M0M10M11M12

BA1

M13

85˚C1 1

70˚C0 0

45˚C

15˚C

0 1

1 0

Self Refresh Coverage

Four Banks

Two Banks (Bank 0,1)

One Bank (Bank 0)

RFU

RFU

RFU

RFU

RFU

A2 A1 A0

0 00

00

00

0

0 01

1

1

1 1

1

11

0

0

111

1



Partial Array Self RefreshFor further power savings during SELF REFRESH,

the Partial Array Self Refresh (PASR) feature allows thecontroller to select the amount of memory that will berefreshed during SELF REFRESH. The refresh optionsare all banks (banks 0, 1, 2, and 3); two banks (banks 0and 1); and one bank (bank 0). WRITE and READ com-

mands occur to any bank selected during standardoperation, but only the selected banks in PASR will berefreshed during SELF REFRESH. It’s important to notethat data in banks 2 and 3 will be lost when the twobank option is used. Data will be lost in banks 1, 2, and3 when the one bank option is used.



CommandsTruth Table 1 provides a quick reference of available

commands. This is followed by a written description ofeach command. Three additional Truth Tables appearfollowing the Operation section; these tables providecurrent state/next state information.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.2. A0-A10 define the op-code written to the mode register.3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.4. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls

DQ0-7, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.

Table 6: TRUTH TABLE 1 - Commands and DQM Operation(Note: 1)

NAME (FUNCTION) CS#RAS

#CAS

# WE#DQM ADDR DQS NOTES

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH(Enter self refresh mode)

L L L H X X X 6, 7

LOAD MODE REGISTER L L L L X Op-Code X 2Write Enable/Output Enable – – – – L – Active 8Write Inhibit/Output High-Z – – – – H – High-Z 8



COMMAND INHIBITThe COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM,regardless of whether the CLK signal is enabled. TheSDRAM is effectively deselected. Operations already inprogress are not affected.

NO Operation (NOP)The NO OPERATION (NOP) command is used to

perform a NOP to an SDRAM which is selected (CS# isLOW). This prevents unwanted commands from beingregistered during idle or wait states. Operationsalready in progress are not affected.

LOAD mode registerThe mode register is loaded via inputs A0, BA0, BA1.

See mode register heading in the Register Definitionsection. The LOAD MODE REGISTER and LOADEXTENDED MODE REGISTER commands can only beissued when all banks are idle, and a subsequent exe-cutable command cannot be issued until tMRD is met.

ACTIVEThe ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. Thevalue on the BA0, BA1 inputs selects the bank, and theaddress provided on inputs A0-A11 selects the row.This row remains active (or open) for accesses until aprecharge command is issued to that bank. A pre-charge command must be issued before opening a dif-ferent row in the same bank.

READThe READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1inputs selects the bank, and the address provided oninputs A0-A8 (x16) or A0-A7 (x32) selects the startingcolumn location. The value on input A10 determineswhether or not auto precharge is used. If auto pre-charge is selected, the row being accessed will be pre-charged at the end of the read burst; if auto prechargeis not selected, the row will remain open for subse-quent accesses. Read data appears on the DQs subjectto the logic level on the DQM inputs two clocks earlier.If a given DQM signal was registered HIGH, the corre-sponding DQs will be High-Z two clocks later; if theDQM signal was registered LOW, the DQs will providevalid data.

WRITEThe WRITE command is used to initiate a burst

write access to an active row. The value on the BA0,BA1 inputs selects the bank, and the address providedon inputs A0-A8 (x16) or A0-A7 (x32) selects the start-ing column location. The value on input A10 deter-mines whether or not auto precharge is used. If autoprecharge is selected, the row being accessed will beprecharged at the end of the write burst; if auto pre-charge is not selected, the row will remain open forsubsequent accesses. Input data appearing on the DQsis written to the memory array subject to the DQMinput logic level appearing coincident with the data. Ifa given DQM signal is registered LOW, the correspond-ing data will be written to memory; if the DQM signalis registered HIGH, the corresponding data inputs willbe ignored, and a write will not be executed to thatbyte/column location.

PRECHARGEThe PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in allbanks. The bank(s) will be available for a subsequentrow access a specified time (tRP) after the prechargecommand is issued. Input A10 determines whetherone or all banks are to be precharged, and in the casewhere only one bank is to be precharged, inputs BA0,BA1 select the bank. Otherwise BA0, BA1 are treated as“Don’t Care.” Once a bank has been precharged, it is inthe idle state and must be activated prior to any READor WRITE commands being issued to that bank.

Auto PrechargeAuto precharge is a feature which performs the

same individual-bank precharge function describedabove, without requiring an explicit command. This isaccomplished by using A10 to enable auto prechargein conjunction with a specific READ or WRITE com-mand. A precharge of the bank/row that is addressedwith the READ or WRITE command is automaticallyperformed upon completion of the READ or WRITEburst, except in the full-page burst mode, where autoprecharge does not apply. Auto precharge is nonpersis-tent in that it is either enabled or disabled for eachindividual Read or Write command.

Auto precharge ensures that the precharge is initi-ated at the earliest valid stage within a burst. The usermust not issue another command to the same bankuntil the precharge time (tRP) is completed. This isdetermined as if an explicit PRECHARGE commandwas issued at the earliest possible time, as describedfor each burst type in the Operation section of thisdata sheet.



BURST TERMINATEThe BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The mostrecently registered READ or WRITE command prior tothe BURST TERMINATE command will be truncated,as shown in the Operation section of this data sheet.

AUTO REFRESHAUTO REFRESH is used during normal operation of

the SDRAM and is analogous to CAS#-BEFORE-RAS#(CBR) refresh in conventional DRAMs. This commandis nonpersistent, so it must be issued each time arefresh is required. All active banks must be PRE-CHARGED prior to issuing an AUTO REFRESH com-mand. The AUTO REFRESH command should not beissued until the minimum tRP has been met after thePRECHARGE command as shown in the operation sec-tion.

The addressing is generated by the internal refreshcontroller. This makes the address bits “Don’t Care”during an AUTO REFRESH command. The 128MbSDRAM requires 4,096 AUTO REFRESH cycles every64ms (tREF), regardless of width option. Providing adistributed AUTO REFRESH command every 15.625µswill meet the refresh requirement and ensure that eachrow is refreshed. Alternatively, 4,096 AUTO REFRESHcommands can be issued in a burst at the minimumcycle rate (tRFC), once every 64ms.

SELF REFRESHThe SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system ispowered down. When in the self refresh mode, theSDRAM retains data without external clocking. TheSELF REFRESH command is initiated like an AUTOREFRESH command except CKE is disabled (LOW).Once the SELF REFRESH command is registered, allthe inputs to the SDRAM become “Don’t Care” with theexception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM pro-vides its own internal clocking, causing it to performits own auto refresh cycles. The SDRAM must remainin self refresh mode for a minimum period equal totRAS and may remain in self refresh mode for an indef-inite period beyond that.

The procedure for exiting self refresh requires asequence of commands. First, CLK must be stable (sta-ble clock is defined as a signal cycling within timingconstraints specified for the clock pin) prior to CKEgoing back HIGH. Once CKE is HIGH, the SDRAMmust have NOP commands issued (a minimum of twoclocks) for tXSR because time is required for the com-pletion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESHcommands must be issued every 15.625µs or less asboth SELF REFRESH and AUTO REFRESH utilize therow refresh counter.



OperationBANK/ROW ACTIVATION

Before any READ or WRITE commands can beissued to a bank within the SDRAM, a row in that bankmust be “opened.” This is accomplished via theACTIVE command, which selects both the bank andthe row to be activated (seeFigure 8).

After opening a row (issuing an ACTIVE command),a READ or WRITE command may be issued to that row,subject to the tRCD specification. tRCD (MIN) shouldbe divided by the clock period and rounded up to thenext whole number to determine the earliest clockedge after the ACTIVE command on which a READ orWRITE command can be entered. For example, a tRCDspecification of 20ns with a 125 MHz clock (8nsperiod) results in 2.5 clocks, rounded to 3. This isreflected in Figure 9, which covers any case where 2 <tRCD (MIN)/tCK � 3. (The same procedure is used toconvert other specification limits from time units toclock cycles.)

A subsequent ACTIVE command to a different rowin the same bank can only be issued after the previousactive row has been “closed” (precharged). The mini-mum time interval between successive ACTIVE com-mands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bankcan be issued while the first bank is being accessed,which results in a reduction of total row-access over-

head. The minimum time interval between successiveACTIVE commands to different banks is defined bytRRD.

Figure 8: Activating a Specific Row in a Specific Bank

Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10, A11 ROWADDRESS

DON’T CARE

HIGH

BA0, BA1 BANKADDRESS

CLK

T2T1 T3T0

t

COMMAND NOPACTIVEREAD or

WRITE

T4

NOP

RCD

DON’T CARE



READsREAD bursts are initiated with a READ command, as

shown in Figure 10. The starting column and bank addresses are pro-

vided with the READ command, and auto precharge iseither enabled or disabled for that burst access. If autoprecharge is enabled, the row being accessed is pre-charged at the completion of the burst. For the genericREAD commands used in the following illustrations,auto precharge is disabled.

During READ bursts, the valid data-out elementfrom the starting column address will be available fol-lowing the CAS latency after the READ command.Each subsequent data-out element will be valid by thenext positive clock edge. Figure 11 shows general tim-ing for each possible CAS latency setting.

Figure 10: READ Command

Upon completion of a burst, assuming no othercommands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (Atthe end of the page, it will wrap to column 0 and con-tinue.)

Data from any READ burst may be truncated with asubsequent READ command, and data from a fixed-length READ burst may be immediately followed bydata from a READ command. In either case, a continu-ous flow of data can be maintained. The first data ele-ment from the new burst follows either the lastelement of a completed burst or the last desired dataelement of a longer burst that is being truncated. Thenew READ command should be issued x cycles beforethe clock edge at which the last desired data element isvalid, where x equals the CAS latency minus one.

Figure 11: CAS Latency

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMNADDRESSA0-A8

A10

BA0,1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANKADDRESS

A9, A11

CLK

DQ

T2T1 T3T0

CAS Latency = 3

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP

T4

NOP

DON’T CARE

UNDEFINED

CLK

DQ

T2T1T0

CAS Latency = 1

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

CLK

DQ

T2T1 T3T0

CAS Latency = 2

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP



This is shown in Figure 11 for CAS latencies of two andthree; data element n + 3 is either the last of a burst offour or the last desired of a longer burst. The 128MbSDRAM uses a pipelined architecture and thereforedoes not require the 2n rule associated with a prefetch

architecture. A READ command can be initiated onany clock cycle following a previous READ command.Full-speed random read accesses can be performed tothe same bank, as shown in Figure 12, or each subse-quent READ may be performed to a different bank.

Figure 12: Consecutive READ Bursts

CLK

DQ DOUT n

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,COL n

NOP

BANK,COL b

DOUTn + 1

DOUTn + 2

DOUTn + 3

DOUT b

READ

X = 0 cycles

NOTE: Each READ command may be to either bank. DQM is LOW.

CAS Latency = 1

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,COL n

NOP

BANK,COL b

DOUTn + 1

DOUTn + 2

DOUTn + 3

DOUT b

READ

X = 1 cycle

CAS Latency = 2

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS


BANK,COL n

NOP

BANK,COL b

DOUTn + 1

DOUTn + 2

DOUTn + 3

DOUT b

READ NOP

T7

X = 2 cycles

CAS Latency = 3

DON’T CARETRANSITIONING DATA



Figure 13: Random READ Accesses

CLK

DQ

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,COL n

DON’T CARE

DOUTn

DOUTa

DOUTx

DOUT m

READ

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK,COL a

BANK,COL x

BANK,COL m

CLK

DQ DOUT n

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,COL n

DOUTa

DOUTx

DOUTm

READ READ READ NOP

BANK,COL a

BANK,COL x

BANK,COL m

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK,COL n

DOUTa

DOUTx

DOUTm

READ READ READ

BANK,COL a

BANK,COL x

BANK,COL m

CAS Latency = 1

CAS Latency = 2

CAS Latency = 3

TRANSITIONING DATA



Data from any READ burst may be truncated with asubsequent WRITE command, and data from a fixed-length READ burst may be immediately followed bydata from a WRITE command (subject to bus turn-around limitations). The WRITE burst may be initiatedon the clock edge immediately following the last (orlast desired) data element from the READ burst, pro-vided that I/O contention can be avoided. In a givensystem design, there may be a possibility that thedevice driving the input data will go Low-Z before theSDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read dataand the WRITE command.

Figure 14: READ to WRITE

The DQM input is used to avoid I/O contention, asshown in Figure 14 and Figure 15. The DQM signalmust be asserted (HIGH) at least two clocks prior tothe WRITE command (DQM latency is two clocks foroutput buffers) to suppress data-out from the READ.Once the WRITE command is registered, the DQs willgo High-Z (or remain High-Z), regardless of the state ofthe DQM signal, provided the DQM was active on theclock just prior to the WRITE command that truncatedthe READ command. If not, the second WRITE will bean invalid WRITE. For example, if DQM was LOW dur-ing T4 in Figure 15, then the WRITEs at T5 and T7would be valid, while the WRITE at T6 would beinvalid.

The DQM signal must be de-asserted prior to theWRITE command (DQM latency is zero clocks forinput buffers) to ensure that the written data is notmasked. Figure 14 shows the case where the clock fre-quency allows for bus contention to be avoided with-out adding a NOP cycle, and Figure 15 shows the casewhere the additional NOP is needed.

Figure 15: READ to WRITE with Extra Clock Cycle

A fixed-length READ burst may be followed by, ortruncated with, a PRECHARGE command to the samebank (provided that auto precharge was not activated),and a full-page burst may be truncated with a PRE-CHARGE command to the same bank. The PRE-CHARGE command should be issued x cycles beforethe clock edge at which the last desired data element isvalid, where x equals the CAS latency minus one. Thisis shown in Figure 16 for each possible CAS latency;data element n + 3 is either the last of a burst of four orthe last desired of a longer burst. Following the PRE-CHARGE command, a subsequent command to thesame bank cannot be issued until tRP is met. Note thatpart of the row precharge time is hidden during theaccess of the last data element(s).

In the case of a fixed-length burst being executed tocompletion, a PRECHARGE command issued at theoptimum time (as described above) provides the sameoperation that would result from the same fixed-lengthburst with auto precharge. The disadvantage of thePRECHARGE command is that it requires that thecommand and address buses be available at theappropriate time to issue the command; the advantageof the PRECHARGE command is that it can be used totruncate fixed-length or full-page bursts.

DON’T CARE

READ NOP NOP WRITENOP

CLK

T2T1 T4T3T0

DQM

DQ DOUT n

COMMAND

DIN b

ADDRESS BANK,COL nBANK,COL b

DS

tHZ

t

tCK

NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.

TRANSITIONING DATA

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS BANK,COL n

WRITE

DIN b

BANK,COL b

T5

DS

tHZ

t

NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank.

TRANSITIONING DATA



Figure 16: READ to PRECHARGE

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

PRECHARGE ACTIVE

t RP

T7

NOTE: DQM is LOW.

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

PRECHARGE ACTIVE

t RP

T7

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS


BANK a,COL n

NOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

PRECHARGE ACTIVE

t RP

T7

BANK a,ROW

BANK(a or all)

DON’T CARE

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

BANK a,COL n

BANK a,ROW

BANK(a or all)

BANK a,COL n

BANK a,ROW

BANK(a or all)

X = 2 cycles

TRANSITIONING DATA



Full-page READ bursts can be truncated with theBURST TERMINATE command, and fixed-lengthREAD bursts may be truncated with a BURST TERMI-NATE command, provided that auto precharge wasnot activated. The BURST TERMINATE command

should be issued x cycles before the clock edge atwhich the last desired data element is valid, where xequals the CAS latency minus one. This is shown inFigure 17 for each possible CAS latency; data elementn + 3 is the last desired data element of a longer burst.

Figure 17: Terminating a READ Burst

DON’T CARE

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS


BANK,COL n

NOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

BURSTTERMINATE

NOP

T7

NOTE: DQM is LOW.

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,COL n

NOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

BURSTTERMINATE

NOP

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,COL n

NOP

DOUTn + 1

DOUTn + 2

DOUTn + 3

BURSTTERMINATE

NOP

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

TRANSITIONING DATA



WRITEsWRITE bursts are initiated with a WRITE command,

as shown in Figure 18. The starting column and bank addresses are pro-

vided with the WRITE command, and auto prechargeis either enabled or disabled for that access. If autoprecharge is enabled, the row being accessed is pre-charged at the completion of the burst. For the genericWRITE commands used in the following illustrations,auto precharge is disabled.

During WRITE bursts, the first valid data-in elementwill be registered coincident with the WRITE com-mand. Subsequent data elements will be registered oneach successive positive clock edge. Upon completionof a fixed-length burst, assuming no other commandshave been initiated, the DQs will remain High-Z andany additional input data will be ignored (seeFigure 19). A full-page burst will continue until termi-nated. (At the end of the page, it will wrap to column 0and continue.)

Figure 18: WRITE Command

Data for any WRITE burst may be truncated with asubsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed bydata for a WRITE command. The new WRITE com-mand can be issued on any clock following the previ-ous WRITE command, and the data providedcoincident with the new command applies to the newcommand. An example is shown in Figure 19. Data n +1 is either the last of a burst of two or the last desired ofa longer burst. The 128Mb SDRAM uses a pipelinedarchitecture and therefore does not require the 2n ruleassociated with a prefetch architecture. A WRITE com-mand can be initiated on any clock cycle following aprevious WRITE command. Full-speed random writeaccesses within a page can be performed to the samebank, as shown in Figure 20, or each subsequentWRITE may be performed to a different bank.

Figure 19: WRITE Burst

Figure 20: WRITE to WRITE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMNADDRESS

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANKADDRESS

A0-A8

A10

BA0,1

A9, A11

VALID ADDRESS

CLK

DQ DIN n

T2T1 T3T0

COMMAND

ADDRESS

NOP NOPWRITE

DINn + 1

NOP

BANK,COL n

NOTE: Burst length = 2. DQM is LOW.


DON’T CARE

CLK

DQ

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,COL n

BANK,COL b

DIN n

DINn + 1

DIN b

NOTE: DQM is LOW. Each WRITE command may be to any bank.

TRANSITIONING DATA



Data for any WRITE burst may be truncated with asubsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by aREAD command. Once the READ command is regis-tered, the data inputs will be ignored, and writes willnot be executed. An example is shown in Figure 22.Data n + 1 is either the last of a burst of two or the lastdesired of a longer burst.

Data for a fixed-length WRITE burst may be fol-lowed by, or truncated with, a PRECHARGE commandto the same bank (provided that auto precharge wasnot activated), and a full-page WRITE burst may betruncated with a PRECHARGE command to the samebank. The PRECHARGE command should be issuedtWR after the clock edge at which the last desired inputdata element is registered. The auto precharge moderequires a tWR of at least one clock plus time, regard-less of frequency.

In addition, when truncating a WRITE burst, theDQM signal must be used to mask input data for theclock edge prior to, and the clock edge coincident with,the PRECHARGE command. An example is shown inFigure 23. Data n + 1 is either the last of a burst of twoor the last desired of a longer burst. Following the PRE-CHARGE command, a subsequent command to thesame bank cannot be issued until tRP is met.

In the case of a fixed-length burst being executed tocompletion, a PRECHARGE command issued at theoptimum time (as described above) provides the sameoperation that would result from the same fixed-lengthburst with auto precharge. The disadvantage of thePRECHARGE command is that it requires that thecommand and address buses be available at theappropriate time to issue the command; the advantageof the PRECHARGE command is that it can be used totruncate fixed-length or full-page bursts.

Figure 21: Random WRITE Cycles

Figure 22: WRITE to READ

Figure 23: WRITE to PRECHARGE

DON’T CARE

CLK

DQ DIN n

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,COL n

DINa

DINx

DINm

WRITE WRITE WRITE

BANK,COL a

BANK,COL x

BANK,COL m

NOTE: Each WRITE command may be to any bank. DQM is LOW.

TRANSITIONING DATA

DON’T CARE

CLK

DQ

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,COL n

DIN n

DINn + 1

DOUT b

READ NOP NOP

BANK,COL b

NOP

DOUTb + 1

T4 T5

NOTE: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration.

TRANSITIONING DATA

DQM

CLK

DQ

T2T1 T4T3T0

COMMAND

ADDRESS BANK a,COL n

T5

NOPWRITE PRECHARGE NOPNOP

DIN n

DINn + 1

ACTIVE

t RP

BANK(a or all)

t WR

BANK a,ROW

DQM

DQ

COMMAND

ADDRESS BANK a,COL n

NOPWRITE PRECHARGE NOPNOP

DIN n

DINn + 1

ACTIVE

t RP

DON’T CARE

BANK(a or all)

t WR

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

BANK a,ROW

T6

NOP

NOP

[email protected] tCK 15ns

[email protected] tCK < 15ns

TRANSITIONING DATA



Fixed-length or full-page WRITE bursts can be trun-cated with the BURST TERMINATE command. Whentruncating a WRITE burst, the input data applied coin-cident with the BURST TERMINATE command will beignored. The last data written (provided that DQM isLOW at that time) will be the input data applied oneclock previous to the BURST TERMINATE command.This is shown in Figure 24, where data n is the lastdesired data element of a longer burst.

Figure 24: Terminating a WRITE Burst

Figure 25: PRECHARGE Command

PRECHARGEThe PRECHARGE command (see Figure 25) is used

to deactivate the open row in a particular bank or theopen row in all banks. The bank(s) will be available fora subsequent row access some specified time (tRP)after the precharge command is issued. Input A10determines whether one or all banks are to be pre-charged, and in the case where only one bank is to beprecharged, inputs BA0, BA1 select the bank. When allbanks are to be precharged, inputs BA0, BA1 aretreated as “Don’t Care.” Once a bank has been pre-charged, it is in the idle state and must be activatedprior to any READ or WRITE commands being issuedto that bank.

POWER-DOWNPower-down occurs if CKE is registered low coinci-

dent with a NOP or COMMAND INHIBIT when noaccesses are in progress. If power-down occurs whenall banks are idle, this mode is referred to as prechargepower-down; if power-down occurs when there is arow active in any bank, this mode is referred to asactive power-down. Entering power-down deactivatesthe input and output buffers, excluding CKE, for maxi-mum power savings while in standby. The device maynot remain in the power-down state longer than therefresh period (64ms) since no refresh operations areperformed in this mode.

The power-down state is exited by registering a NOPor COMMAND INHIBIT and CKE HIGH at the desiredclock edge (meeting tCKS). See Figure 26.

Figure 26: Power-Down

CLK

DQ

T2T1T0

COMMAND

ADDRESS BANK,COL n

WRITE BURSTTERMINATENEXT

COMMAND

DIN n

(ADDRESS)

(DATA)

NOTE: DQMs are LOW.

TRANSITIONING DATA DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON’T CARE

HIGH

All Banks

Bank Selected

A0-A9

BA0,1 BANKADDRESS

VALID ADDRESS

DON’T CARE

tRAS

tRCD

tRC

All banks idleInput buffers gated off

Exit power-down mode.

()()

()()

()()

tCKS > tCKS

COMMAND NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

()()



CLOCK SUSPENDThe clock suspend mode occurs when a column

access/burst is in progress and CKE is registered low.In the clock suspend mode, the internal clock is deacti-vated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is sam-pled LOW, the next internal positive clock edge is sus-pended. Any command or data present on the inputpins at the time of a suspended internal clock edge isignored; any data present on the DQ pins remainsdriven; and burst counters are not incremented, aslong as the clock is suspended. (See examples inFigure 27 and Figure 28.)

Figure 27: Clock Suspend During WRITE Burst

Clock suspend mode is exited by registering CKEHIGH; the internal clock and related operation willresume on the subsequent positive clock edge.

BURST READ/SINGLE WRITEThe burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the moderegister to a logic 1. In this mode, all WRITE com-mands result in the access of a single column location(burst of one), regardless of the programmed burstlength. READ commands access columns according tothe programmed burst length and sequence, just as inthe normal mode of operation (M9 = 0).

Figure 28: Clock Suspend During READ Burst

DON’T CARE

DIN

COMMAND

ADDRESS

WRITE

BANK,COL n

DIN n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNALCLOCK

NOP

DINn + 1

DINn + 2

NOTE: For this example, burst length = 4 or greater, and DMis LOW.

TRANSITIONING DATADON’T CARE

CLK

DQ DOUT n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,COL n

NOP

DOUTn + 1

DOUTn + 2

DOUT n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.

CKE

INTERNALCLOCK

NOP

TRANSITIONING DATA



CONCURRENT Auto PrechargeAn access command (READ or WRITE) to another

bank while an access command with auto prechargeenabled is executing is not allowed by SDRAMs, unlessthe SDRAM supports Concurrent Auto precharge.Micron SDRAMs support Concurrent Auto precharge.Four cases where Concurrent Auto precharge occursare defined below.

READ with Auto Precharge1. Interrupted by a READ (with or without auto pre-

charge): A READ to bank m will interrupt a READ onbank n, CAS latency later. The precharge to bank nwill begin when the READ to bank m is registered(Figure 29).

2. Interrupted by a WRITE (with or without auto pre-charge): A WRITE to bank m will interrupt a READon bank n when registered. DQM should be usedtwo clocks prior to the WRITE command to preventbus contention. The precharge to bank n will beginwhen the WRITE to bank m is registered (Figure 30).

Figure 29: READ With Auto Precharge Interrupted by a READ

Figure 30: READ With Auto Precharge Interrupted by a WRITE

DON’T CARE

CLK

DQ DOUTa

T2T1 T4T3 T6T5T0

COMMAND READ - AP BANK n NOP NOPNOPNOP

DOUTa + 1

DOUTd

DOUT d + 1

NOP

T7

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,COL a

BANK m,COL d

READ - AP BANK m

Internal States

t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK n tRP - BANK m

CAS Latency = 3 (BANK n)

TRANSITIONING DATA

CLK

DQDOUT

a

T2T1 T4T3 T6T5T0

COMMAND NOPNOPNOPNOP

DINd

DINd + 2

DIN d + 3

NOP

T7

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.

BANK n,COL a

BANK m,COL d

WRITE - AP BANK m

Internal States

t

Page Active

READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP - BANK n t WR - BANK m

CAS Latency = 3 (BANK n)

READ - AP BANK n

1


DINd + 1



WRITE with Auto Precharge3. Interrupted by a READ (with or without auto pre-

charge): A READ to bank m will interrupt a WRITEon bank n when registered, with the data-outappearing CAS latency later. The precharge to bankn will begin after tWR is met, where tWR beginswhen the READ to bank m is registered. The lastvalid WRITE to bank n will be data-in registered oneclock prior to the READ to bank m (Figure 31).

4. Interrupted by a WRITE (with or without auto pre-charge): A WRITE to bank m will interrupt a WRITEon bank n when registered. The precharge to bank nwill begin after tWR is met, where tWR begins whenthe WRITE to bank m is registered. The last validdata WRITE to bank n will be data registered oneclock prior to a WRITE to bank m (Figure 32).

Figure 31: WRITE With Auto Precharge Interrupted by a READ

Figure 32: WRITE With Auto Precharge Interrupted by a WRITE

DON’T CARE

CLK

DQ

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP BANK n NOPNOPNOPNOP

DINa + 1

DINa

NOP NOP

T7

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,COL a

BANK m,COL d

READ - AP BANK m

Internal States

t

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

DOUTd

DOUTd + 1

CAS Latency = 3 (BANK m)

RP - BANK nWR - BANK n

TRANSITIONING DATA

DON’T CARE

CLK

DQ

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP BANK n NOPNOPNOPNOP

DINd + 1

DINd

DINa + 1

DINa + 2

DINa

DINd + 2

DIN d + 3

NOP

T7

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,COL a

BANK m,COL d

WRITE - AP BANK m

Internal States

t

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK n tRP - BANK nt WR - BANK m

TRANSITIONING DATA



NOTE:

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.2. Current state is the state of the SDRAM immediately prior to clock edge n.3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.4. All states and sequences not shown are illegal or reserved.5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided

that tCKS is met).6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or

NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP com-

mands must be provided during tXSR period.7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock

edge n + 1.

Table 7: Truth Table – CKE(Notes: 1-4)

CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn NOTES

L L Power-Down X Maintain Power-DownSelf Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock SuspendL H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6Clock Suspend X Exit Clock Suspend 7

H L All Banks Idle COMMAND INHIBIT or NOP Power-Down EntryAll Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend EntryH H See Truth Table 3



NOTE:

1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:Idle:The bank has been precharged, and tRP has been met.Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state.Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state.Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state.Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state.Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle.8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.11.Does not affect the state of the bank and acts as a NOP to that bank.

Table 8: TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK nNotes: 1-6; notes appear below table

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)L H H H NO OPERATION (NOP/Continue previous operation)

Idle L L H H ACTIVE (Select and activate row)L L L H AUTO REFRESH 7L L L L LOAD MODE REGISTER 7L L H L PRECHARGE 11

Row Active L H L H READ (Select column and start READ burst) 10L H L L WRITE (Select column and start WRITE burst) 10L L H L PRECHARGE (Deactivate row in bank or banks) 8

Read (Auto Precharge Disabled)

L H L H READ (Select column and start new READ burst) 10L H L L WRITE (Select column and start WRITE burst) 10L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8L H H L BURST TERMINATE 9

Write (Auto Precharge Disabled)

L H L H READ (Select column and start READ burst) 10L H L L WRITE (Select column and start new WRITE burst) 10L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8L H H L BURST TERMINATE 9



NOTE:

1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com-mands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given com-mand is allowable). Exceptions are covered in the notes below.

3. Current state definitions:Idle: The bank has been precharged, and tRP has been met.Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.6. All states and sequences not shown are illegal or reserved.7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been inter-

rupted by bank m’s burst.9. Burst in bank n continues as initiated.

Table 9: TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK mNotes: 1-6; notes appear below and on next page

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)L H H H NO OPERATION (NOP/Continue previous operation)

Idle X X X X Any Command Otherwise Allowed to Bank mRow

Activating,Active, or

Precharging

L L H H ACTIVE (Select and activate row)L H L H READ (Select column and start READ burst) 7L H L L WRITE (Select column and start WRITE burst) 7L L H L PRECHARGE

Read(Auto

PrechargeDisabled)

L L H H ACTIVE (Select and activate row)L H L H READ (Select column and start new READ burst) 7, 10L H L L WRITE (Select column and start WRITE burst) 7, 11L L H L PRECHARGE 9

Write(Auto

PrechargeDisabled)

L L H H ACTIVE (Select and activate row)L H L H READ (Select column and start READ burst) 7, 12L H L L WRITE (Select column and start new WRITE burst) 7, 13L L H L PRECHARGE 9

Read(With AutoPrecharge)

L L H H ACTIVE (Select and activate row)L H L H READ (Select column and start new READ burst) 7, 8, 14L H L L WRITE (Select column and start WRITE burst) 7, 8, 15L L H L PRECHARGE 9

Write(With AutoPrecharge)

L L H H ACTIVE (Select and activate row)L H L H READ (Select column and start READ burst) 7, 8, 16L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17L L H L PRECHARGE 9



10.For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 12).

11.For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 14 and Figure 15). DQM should be used one clock prior to the WRITE command to prevent bus contention.

12.For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 22), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13.For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered (Figure 20). The last valid WRITE to bank n will be data-in regis-tered one clock prior to the READ to bank m.

14.For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 29).

15.For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to pre-vent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 30).

16.For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to

bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m (Figure 31).

17.For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m (Figure 32).



ABSOLUTE MAXIMUM RATINGSVoltage on VDD/VDDQ SupplyRelative to VSS(3.3V) . . . . . . . . . . . . . . . .-1V to +4.6VRelative to VSS(2.5V). . . . . . . . . . . . . . . . 0.5V to +3.6VVoltage on Inputs, NC or I/O Pins Relative to VSS((3.3V) . . . . . . . . . . . . . . . .-1V to +4.6VRelative to VSS(2.5V). . . . . . . . . . . . . . . .-0.5V to +3.6VOperating TemperatureTA (Commercial) . . . . . . . . . . . . . . . . . . . 0°C to +70°CTA (Industrial) . . . . . . . . . . . . . . . . . . . -40°C to +85°CStorage Temperature (plastic) . . . . -55°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Stresses greater than those listed under “AbsoluteMaximum Ratings” may cause permanent damage tothe device. This is a stress rating only, and functionaloperation of the device at these or any other condi-tions above those indicated in the operational sectionsof this specification is not implied. Exposure to abso-lute maximum rating conditions for extended periodsmay affect reliability.

Table 10: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS(LC VERSION)

Notes: 1, 5, 6; notes appear on page 37; VDD= +3.3V ±0.3V, VDDQ = +3.3V ±0.3V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 3 3.6 V

I/O Supply Voltage VDDQ 3 3.6 V

Input High Voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 22

Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22

Data Output High Voltage: Logic 1; All inputs VOH 2.4 – V

Data Output LOW Voltage: LOGIC 0; All inputs VOL – 0.4 V

Input Leakage Current: II -5 5 µA

Any Input 0V � VIN � VDD (All other pins not under test = 0V)Output Leakage Current: DQs are disabled; 0V � VOUT � VDDQ IOZ -5 5 µA

Table 11: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS(V VERSION)

Notes: 1, 5, 6; notes appear on page 37; VDD = 2.5 ±0.2V, VDDQ = +2.5V ±0.2V or +1.8V ±0.15V


Supply Voltage VDD 2.3 2.7 V

I/O Supply Voltage VDDQ 1.65 2.7 V

Input High Voltage: Logic 1; All inputs VIH 1.25 VDD + 0.3 V 22

Input Low Voltage: Logic 0; All inputs VIL -0.3 +0.55 V 22

Data Output High Voltage: Logic 1; All inputs VOH VDDQ - 0.2 – V

Data Output Low Voltage: LOGIC 0; All inputs VOL – 0.2 V

Input Leakage Current: II -5 5 µA

Any input 0V � VIN � VDD (All other pins not under test = 0V)Output Leakage Current: DQs are disabled; 0V � VOUT � VDDQ IOZ -5 5 µA

Table 12: AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONSVDD = +3.3V ±0.3V or 2.5 ±0.2V, VDDQ = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V ±0.15V


Input High Voltage: Logic 1; All inputs VIH 1.4 – VInput Low Voltage: Logic 0; All inputs VIL – 0.4 V



Table 13: ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

Notes: 5, 6, 8, 9, 11; notes appear on page 37

AC CHARACTERISTICS -8 -10

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTESAccess time from CLK (pos. edge) CL = 3 tAC (3) 6 6 ns 27

CL = 2 tAC (2) 7 7 ns

CL = 1 tAC (1) 18 18 ns

Address hold time tAH 1 1 ns

Address setup time tAS 2.5 2.5 ns

CLK high-level width tCH 3 3 ns

CLK low-level width tCL 3 3 ns

Clock cycle time CL = 3 tCK (3) 8 10 ns 23

CL = 2 tCK (2) 10 12 ns 23

CL = 1 tCK (1) 20 25 ns 23

CKE hold time tCKH 1 1 ns

CKE setup time tCKS 2.5 2.5 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2.5 2.5 ns

Data-in hold time tDH 1 1 ns

Data-in setup time tDS 2.5 2.5 ns

Data-out high-impedance time CL = 3 tHZ (3) 6 6 ns 10

CL = 2 tHZ (2) 7 7 ns 10

CL = 1 tHZ (1) 18 18 ns 10

Data-out low-impedance time tLZ 1 1 ns

Data-out hold time (load) tOH 2.5 2.5 ns

Data-out hold time (no load) tOHN 1.8 1.8 ns 28ACTIVE to PRECHARGE command tRAS 48 120,000 50 120,000 ns

ACTIVE to ACTIVE command period tRC 80 100 ns

ACTIVE to READ or WRITE delay tRCD 20 20 ns

Refresh period (4,096 rows) tREF 64 64 ms

AUTO REFRESH period tRFC 80 100 ns

PRECHARGE command period tRP 20 20 ns

ACTIVE bank a to ACTIVE bank b command

tRRD 20 20 ns

Transition time tT 0.5 1.2 0.5 1.2 ns 7

WRITE recovery time Auto Precharge Mode

tWR (a) 1 CLK +7ns

1 CLK+ 5ns

– 24

Manual Precharge Mode

tWR (m) 15 15 ns 25

Exit SELF REFRESH to ACTIVE command tXSR 80 100 ns 20



Table 14: AC FUNCTIONAL CHARACTERISTICSNotes: 5, 6, 7, 8, 9, 11; notes appear on page 37

PARAMETER SYMBOL -8 -10 UNITS NOTESREAD/WRITE command to READ/WRITE command tCCD 1 1 tCK 17

CKE to clock disable or powe

128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAMglacier.lbl.gov/.../MT48V4M32LFFC-8-128Mbx16x32.pdf · 2003. 4. 1. · 128Mb: x16, x32 MOBILE SDRAM 09005aef808ebf65 Micron Technology,

Text of 128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAMglacier.lbl.gov/.../MT48V4M32LFFC-8-128Mbx16x32.pdf ·...

128MB memory - Brother

Hardware Accelerated Similarity Search · Multi Board Solutions For Huge Databases ( ~ 1TB ) 16GB Memory PCIe Card 128Mb 128Mb 16GB Memory PCIe Card 128Mb 128Mb 16GB Memory PCIe Card

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

128Mb: x32 SDRAMDQM mask logic read data latch write drivers Column decoder Bank 0 memory array (4096 x 2048 x 4) Bank 0 row-address latch and decoder 4096 Sense amplifiers Bank control

JHF VISTA X32

Intel® Agilex™ Configuration User Guide · Avalon-ST configuration supports x8, x16, and x32 modes. The x16 and x32 bit modes use general-purpose The x16 and x32 bit modes use

eminigarderr x16 int 9 mm x32 fx8 hxl ... · eminigarderr x16 int 9 mm x32 fx8 hxl [email protected] CORNER COLUMN ax2 14cm 17cm 150cm 12L cx8 0.78in 450 compost/substrate - substrato

X32 DIGITAL MIXER

2Gb (x16, x32) Mobile DDR SDRAM - ISSIIS43/46LR32640B IS43/46LR16128B Rev. 00B | December 2019 - [email protected] 1 2Gb (x16, x32) Mobile DDR SDRAM Description The IS43/46LR16128B/32640B

CD 28L QL Series - Jianghai Europejianghai-europe.com/wp-content/uploads/JE18_CD_28L_QL.pdf · CD 28L QL Series TA (˚C) IA ––– IR 2.5 2.0 1.5 1.0 0.5 0.0 X32 X16 X8 X4 X2 X1

8Gb: x16, x32 GDDR5X SGRAM · • Consecutive read of read FIFO via RDTR command • Read/write EDC on/off mode • Programmable EDC hold pattern for CDR • Read/write data transmission

Mobile SDRAM 128Mb: x16, x32 Data Sheet€¦ · ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A11 select the row). The address

TN-52-02: LPDDR2/LPDDR3 Point-to-Point System Design · 533 MHz/DDR1066 800 MHz/DDR1600; 1066 MHz/DDR2133 Burst lengths 4, 8, 16 8 Configurations x16, x32 x16, x32 Address command

Apollo x16 Hardware Manual - Universal Audiomedia.uaudio.com/support/manuals/hardware/Apollo x16 Hardware … · Apollo x16 Hardware Manual 8 Introduction Apollo x16 Documentation

2Gb: x16, x32 Mobile LPDDR SDRAM - Micron …/media/Documents/Products/Data...Figure 51: WRITE-to-PRECHARGE – Interrupting 90 Figure 52: WRITE-to-PRECHARGE – Odd Number of Data,

128Mb B-die Page NOR Specification Dual Die Package ... · K8Q2815UQB FLASH MEMORY Revision 1.1 June 2007 3 128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory / 56TSOP - Two

256Mb (x16, x32) Mobile LpddR2 s4 sdRAM

X32 Quick Start

2Gb: x16, x32 Mobile LPDDR SDRAM - Micron Technology

4Gb (x16/x32) Mobile LPDDR4/LPDDR4X with ECCIntegrated Silicon Solution, Inc. — 2 Rev. A 07/16/2020 ® Long-te upport W uality IS43/46LQ16256A, IS43/46LQ32128A, 200-ball x16 Discrete

INSTALLATION INSTRUCTIONS: HORIZONTAL WALL BED …go.rockler.com/tech/horizontal-mount-murphy-bed-instructions.pdfPlease see next page to see which slats to skip. x32 x32 x16 *If necessary,

512Mb (x16, x32) Mobile LpddR2 s4 sdRAM · 2017. 8. 28. · IS43/46LD16320A IS43/46LD32160A Integrated Silicon Solution, Inc. — 6 Rev. C 08/18/2017 NOTE 1 Data includes DQ and DM

Ibm x32 Manual

1Gb: x16, x32 Automotive LPDDR2 SDRAM · 2020. 8. 3. · Table 3: Package Codes and Descriptions Package Code Ball Count # Ranks # Channels Size (mm) Die per Package Solder Ball Composition

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Data Sheet · Products and specifications discussed herein are subject to change by Micron without notice. 256Mb: x16, x32 Mobile SDRAM

Design considerations for LPDDR4/3 PHY and controller … dual mode concept LPDDR3 mode (single channel, 32 byte access) MC CMD queue, Bus Fabric x16 /x32 LPDDR3 x32 DRAM 16 DQ 16

8Gb: x16, x32 GDDR5X SGRAM - Micron Technology, Inc./media/documents/products/... · 8n prefetch architecture with 256bit per array read or write access; burst length 8 • 16 internal

200b: x16/x32 LPDDR4/LPDDR4X SDRAM · 2020. 10. 19. · LPDDR4/LPDDR4X SDRAM MT53D512M16D1, MT53D512M32D2, MT53D1024M32D4 Features This data sheet is for LPDDR4 and LPDDR4X unified

2Gb: x16, x32 Automotive LPDDR SDRAM - Texas Instruments · Automotive LPDDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks MT46H64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 –

1Gb (x16, x32) Mobile LpddR2 s4 sdRAM · 2017-08-18 · 1Gb (x16, x32) Mobile LpddR2 s4 sdRAM AUGUst 2017 FeAtURes • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ