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4/9/2014 VLSI DESIGN UNIT-1 LECTURE-2 Basic MOS Transistor nMOS enhancement mode Transistor nMOS depletion mode Transistor MOS transistors when Vds=0V Source Vgs,Vsb=0V

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  • 4/9/2014

    VLSI DESIGN

    UNIT-1

    LECTURE-2

    Basic MOS TransistornMOS enhancement mode Transistor

    nMOS depletion mode Transistor

    MOS transistors when Vds=0V SourceVgs,Vsb=0V

  • 4/9/2014

    Action of enhancement mode transistor action(nMOS)

    Source and drain regions are formed by doping desired n-impurityconcentration.

    Source and drain are separated by two back to back connected diodeshence electrons flows from source to drain. Depletion region surroundsaround source and drain junctions as they are reverse biased.

    Gate oxide (Sio2) is grown above substrate between source and drainwhile polysilicon/metal is deposited over it.

    Channel is not formed when gate voltage is not applied(Vgs=0V) There are two electric fields in the transistor ,vertical from gate to

    substrate due to Vgs, horizontal from drain to source due to Vds.

    nMOS depletion mode MOSFET

    When Vgs=0V, Vd>0 V current flows in the transistor. When Vgs0V the depletion MOSFET acts as enhancement MOSFET.

    Transistor is normally ON. The ntype impurities are buried in

    the channel area.

  • 4/9/2014

    When positive gate voltage isapplied the positive voltage onthe gate plate attracts theminority carriers (electrons) fromthe substrate.

    This also uncovers the positive ionsnear the surface formingdepletion region .

    At a particular gate voltage the number of electrons near the surfacebecome equal to the doping concentration of the substrate. The surfaceinverts to n-type. This voltage is known as Threshold Voltage (Vth).

    A uniform channel is formed near the surface at threshold voltage(Vgs=Vth)

    Vgs> 0V ,Vds= 0V

    When Vgs>Vth and Vds0V) Current flows from drain to source as

    electrons move through the channelunder the influence of the horizontalelectric field as well as vertical electricfield.

    There is voltage drop in the channel due to VDS varying with distance,(more near the drain end).

    Effective gate voltage is Vg=Vgs-Vth.There will be no voltage available toinvert the channel at the drain end so long as Vgs-Vth>=Vds.

  • 4/9/2014

    The limiting condition comes when For all voltages Vds