11.9: A 105 Gb/s Dielectric-Waveguide Link in 130nm BiCMOS … · 2021. 2. 24. · Mixer Sub-THz Source BD 1 2 BD 3 Sub-THz Source Freq. Synth. & Baseband Control TX Chip RX Chip

11.9: A 105 Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler© 2021 IEEE International Solid-State Circuits Conference 1 of 59

11.9: A 105 Gb/s Dielectric-Waveguide Link in 130nm

BiCMOS Using Channelized 220-to-335GHz Signal

and Integrated Waveguide Coupler

Jack W. Holloway1,2, Georgios C. Dogiamis3, Ruonan Han1

1Massachusetts Institute of Technology, Cambridge, MA2Raytheon Technologies, Tewksbury, MA3Intel, Chandler, AZ


Self Introduction

S.B. Mathematics, S.B. Electrical Engineering MIT

M.Eng. Electrical Engineering & Computer Science MIT

Ph.D. Electrical Engineering MIT

United States Marine Corps 2006 – 2019

Office of Naval Research 2014 – 2017

MIT Lincoln Laboratory 2015 – 2018

Naval Research Laboratory 2014 – 2020

Raytheon Technologies 2018 – Present

Interests

High-performance RF/mixed signal microelectronics

Heterogenous integration/packaging

Analog signal processing

Microwave photonics


Outline

Introduction

Architecture

Circuit Description

Experimental Results

Conclusion


Introduction: Application

Intermediate range (~1m)

High-rate (100+ Gbps)

Monolithic

Simple packaging

Energy-efficient (~pJ/bit)

Throughput density (300+ Gbps/mm)

Intermediate Reach IO

Interconnect Reach



Backplane Package-Package Interconnect

• Better energy efficiency than

photonics or copper in meter-

class links

• High data rates over .1-1m

• Large throughput density

• Low-cost integration/packaging



Backplane-Backplane Fly-Over Cable Concept

• The waveguide flexibility

• Small cross section

• Efficient operation over ~1m


Key Enabler: Sub-THz Dielectric Waveguides

Dielectric Waveguides

Unclad Dielectric Waveguides

Channel Loss, 1 Meter

0 5 10 15 20 25 30

Channel Bandwidth (GHz)

-30

-25

-20

-15

-10

-5

0

S2

1 (d

B)

1m Twinax

Sub-THz Dielectric

Waveguide Est. Loss

400 μm

400 μm

235 GHz 275 GHz 315 GHz

Ey1

1E

x1

1E

x1

1

Fie

ld

Str

en

gth

𝐸11𝑥

235 GHz 275 GHz 315 GHz

Waveguide Bond

Surface Contour

[J. Holloway et al., IEDM, 2020]


Comparison

[S. Fukuda et al., JSSC, 2011]

• 57 GHz and 80 GHz duplex operation

• Single-channel scheme

• Off-chip coupler

• Planar coupler/waveguide architecture

Demonstration:

• Data rate: 12.5 Gbps, full-duplex (25 Gbps)

• Link efficiency: 5.7 pJ/bit


Comparison[M. Sawaby et al., SSC-L, 2018]

• 130 GHz operation



• Planar coupler/waveguide architecture

Demonstration:

• Data rate: 36 Gbps

• Link efficiency: 6 pJ/bit (transmitter only)


Comparison

[M. De Wit et al., ESSCIRC, 2016]

• 140 GHz operation



• Orthogonal coupler/waveguide

scheme

Demonstration:

• Data rate: 12 Gbps

• Link efficiency: 19.2 pJ/bit


Comparison with Dielectric Waveguide Links

• Electrical links provide high efficiency below 56 Gbps

– Dielectric links must maintain competitive efficiency and show data rate

scaling beyond 100 Gbps to be competitive


Comparison with Dielectric Waveguide Links

• Research focus on planar monolithic/in-package links

• Multiple sub-THz channels to maximize available guide bandwidth

• Higher frequency operation to improve bandwidth and reduce size


Outline

Introduction

Architecture

Circuit Description


Conclusion


Architecture Concept

• On-chip sub-THz carrier generation

Sub-THz

Source

Freq. Synth. & Baseband

Control



• Baseband bit streams modulate each carrier

Sub-THz

Source


Control

Transmit Data Stream

BD 2Baseband Data 1

(BD1)BD 3

Digital Block



• A sub-THz multiplexer combines channels

Sub-THz

Source


Control

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHz

220-335 GHz MultiplexerTransmit Data Stream

BD 2Baseband Data 1

(BD1)BD 3

Digital Block



• Power coupled to- and transported along low-loss dielectric waveguides

Sub-THz

Source


Control Broadband

Coupler

Broadband

Coupler

Dielectric Waveguide

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHz


BD 2Baseband Data 1

(BD1)BD 3

Digital Block



• Independent channels separated and demodulated on receive

Sub-THz

Source


Control Broadband

Coupler

Broadband

Coupler

Dielectric Waveguide

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHz


BD 2Baseband Data 1

(BD1)BD 3

Digital Block

Sub-THz

Source


Control

Digital Block

Receive Data Stream


Link Demonstration

• Designed and implemented in IHP 130 nm BiCMOS process

– SG13G2, 𝑓𝑡 = 300 GHz, 𝑓𝑚𝑎𝑥 = 500 GHZ HBT

• Three-channel transmitter, single-channel receiver for testing

Sub-THz

Mixer

Sub-THz

Source

BD 1 BD 2 BD 3

Sub-THz

Source


Control

TX Chip

RX Chip


Transmitter Architecture

• Single-chip generates three sub-harmonic carriers

• System performs harmonic doubling and modulation

• On-chip multiplexer channelizes/aggregates RF spectra

• Broadband coupler launches the sub-THz energy

[J. Holloway et al., ISSCC, 2021]


Outline

Introduction

Architecture

Circuit Description


Conclusion


Link Transmitter Chip: Amp. Multiplier Chain

130GHz Tripler

5dB Coupler

Freq.-Doubling Modulator



fLO1=110GHz

fLO2=130GHz

fLO3=150GHz

fC1

fC2

fC3

20GHz I/Q

20GHz I/Q

SSB Mixer

D1 D2 D3 PRBS(35x3 Gbps)

fin=43.3GHz

PA1

PA2

PA2

PA2

PA2 PA2

PA2

VCC=1.6VVB4

VB3

VCC=1.6VVB4

VB5

130GHz PA1PA2

(Tuned at 110, 130 &

150GHz)

T3

T4

T5

T6

• Off-chip V-band source

• Multiplied and amplified

to generate a 130 GHz

seed carrier

VB1

VCC=1.6V VB2 VCC=1.6V130GHz Tripler

fin=43.3GHzTo

130GHz PA

T1

T2


Link Transmitter Chip: AMC

• Nominal 0 dBm input power, 3.2 dBm output power

• 45 dBc spur performance

• Approx. 8 GHz input LO BW: 48 GHz sub-THz BW38 40 42 44 46 48

Input Frequency (GHz)

-20

-15

-10

-5

0

5

Outp

ut P

ow

er

(dB

m)

-5 -4 -3 -2 -1 0 1 2 3 4 5

Input Power (dBm)

2.6

2.8

3

3.2

3.4

3.6

Outp

ut P

ow

er

(dB

m)

130GHz Tripler

5dB Coupler




fLO1=110GHz

fLO2=130GHz

fLO3=150GHz

fC1

fC2

fC3

20GHz I/Q

20GHz I/Q

SSB Mixer


fin=43.3GHz

PA1

PA2

PA2

PA2

PA2 PA2

PA2

40 60 80 100 120 140 160 180

Frequency (GHz)

-80

-60

-40

-20

0

Outp

ut P

ow

er

(dB

m)

-45 dBc

~8 GHz BW


130GHz Tripler

5dB Coupler




fLO1=110GHz

fLO2=130GHz

fLO3=150GHz

fC1

fC2

fC3

20GHz I/Q

20GHz I/Q

SSB Mixer


fin=43.3GHz

PA1

PA2

PA2

PA2

PA2 PA2

PA2

Link Transmitter Chip: 5dB Coupler

• A two-stage 3-way Wilkinson divider-based 5dB coupling

– Provides ~5.4 – 5.8 dB coupling

– Less than 0.1dB asymmetry across 110-150 GHz

110 120 130 140 150

Frequency (GHz)

-5.9

-5.8

-5.7

-5.6

-5.5

-5.4

-5.3

S-P

ara

mete

rs (

dB

)

R1=260Ω

R2=320Ω

P1

P2

P3

P4

~92° @ 130 GHz

𝑍0 ≈ 65Ω

𝑅1 = 260Ω

𝑅2 = 320Ω

𝑍0 ≈ 75Ω

~75° @ 130 GHz


Link Transmitter Chip: SSB Mixers

• A quadrature SSB mixer generates 110 GHz and 150 GHz carriers

• Single mixer core, up/down conversion via 𝑉𝐴 − 𝑉𝐷 phase reordering

130 GHz

Marchand Balun

130 GHz Lange

Coupler

𝑉𝐴

𝑉𝐵𝑉𝐶

𝑉𝐷

USB

𝑉𝐴

𝑉𝐵𝑉𝐷

𝑉𝐶

LSB

VCC=1.6V

VB1

VB2

VA

V0LO

VB1

VB2

VB

V180LO

VB1

VB2

VC

V270LO

VB1

VB2

VD

V90LO

VLO

V0

LO

V90

LO

V180

LO

V270

LO

VB3VB3

VCC=1.6VVCC=1.6V130GHz Quadrature Network

T1 T2 T3 T4

T5 T6 T7 T8

TL1 TL2 TL3 TL4

T9T10

To PA2


Link Transmitter Chip: SSB Mixers + PAs

• Tuned PA2 amplifiers provide an additional sideband suppression and gain

• Simulated output power: -2.3 dBm to -0.4 dBm

100 120 140 160 180 200

Frequency (GHz)

-80

-60

-40

-20

0

Outp

ut P

ow

er

(dB

m)

USB Mixing

-39.0 dBc

-30.6 dBc

-2.3 dBm

100 120 140 160 180 200

Frequency (GHz)

-80

-60

-40

-20

0

Outp

ut P

ow

er

(dB

m)

LSB Mixing

-0.4 dBm

-37.3 dBc

-57.1 dBc


Link Transmitter Chip: Doubler-Modulator

• A combined doubler-modulator provides modulated power

130GHz Tripler

5dB Coupler




fLO1=110GHz

fLO2=130GHz

fLO3=150GHz

fC1

fC2

fC3

20GHz I/Q

20GHz I/Q

SSB Mixer


fin=43.3GHz

PA1

PA2

PA2

PA2

PA2 PA2

PA2

75fF

Data In

fLO From PA

C2=75fF

VCC=2.5V

To Triplexer

VB

Lo-Z @ 2fLO

fOUT

Hi-Z @ fOUT

T7 T8

T9

T10

C1=300fF

+

-

Broadband Stop



• Single broadband stop provides high impedance across band

0 200 400 600 800 1000

Frequency (GHz)

-50

-40

-30

-20

-10

0

S-P

ara

mete

rs (

dB

)

𝑆11𝑆21

200 250 300 350

Frequency (GHz)

0

500

1000

1500

|Zin| (

)

P1

P2

35+ GHz Open

Tuned Across Band

Using Matching

Network



• Simulated upper sideband modulation power: -14 dBm to -9.5 dBm

CH1 (2fLO=220GHz)CH2 (2fLO=260GHz)CH3 (2fLO=300GHz)

PLO,IN=0dBm

0 10 20 30 40 50-20

-15

-10

-5

Mod

ule

Out

put P

ower

(dBm

)

Modulation Frequency (GHz)

Modulation Frequency (GHz)

75fF

Data In

fLO From PA

C2=75fF

VCC=2.5V

To Triplexer

VB

Lo-Z @ 2fLO

fOUT

Hi-Z @ fOUT

T7 T8

T9

T10

C1=300fF

+

-

Broadband Stop


Sub-THz Channelizers

• Channelizer performance impacts receiver SINR

– Directly impacts link efficiency, capacity, and bit error rate (BER)

• Channel fractional bandwidth and filter roll-off drive higher-order

conventional filters

– Lower on-chip passive quality factor at sub-THz worsens insertion loss

𝑓𝑐1 𝑓𝑐2 𝑓𝑐3

[J. Holloway et al., Micro. Mag., 2020]


On-Chip Channelizers: Channel Filters

P1

P2

M1 M2 M3

M5M4 M6

• Quarter-wave microstrip tuned to maximize individual resonator 𝑄𝑢• Mixed electric & magnetic coupling used to realize filter response


On-Chip Channelizers

• Excellent agreement between

simulation and measurements

0 50 100µm

P1

P2P3

P4


Integrated Sub-THz Coupler

• Tapered, enclosed structure, differentially driven

• Guide mode matched to slot-line leaky mode

𝑉𝑖𝑛

BEOL Coupler Structure

Dielectric

Waveguide

Guided Mode

[J. Holloway et al., T-MTT, 2017]

Waveguide Hybrid Mode Profile

235 GHz

~𝜆/2

315 GHz

E-Field


Integrated Sub-THz Coupler

• Wideband single-ended to differential transition

• Direct waveguide bonding


Link Receiver Chip

Sub-THz

Mixer

Sub-THz

Source

RX Chip

• Single-channel receiver chip


Link Receiver Chip

VCC=2.5VVCC=3.3V VCC=2.5V

1.5mA

250Ω 250Ω

VCC=2.5V

VB

Data Out

220, 260 or 300GHz

LOIN

Marchand Balun

+-

T11 T12 T13 T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

Sub-THz

Mixer

Sub-THz

Source

RX Chip


• Gilbert switching quad provides down-conversion

– Tail transistors provide wideband differential current and match to coupler

– Emitter followers provide voltage translation


Link Receiver Chip


1.5mA

250Ω 250Ω

VCC=2.5V

VB

Data Out

220, 260 or 300GHz

LOIN

Marchand Balun

+-

T11 T12 T13 T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27





Sub-THz

Mixer

Sub-THz

Source

RX Chip


Link Receiver Chip





• Wideband baseband amplifier pair drives off-chip measurements

Sub-THz

Mixer

Sub-THz

Source

RX Chip


1.5mA

250Ω 250Ω

VCC=2.5V

VB

Data Out

220, 260 or 300GHz

LOIN

Marchand Balun

+-

T11 T12 T13 T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27


Link Receiver Chip

220 240 260 280 300 320 340

RF Frequency (GHz)

-20

-15

-10

-5

0

Gc S

SB

(d

B)

220 230 240 250 260 270

RF Frequency (GHz)

-10

-8

-6

-4

-2

0

Gc S

SB

(d

B)

260 270 280 290 300

RF Frequency (GHz)

-10

-8

-6

-4

-2

0

Gc S

SB

(d

B)

300 310 320 330 340

RF Frequency (GHz)

-10

-8

-6

-4

-2

0

Gc S

SB

(d

B)

220 GHz LO 260 GHz LO

300 GHz LO

3dB BW3dB BW

3dB BW• Simulation with full-wave interconnect demonstrates

more than 30 GHz of receiver bandwidth in all channels

• Simulated DC power consumption:

– 20 mW (mixer) + 45 mW (baseband amplifiers)


Outline

Introduction

Architecture

Circuit Description


Conclusion


Link Transmitter Chip

• Measured 3.9 x 2.4 mm

• Consumes 256 mW

3-Channel

Transmitter

Chip

3.9 mm

2.4

mm


Link Receiver Chip

• The final circuit measures 0.9 mm x 0.9 mm and consume 73 mW

Sub-THz

Mixer

Sub-THz

Source

RX Chip

Single-Channel Receiver

Chip

0.9 mm

0.9

mm


Power Measurement

• Waveguide power meter used to measure TX power in each channel

D3

D2

D1

Signal Source(Agilent E8257D)

20GHz I/Q

Signal Source(HP 83650A)

fin=43.3~50GHzTX Chip

Dielectr ic Fiber

(~27cm) Erikson PM5 Power Meter

Sensor Head

Low for CH1

Low for CH3

μW

WR-3.4 Horn

WR-3.4 toWR-10 Taper

I/Q Generation

Network

Low for CH2


Power Measurement


220 240 260 280 300 320

Frequency (GHz)

-40

-35

-30

-25

-20

-15R

ece

ived

Pow

er

(dB

m)

CH 1CH 2CH 3


Power Measurement


• Measured power agrees with the simulation

– Waveguide – horn mode conversion not modeled

220 240 260 280 300 320

Frequency (GHz)

-40

-35

-30

-25

-20

-15R

ece

ived

Pow

er

(dB

m)

220 240 260 280 300 320

Frequency (GHz)

-40

-35

-30

-25

-20

-15R

ece

ived

Pow

er

(dB

m)

~5 dB

Measured

Modeled


Link Testing: Setup

• Waveguide bonded to the chip

surfaces

• Two wideband PRBS generators

used to excite two adjacent

channels at a time


Link Testing: Data Transmission

• Single-channel baseband

measurements confirm PRBS

spectrum

• Adjacent channel

unmodulated carrier present

– Attenuated by RX mixer and

baseband amplifiers



• Eye diagram measurements using

uncorrelated adjacent channel PRBS

data

• 35Gbps verified across all three

channels

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHzCH1 (35Gbps)

25.1mV

35G PRBS

35G PRBS(measurement)

CH2 (35Gbps)

23.0mV

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHz

35G PRBS


CH3 (35Gbps)

14.5mV

fC1

GHz220

fC2

260

fC3

300

35GHz 5GHz

35G PRBS




• BER for two link lengths

• BER:

– < 5 × 10−8 for 35Gbps, 30cm

– < 10−8 for 35Gbps, 5cm

• Eye closure from SNR, not

from dispersion, ISI, or jitter

0 0.2 0.4 0.6 0.8 1

Unit Interval

10-10

10-8

10-6

10-4

10-2

100

Bit E

rror

Ra

te

CH 1CH 2CH 3

35G, 30 cmCH 1CH 2CH 3

35G, 5 cm

Additional

Channel

Loss


Adjacent Channel Interference

• Single 5cm link, 35Gbps

• Single-channel and two-channel operation

– ~10x worse BER from adjacent channel interference

– Remaining VSB power degrades SINR

0 0.2 0.4 0.6 0.8 1

Unit Interval

10-11

10-9

10-7

10-5

10-3

10-1

Bit E

rror

Ra

te

CH 1 OnlyCH 1 + CH2

35G, 5cm

Adjacent

Channel

Interference

[J. Holloway et al., Micro. Mag., 2020]

Adjacent Channel Interference


Outline

Introduction

Architecture

Circuit Description


Conclusion


Link Comparison

• Demonstration exceeds the aggregate data rate of the state of the art by

approximately 3x at commensurate BER[1] S. Fukuda, et. al., “A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect,” JSSC, 2011.

[2] M. Sawaby, et. al., “A Fully Packaged 130-GHz QPSK Transmitter With an Integrated PRBS Generator,” SSC-L, 2018.

[3] N. van Thienen, et. al., “An 18Gbps Polymer Microwave Fiber (PMF) Communication Link in 40nm CMOS,” ESSCIRC, 2016.

[4] M. de Wit, et. al., “Analysis and Design of a Foam-Cladded PMF Link with Phase Tuning in 28-nm CMOS,” JSSC, 2019.

Tech.

Carrier

Freq.

(GHz)

Data Rate

(Gbps)BER

Waveguide

Coupler

Fiber Size

(WH, mm)

Demo

Link

Length

(cm)

TX DC

Power &

Efficiency

RX DC

Power &

Efficiency

Density

FOM

(Gbps/mm)

JSSC

2011 [1]

40nm

CMOS57, 80 12.5+12.5† <10-12 Quasi Yagi

(Off-Chip)81.1 120

56mW

2.2pJ/bit

87mW

3.5pJ/bit8.4

SSC-L

2018 [2]

55nm

SiGe130 36

<10-8

@ 25G

Vivaldi

(Off-Chip)1.31.3 100

216mW††

6pJ/bitNo RX 27.7

ESSCIRC

2016 [3]

40nm

CMOS120 17.7 <10-12 Tapered Slot

(Off-Chip)

2

(Circular)100

11.1mW

0.63pJ/bit

59.6mW

3.4pJ/bit8.9

JSSC

2019 [4]

28nm

CMOS140 12 <10-12 CPW-WG

(Off-Chip)1.91.0 100

65mW

5.4pJ/bit

165mW

13.8pJ/bit8.7

This Work130nm

BiCMOS

220, 260,

& 300

353‡ 510-8 Leaky SIW

(Integrated)0.40.25 30

256mW††

2.4pJ/bit

73mW‡‡

2.1pJ/bit332.0

303‡<10-12

†Full-duplex transmission (12.5Gbps each direction)

‡The link is demonstrated with a three-channel TX and one-channel RX

††Input signal sources (16.25GHz in [2], 43.3, & 20GHz in this work) not included

‡‡RX LO source (220~300 GHz) not included


Link Comparison

• Only published link incorporating a monolithically-integrated coupler

Tech.

Carrier

Freq.

(GHz)

Data Rate

(Gbps)BER

Waveguide

Coupler

Fiber Size

(WH, mm)

Demo

Link

Length

(cm)

TX DC

Power &

Efficiency

RX DC

Power &

Efficiency

Density

FOM

(Gbps/mm)

JSSC

2011 [1]

40nm

CMOS57, 80 12.5+12.5† <10-12 Quasi Yagi

(Off-Chip)81.1 120

56mW

2.2pJ/bit

87mW

3.5pJ/bit8.4

SSC-L

2018 [2]

55nm

SiGe130 36

<10-8

@ 25G

Vivaldi

(Off-Chip)1.31.3 100

216mW††

6pJ/bitNo RX 27.7

ESSCIRC

2016 [3]

40nm


(Off-Chip)

2

(Circular)100

11.1mW

0.63pJ/bit

59.6mW

3.4pJ/bit8.9

JSSC

2019 [4]

28nm

CMOS140 12 <10-12 CPW-WG

(Off-Chip)1.91.0 100

65mW

5.4pJ/bit

165mW

13.8pJ/bit8.7

This Work130nm

BiCMOS

220, 260,

& 300



256mW††

2.4pJ/bit

73mW‡‡

2.1pJ/bit332.0

303‡<10-12





[1] S. Fukuda, et. al., “A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect,” JSSC, 2011.





Link Comparison

• Smallest published waveguide cross section

Tech.

Carrier

Freq.

(GHz)

Data Rate

(Gbps)BER

Waveguide

Coupler

Fiber Size

(WH, mm)

Demo

Link

Length

(cm)

TX DC

Power &

Efficiency

RX DC

Power &

Efficiency

Density

FOM

(Gbps/mm)

JSSC

2011 [1]

40nm

CMOS57, 80 12.5+12.5† <10-12 Quasi Yagi

(Off-Chip)81.1 120

56mW

2.2pJ/bit

87mW

3.5pJ/bit8.4

SSC-L

2018 [2]

55nm

SiGe130 36

<10-8

@ 25G

Vivaldi

(Off-Chip)1.31.3 100

216mW††

6pJ/bitNo RX 27.7

ESSCIRC

2016 [3]

40nm


(Off-Chip)

2

(Circular)100

11.1mW

0.63pJ/bit

59.6mW

3.4pJ/bit8.9

JSSC

2019 [4]

28nm

CMOS140 12 <10-12 CPW-WG

(Off-Chip)1.91.0 100

65mW

5.4pJ/bit

165mW

13.8pJ/bit8.7

This Work130nm

BiCMOS

220, 260,

& 300



256mW††

2.4pJ/bit

73mW‡‡

2.1pJ/bit332.0

303‡<10-12










Link Comparison

• Total link efficiency similar to lower-frequency implementation

Tech.

Carrier

Freq.

(GHz)

Data Rate

(Gbps)BER

Waveguide

Coupler

Fiber Size

(WH, mm)

Demo

Link

Length

(cm)

TX DC

Power &

Efficiency

RX DC

Power &

Efficiency

Density

FOM

(Gbps/mm)

JSSC

2011 [1]

40nm

CMOS57, 80 12.5+12.5† <10-12 Quasi Yagi

(Off-Chip)81.1 120

56mW

2.2pJ/bit

87mW

3.5pJ/bit8.4

SSC-L

2018 [2]

55nm

SiGe130 36

<10-8

@ 25G

Vivaldi

(Off-Chip)1.31.3 100

216mW††

6pJ/bitNo RX 27.7

ESSCIRC

2016 [3]

40nm


(Off-Chip)

2

(Circular)100

11.1mW

0.63pJ/bit

59.6mW

3.4pJ/bit8.9

JSSC

2019 [4]

28nm

CMOS140 12 <10-12 CPW-WG

(Off-Chip)1.91.0 100

65mW

5.4pJ/bit

165mW

13.8pJ/bit8.7

This Work130nm

BiCMOS

220, 260,

& 300



256mW††

2.4pJ/bit

73mW‡‡

2.1pJ/bit332.0

303‡<10-12










Link Comparison

• Almost 12x improvement in data rate density figure of merit

Tech.

Carrier

Freq.

(GHz)

Data Rate

(Gbps)BER

Waveguide

Coupler

Fiber Size

(WH, mm)

Demo

Link

Length

(cm)

TX DC

Power &

Efficiency

RX DC

Power &

Efficiency

Density

FOM

(Gbps/mm)

JSSC

2011 [1]

40nm

CMOS57, 80 12.5+12.5† <10-12 Quasi Yagi

(Off-Chip)81.1 120

56mW

2.2pJ/bit

87mW

3.5pJ/bit8.4

SSC-L

2018 [2]

55nm

SiGe130 36

<10-8

@ 25G

Vivaldi

(Off-Chip)1.31.3 100

216mW††

6pJ/bitNo RX 27.7

ESSCIRC

2016 [3]

40nm


(Off-Chip)

2

(Circular)100

11.1mW

0.63pJ/bit

59.6mW

3.4pJ/bit8.9

JSSC

2019 [4]

28nm

CMOS140 12 <10-12 CPW-WG

(Off-Chip)1.91.0 100

65mW

5.4pJ/bit

165mW

13.8pJ/bit8.7

This Work130nm

BiCMOS

220, 260,

& 300



256mW††

2.4pJ/bit

73mW‡‡

2.1pJ/bit332.0

303‡<10-12










Conclusion

• Key passive device enablers demonstrated:

– Multiplexers and couplers

• Successful demonstration of first:

– Fully-monolithic,

– Sub-THz dielectric,

– Channel-aggregating link

• Competitive energy efficiency demonstrated in BiCMOS

• 3x improvement in lane capacity

• Approx. 12x improvement in lane capacity density


Acknowledgement

• Raytheon Technologies

• Intel Corporation

• Office of Naval Research (ONR)

• MIT Lincoln Laboratory

• Naval Research Laboratory (NRL)

• IHP


Thank you for your attention.

Documents

11.9: A 105 Gb/s Dielectric-Waveguide Link in 130nm BiCMOS … · 2021. 2. 24. · Mixer Sub-THz Source BD 1 2 BD 3 Sub-THz Source Freq. Synth. & Baseband Control TX Chip RX Chip