115KV SOLID STATE LONG PULSE MODULATORFOR THE EUROPEAN SPALLATION SOURCE (ESS)

M. Jaritz and J. BielaLaboratory for High Power Electronic Systems ETH Zurich, Physikstrasse 3, CH-8092 Zurich, Switzerland

Email: jaritz@hpe.ee.ethz.ch

Abstract

In this paper, the results of a 2.88MW solidstate long pulse modulator, which has been designed forthe new linear collider at the european spallation sourcein Lund, are summarized. The presented modulatorgenerates an output voltage pulse of 115 kV with a pulselength of 3.5ms. The modulator design is verified bymeasurements performed with a full scale prototype,which is operated under nominal load conditions. Allspecifications are well within the given limits and thesystem achieves a pulse efficiency of 96.78% and anoverall system efficiency of 91.88%.

I. INTRODUCTION

For performing the planned material science experi-ments at the new linear collider at the European SpallationSource (ESS) in Lund, 2.88MW long pulse modulatorswith a pulsed output voltage of 115 kV and pulse lengthsin the range of milliseconds are required (see Tab. 1).Applying direct switched topologies, as e.g. the approachpresented in [1], for these modulators have the drawbackthat the pulse generating components (e.g. the solid stateswitch) have to be designed for the full pulse voltage. Thisdrawback could be avoided by using pulse transformers.However, pulse transformer based topologies (e.g. [2], [3])require a huge transformer due to the high voltage timeproduct caused by the large pulse length. In order to avoidthe large transformers, series/parallel connected DC/DCconverters switching at a high frequency resulting in asmall voltage time product for the transformer can beused. Such DC/DC modules can be for example basedon single active bridge converters with transformer andoutput rectifier as presented in [4], or on soft switchedseries parallel resonance converters (SPRC) as shown inFig. 1 (b) and presented in [5], [6]. For generating thehigh output voltage, usually several modules are connectedin series at the output. Due to the resonant tank, theSPRC has sinusoidal currents and voltages resulting in lowEMI and allows ZVS for all switches, which is beneficialfor MOSFETs and enables high switching frequencies.Therefore, that topology is chosen for the consideredmodulator system. The SPRC topology consists of 18SPRC-basic modules (SPRC-Bm) (see Fig. 1 (b)), whichare operated at high switching frequencies (100 kHz -

Table 1. Modulator specifications

Pulse specifications

Pulse voltage VK −115 kV

Pulse current IK 25A

Pulse power PK 2.88MW

Pulse repetition rate PRR 14Hz

Pulse width TP 3.5ms

Pulse duty cycle D 0.05

Efficiency specifications

Pulse rise time (0..99% of VK) trise 150µs

Pulse fall time (100..10% of VK) tfall 150µs

System efficiency ηsys ≥ 90%

Pulse voltage ripple frequency specifications

f < 300Hz 1% of VK

300Hz < f ≤ 1 kHz 0.3% of VK

1 kHz < f ≤ 100 kHz 0.1% of VK

100 kHz < f ≤ 300 kHz 0.3% of VK

f > 300 kHz 1% of VK

110 kHz) to minimize the dimensions of the reactivecomponents and the transformers.

In this paper, a full scale prototype system and mea-surements of the output voltage pulse for such a SPRCmodulator system are presented. In section II, first theprototype system is presented and all design results aresummarized. Afterwards, the performance is evaluated bymeasured nominal output voltage pulses in section III.

II. PROTOTYPE SYSTEM

The modulator system and its basic block diagram aredepicted in Fig. 1 (a) and (b). A single SPRC-Bm of themodulator consists of a MOSFET full bridge, a resonanttank, a transformer and an output rectifier as presentedin [7] and depicted in Fig. 1 (b). Two SPRC-Bms areconnected in series at the input, sharing the same 800Vinput voltage bus, and in parallel at the output, formingan input series output parallel stack (ISOP). To achievethe full output voltage and to deliver the full ouput powergiven in Tab. 1, nine of these ISOP stacks are connectedin parallel at the input and in series at the output, formingan IPOS system (see Fig. 1 (b)). Each ISOP system also

Kly

stro

n/IO

T

Cf

1 ü:CS

CDL1

CDL2

CP

CP

CP

CP

LS

LDL

18-SPRC-Bmsin series and parallelconnection of single full modulator system

800VAC/DCIVCU

400 V3-phase50 Hz

IVCU

9 DC-balancing circuits1 for each ISOP

1 m

(a) (b)

2.4 m

Oil tank

4.5 m

SPRC-Bm1

VO1

IO1

12.5 A

12.77 kV

VO1

VsecIprim

VO2

Vout115 kV

Vin800 V S1

SB1

SB2

S2

S4S3

VDL2400 V

VDL3400 V

VDL4400 V

VDL17400 V

VDL18400 V

VO9

SPRC-Bm2

DC-B1

DC-B2

DC-B9

AC

DC

2 SPRC-Bms ISOP stack

2 SPRC-Bms ISOP stack

2 SPRC-Bms ISOP stack

SPRC-Bm17

SPRC-Bm18

SPRC IPOS modulator system

Balancing Circuit

SPRC-Bm3

SPRC-Bm4

VDL1400 V

Figure 1. (a) Full scale prototype system. The depicted setup includes two separate full modulator systems with 36SPRC-Bms in total. (b) Block diagram of one full modulator system. Two SPRC-Bms form an ISOP stack and 9 ofthem are connected in series forming an IPOS system. To balance the input voltages, active balancing circuits (DC-Bi)are used. The modulator system is powered by the input voltage charging unit (IVCU), which is a PFC boost converter.The full modulator system has been built by AMPEGON AG.

contains an active balancing circuit (DC-Bi) [8], whichequalizes the DC-link voltage VDL,i after each pulse.

For designing the modulator system, an optimizationprocedure has been presented in [9] for identifying theoptimal set of parameters and components, resulting inminimal losses. All optimization results are summarizedin Tab. 2.

The input voltage charging unit (IVCU) is based onan industrial PFC boost converter [10] with an efficiency> 98%. It is connected to the standard three phase 400Vgrid and provides the 800V DC-link voltage Vin for theSPRC-Bms.

An equal sharing of the SPRC-Bm output voltagescould be achieved purely by control. Additionally, adroop compensation for a constant pulse voltage, whichcompensates the input voltage droop due to the high powerconsumption during the pulse, is implemented. A detailedinvestigation of the different control systems is given in[8].

III. MEASUREMENT RESULTS

In the following, the measured output voltage pulse isevaluated with regard to the pulse specifications given inTab. 1.

A. Dynamic pulse perfomanceThe modulator system is designed for a nominal output

voltage of 115 kV. The switching frequency is starting at103.93 kHz at the beginning of the pulse and is ending at101.24 kHz in order to compensate the decreasing DC-link

Table 2. Optimization results of a single SPRC-Bm andoptimal number of modules.

Parameters and component values ofa single SPRC-Bm and the active balancing circuit

VO1 12.75 kV LS 4.199µH LDL 220µH

IO1 12.5A CS 0.837µF f 100 kHz-110 kHz

PO1 160 kW CP 4.23 nF fbal 37 kHz

VDL,i 400V CDL,i 30mF Dbal 0.3

# of turns for LS Type: HF-litz wire21 3 x6390 x0.071mm

# of capacitors for CS Type: SMD 2225896 C2225N153J102T

# of capacitors for a single CP Type: SMD 2220216 C5750C0G2J104J280KC

# of capacitors for CDL,i Type: Electrolytic3 Epcos B43455A5109M007

Semiconductors# of parallel switches Type: MAX247

6 x4 STY139N65M5# of rectifier diodes Type: SMD D3PAK

144 APT60DQ120SG# of IGBT half bridge Type: Infineon module

1 FF50R12RT4

Electric and magnetic parameters of the transformerVsec 12.75 kV Emax < 12 kV/mm

Iprim 1200A Bmax <= 200mT

n 20

Transformer coreType: Ferrite K2008 U126/20

# of cores: 16Transformer windings

Type: HF-litz wire# of Primary Wdg. 2 18 x405 x0.071mm

# of Secondary Wdg. 40 1125 x0.071mm

-115

-115

-115

-11.5

Vout

Vout

Vout,avg

Vout,avg

trise

t1 t2

t2

(a)

(b)

(c)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5Time t (ms)

-120

-100

-80

-60

-40

-20

0

20

Out

put v

olta

ge (k

V)

-0.05 0 0.05 0.1 0.15 0.2Time t (ms)

-120

-100

-80

-60

-40

-20

0

20

Out

put v

olta

ge (k

V)

3.45 3.5 3.55 3.6 3.65 3.7 3.75Time t (ms)

-120

-100

-80

-60

-40

-20

0

20

Out

put v

olta

ge (k

V)

K1

K2

K2

10 % of Vout

-113.85 = 99 % of Vout

tfall

Vout,avg

K1

Vout

Figure 2. (a) Measured output voltage pulse Vout andaveraged output voltage pulse Vout,avg (green line). (b)The zoomed view of the beginning of the pulse showsthe achieved rise time trise = 107.76µs. (c) The zoomedview of the end of the pulse shows the achieved fall timetfall = 83.48µs. The areas K1 and K2 represent the partof the transferred energy, which is lost.

capacitor voltage. Figure 2 (a) shows a measured outputvoltage pulse, where Vout is the output voltage and Vout,avg(green line) is the averaged voltage pulse, which is usedfor calculating the rise time trise and the fall time tfall. TheSPRC-Bms are working interleaved with an interleavingangle κ as given in [11].

The rise time is trise = 107.76µs (0..99% of VK) (seeFig. 2 (b)) and the fall time is tfall = 83.48µs (100..10%of VK) (see Fig. 2 (c)). Both times are well below thegiven limits in Tab. 1. The pulse efficiency ηpulse is the

-1 0 1 2 3 4 5Time t (ms)

-118

-117

-116

-115

-114

-113

-112

Out

put v

olta

ge (k

V)

Vout

Vout,avg

Figure 3. Zoom of the flat-top of the measured outputvoltage pulse Vout given in Fig. 2 (a). In addition, themeasured averaged output voltage pulse Vout,avg (greenline) is shown. The blue part of the flat-top is used fordetermining the ripple spectrum.

ratio between the ideal rectangular and the real pulse withlimited rise and fall time [12]

ηpulse =

(Kideal

Kreal

)· 100% = 96.78% (1)

withKideal = VK · (t1 − trise) (2)

Kreal =

∫ t2

0

Voutdt (3)

The areas K1 (see Fig. 2 (b)) and K2 (see Fig. 2 (c))represent the part of the transferred energy, which islost\cannot be used because the klystron load can justbe initiated at a certain high voltage level [3]. After thepulse dynamics, the ripple of the output voltage pulse inFig. 2 (a) is evaluated in the following.

B. Output voltage ripple evaluationFigure 3 shows a zoomed region of the flat-top of the

measured output voltage pulse of Fig. 2 (a). The blue part,which starts at trise and ends at t1, is used for calculatingthe ripple spectrum and results in the lowest resolvablefrequency component f1 of 294.8Hz with

f1 =1

t1 − trise(4)

The measured data is sampled at a rate of 250MS/sand has been processed with a moving average filter witha cutoff frequency of 104 kHz resulting in Vout,avg. Thisresulting averaged voltage gives a good indication for thelow frequency ripple during the flat-top (see Fig. 3). Theresulting output voltage ripple spectrum is depicted inFig. 4. There, an overview is given for the full spectrumfrom 0 to 6MHz (Fig. 4 (a)) and for the low frequencyrange from 0 to 1 kHz (Fig. 4 (b)). It is clearly visiblethat all frequency components are well within the yellowarea, which indicates the maximum allowed peak to peak

Frequency f (kHz)0 1 2 3 4 5 6 7 8 9 10

0

200

400

600

800

1000

1200

Peak

to p

eak

rippl

e sp

ectru

m (V

)

0 1 2 3 4 5 6Frequency f (MHz)

0

100

200

300

400

500

600

700

Pea

k to

pea

k rip

ple

spec

trum

(V)

(a)

(b)

f1 = 294.8 Hz

f1 = 294.8 Hz

f ≈ 200 kHz

f ≈ 400 kHz

Maximal allowed peak to peak ripple voltage area

Maximal allowed peak to peak ripple voltage area

Figure 4. Ripple spectrum of the analyzed output voltagepulse in Fig. 3. (a) Full spectrum from 0Hz to 6MHz. (b)Zoomed view of the spectrum from 0Hz to 10 kHz. Themain ripple frequency of the output voltage of a singleSPRC-Bm is around 200 kHz. The yellow area indicatesthe maximum allowed peak to peak ripple voltage for eachfrequency component, according to Tab. 1.

Table 3. System efficiency

Single SPRC-Bm efficiency 93.75%

Efficiency of the IVCU 98%

Overall system# of SPRC-Bms in parallel and series 2 x9

System efficiency ηsys 91.88%

Output voltage pulse parametersPulse rise time trise 107.76µs

Pulse fall time tfall 83.48µs

Pulse efficiency ηpulse 96.78%

ripple voltage for each frequency component (see Tab. 1).The main switching frequency is around 100 kHz andbecause of the full wave output rectifier, the main outputvoltage ripple frequency of a single SPRC-Bm is around200 kHz. Despite the interleaving of all SPRC-Bms, alsomultiples of the 200 kHz appear in the spectrum below 9 x200 kHz due to the component tolerances. Table 3 lists theachieved system performance. The designed system easilyfulfills the global pulse specifications from Tab. 1 andachieves a system efficiency ηsys of 91.88%. For the entiresystem 18 SPRC-Bm (2 x 9 units connected in parallel)are required.

IV. CONCLUSION

In this paper, a long pulse modulator prototype systemis presented and a detailed description of the measuredpulse parameters is given. Two SPRC-Bms connected inseries at the input and in parallel at the output formingan ISOP stack. To generate the given output voltage of115 kV, nine of this ISOP stacks are connected in series.The measured output voltage pulses are well within thegiven specification. The achieved rise time of 107.76µsand the achieved fall time of 83.48µs result in a pulseefficiency of 96.78%. The efficiency of a single seriesparallel resonant module is 93.75% and the overall systemefficiency is 91.88%.

ACKNOWLEDGMENT

The authors would like to thank the project partners CTIand Ampegon AG very much for their strong support ofthe CTI-research project 13135.1 PFFLR-IW.

References

[1] M. Kempkes, K. Schrock, R. Ciprian, T. Hawkey, and M. P. J.Gaudreau, “A Klystron Power System for the ISIS Front End TestStand,” in IEEE Int. Vacuum Electron. Conf., April 2009, pp. 493–494.

[2] H. Pfeffer, L. Bartelson, K. Bourkland, C. Jensen, Q. Kerns,P. Prieto, G. Saewert, and D. Wolff, “A long pulse modulator forreduced size and cost,” in Proc. Conf. Power Modulator Symp.,1994, pp. 48–51.

[3] S. Blume and J. Biela, “Optimal transformer design for ultraprecisesolid state modulators,” IEEE Trans. Plasma Sci., vol. 41, no. 10,pp. 2691–2700, 2013.

[4] C. Martins, M. Collins, G. Goransson, and M. Kalafatic, “PulsedHigh Power Klystron Modulators for ESS Linac Based on theStacked Multi-Level Topology,” in Proc. 28th Linear AcceleratorConf. (LINAC’16), 25-30 Sept. 2016, pp. 359–362.

[5] M. Jaritz and J. Biela, “Optimal Design of a Modular Series ParallelResonant Converter for a Solid State 2.88 MW/115-kV Long PulseModulator,” IEEE Trans. Plasma Sci., no. 99, 2014.

[6] M. Jaritz, S. Blume, D. Leuenberger, and J. Biela, “Experimentalvalidation of a series parallel resonant converter model for a solidstate 115-kv long pulse modulator,” IEEE Trans. Plasma Sci.,vol. 43, no. 10, pp. 3392–3398, 2015.

[7] M. Jaritz and J. Biela, “Optimal design of a modular 11kW seriesparallel resonant converter for a solid state 115-kV long pulsemodulator,” in 19th IEEE Pulsed Power Conf. (PPC), 2013, pp.1–6.

[8] M. Jaritz, T. Rogg, and J. Biela, “Analytical Modelling andController Design of a Modular Series Parallel Resonant ConverterSystem for a Solid State 2.88MW/115-kV Long Pulse Modulator,”Submitted for Review to the IEEE Trans. Power Electron.

[9] M. Jaritz and J. Biela, “Optimal Design of a Series ParallelResonant Converter for a Solid State Long Pulse Modulator,” in4th Euro-Asian Pulsed Power Conf. (EAPPC), 2012.

[10] [Online]. Available: http://www.revcon.de/fileadmin/pdf/datenblaetter/RSU d DB.pdf, accessed April. 10, 2017

[11] M. Jaritz and J. Biela, “Output Voltage Ripple Analysis for Mod-ular Series Parallel Resonant Converter Systems with CapacitiveOutput Filter,” Submitted for Review to the IEEE Trans. PowerElectron.

[12] D. Aguglia and E. Sklavounou, “Klystron modulators capacitorchargers design compromises for ac power quality increase of theCompact Linear Collider (CLIC),” in Int. Symp. Power Electron.,Elect. Drives, Autom. Motion, June 2012, pp. 1535–1541.