11002_GS2.pdf

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2005 Microchip Technology Incorporated. All Rights Reserved. 2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 1

11002 GS2

Getting Started withPICMCU Mid-Range

AArrcchhiitteeccttuurree,,IInnssttrruuccttiioonnSSeettaannddAAsssseemmbbllyyLLaanngguuaaggeePPrrooggrraammmmiinngg

2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 2

Class Objective

When you finish this class you will:

Understand the basics of the innerworkings of a PIC16

Understand most instructions

Understand memory organization

Understand how to write simpleprograms

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Agenda

Architecture Basics

Instruction Set Overview Memory Organization and

Addressing Modes

Special Features

Hands-on Exercises


Architecture The high performance of the PIC

microcontroller can be attributed to the

following architectural features:

Harvard Architecture

Instruction Pipelining

Large Register File

Single Cycle Instructions

Single Word Instructions

Long Word Instructions

Reduced Instruction Set

Orthogonal Instruction Set

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Harvard Architecture

Von NeumannArchitecture:

Fetches instructions and

data from a single memoryspace

Limits operating bandwidth

Harvard Architecture:

Uses two separate memoryspaces for programinstructions and data

Improved operating

bandwidth Allows for different bus

widths


Instruction Pipelining Instruction fetch is overlapped with execution of previously

fetched instruction

call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54

Example ProgramFetch Execute

T0

Flush

T1 T2 T3 T4 T5

Instruction Cycles

T6

Fetch Execute

Fetch Execute

Fetch

Fetch Execute

Fetch Execute

Fetch Flush

Fetch

T7

Time to execute normal instruction

Time to execute call

instruction includes

pipeline flush

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call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54

Example ProgramFetch

T0

Instruction Cycles

movlw 0x05 -

Pre-Fetched Instruction Executing Instruction



call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0 T1

Instruction Cycles

Fetch

movwf REG1 movlw 0x05


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call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0 T1 T2

Instruction Cycles

Fetch Execute

Fetch

call SUB1 movwf REG1


Time to execute normal instruction



call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0 T1 T2 T3

Instruction Cycles

Fetch Execute

Fetch Execute

Fetch

addwf REG2 call SUB1


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call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0

Flush

T1 T2 T3 T4

Instruction Cycles

Fetch Execute

Fetch Execute

Fetch

Fetch

movf PORTB,w call SUB1


Time to execute call

instruction includes

pipeline flush



call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0

Flush

T1 T2 T3 T4 T5

Instruction Cycles

Fetch Execute

Fetch Execute

Fetch

Fetch Execute

Fetch

return movf PORTB,w


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call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0

Flush

T1 T2 T3 T4 T5

Instruction Cycles

T6

Fetch Execute

Fetch Execute

Fetch

Fetch Execute

Fetch Execute

Fetch

movf PORTC,w return




call SUB1

addwf REG2

movf PORTB,w

return

movf PORTC,w

return

SUB1

SUB2

movlw 0x05MAIN

movwf REG1

1

2

3

4

51

52

53

54


T0

Flush

T1 T2 T3 T4 T5

Instruction Cycles

T6

Fetch Execute

Fetch Execute

Fetch

Fetch Execute

Fetch Execute

Fetch Flush

Fetch

T7

addwf REG2 return


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Long Word Instruction8-bit Program Memory

14-bit Program Memory

11 00 00 00 00 11 11 00

kk kk kk kk kk kk kk kk

11 11 00 00 00 00 kk kk kk kk kk kk kk kk

8-bit Instruction on typical 8-bit MCU

Example: Freescale Load Accumulator A: 2 Program Memory Locations 2 Instruction Cycles to Execute

14-bit Instruction on PIC16 8-bit MCU

Example: Move Literal to Working Register 1 Program Memory Location 1 Instruction Cycle to Execute

Limits

Bandwidth Increases

Memory SizeRequirements

Separate busses allow different widths

2k x 14 is roughly equivalent to 4k x 8

ldaa #k

movlw k


Register File Concept

Data

Bus

Data

Bus

d

OpcodeOpcode dd AddressAddressDecoded Instruction

from Program

Memory:

Arithmetic/Logic

Function to be Performed Result

Destination

Address of Second

Source Operand

Register File Concept:

All of data memory is

part of the register

file, so any location in

data memory may be

operated on directly

All peripherals are

mapped into data

memory as a series of

registers

Orthogonal

Instruction Set: ALL

instructions can

operate on ANY data

memory location

The Long Word

Instruction format

allows a directly

addressable register

file

w f

w f

ALU

WW

Data Memory

(Register File)

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

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Instruction Set Overview



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PIC16 Instruction SetByte Oriented OperationsByte Oriented Operations Bit Oriented OperationsBit Oriented Operations

addwf f,daddwf f,d

andwf f,dandwf f,d

clrf f clrf f

clrw -clrw -

comf f,dcomf f,d

decf f,ddecf f,d

decfsz f,ddecfsz f,d

incf f,dincf f,d

incfsz f,dincfsz f,d

iorwf f,diorwf f,d

movf f,dmovf f,d

movwf f movwf f

nop -nop -

rlf f,drlf f,d

rrf f,drrf f,d

subwf f,dsubwf f,d

swapf f,dswapf f,d

xorwf f,dxorwf f,d

Add W and fAdd W and f

AND W with fAND W with f

Clear fClear f

Clear WClear W

Complement fComplement f

Decrement fDecrement f

Decrement f, Skip if 0Decrement f, Skip if 0

Increment fIncrement f

Increment f, Skip if 0Increment f, Skip if 0

Inclusive OR W with fInclusive OR W with f

Move fMove f

Move W to fMove W to f

No OperationNo Operation

Rotate Left f through CarryRotate Left f through Carry

Rotate Right f through CarryRotate Right f through Carry

Subtract W from fSubtract W from f

Swap nibbles in fSwap nibbles in f

Exclusive OR W with fExclusive OR W with f

bcf f,bbcf f,b

bsf f,bbsf f,b

btfsc f,bbtfsc f,b

btfss f,bbtfss f,b

Bit Clear fBit Clear f

Bit Set fBit Set f

Bit Test f, Skip if ClearBit Test f, Skip if Clear

Bit Test f, Skip if SetBit Test f, Skip if Set

Literal and Control OperationsLiteral and Control Operations

addlw kaddlw k

andlw kandlw k

call kcall k

clrwdt -clrwdt -

goto kgoto k

iorlw kiorlw k

movlw kmovlw k

retfie -retfie -

retlw kretlw k

return -return -

sleep -sleep -

sublw ksublw k

xorlw kxorlw k

Add literal and WAdd literal and W

AND literal with WAND literal with W

Call subroutineCall subroutine

Clear Watchdog TimerClear Watchdog Timer

Go to addressGo to address

Inclusive OR literal with WInclusive OR literal with W

Move literal to WMove literal to W

Return from interruptReturn from interrupt

Return with literal in WReturn with literal in W

Return from SubroutineReturn from Subroutine

Go into standby modeGo into standby mode

Subtract W from literalSubtract W from literal

Exclusive OR literal with WExclusive OR literal with W

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PIC16 Visual Interpreter

ADDLW 0x0A Execute

Register File Address

d

FFFFFFW Register

FFFFFFFFFFFFFFFFFF181818FFFFFFFFFFFF

FFFFFFFFFFFFFFFFFFFFFFFF

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

w f

w f

ALU

111 00 000

Z DC C

STATUS

Data

Bus

Reset

Hex

Dec

Bin

Literal Data from

Instruction Word

,,

012


Data Memory Organization

Accesses

70h 7Fh

Accesses

70h 7FhAccesses

70h 7Fh

Accesses

70h 7FhAccesses

70h 7Fh

Accesses

70h 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

PIC16F876/877 Register File Map

368 Bytes of General Purpose RAM Plus Special Function Registers

000h

01Fh

020h

07Fh

080h

09Fh

0A0h

0FFh

100h

110h

17Fh

180h

190h

1FFh

0EFh 16Fh 1EFh

10Fh 18Fh

128 Bytes

SFR SFR SFR SFR

GPR

96 Bytes

GPR

80 Bytes

GPR

96 Bytes

GPR

96 Bytes

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Data Memory Organization

INDFINDF

TMR0TMR0

PCLPCL

STATUSSTATUS

FSRFSR

PORTAPORTA

PORTBPORTB

PORTCPORTC

PORTDPORTD

PORTEPORTE

PCLATHPCLATH

INTCONINTCON

INDFINDF

OPTION_REGOPTION_REG

PCLPCL

STATUSSTATUS

FSRFSR

TRISATRISA

TRISBTRISB

TRISCTRISC

TRISDTRISD

TRISETRISE

PCLATHPCLATH

INTCONINTCON

INDFINDF

TMR0TMR0

PCLPCL

STATUSSTATUS

FSRFSR

PORTBPORTB

PCLATHPCLATH

INTCONINTCON

INDFINDF

OPTION_REGOPTION_REG

PCLPCL

STATUSSTATUS

FSRFSR

TRISBTRISB

PCLATHPCLATH

INTCONINTCON

PIR1PIR1 PIE1PIE1 EEDATAEEDATA EECON1EECON1

PIR2PIR2 PIE2PIE2 EEADREEADR EECON2EECON2

Bank 0 Bank 1 Bank 2 Bank 3

000

001

002

003

004

005

006

007

008

009

00A

00B

00C

00D

080

081

082

083

084

085

086

087

088

089

08A

08B

08C

08D

100

101

102

103

104

105

106

107

108

109

10A

10B

10C

10D

180

181

182

183

184

185

186

187

188

189

18A

18B

18C

18D

Device Specific Registers


STATUS RegisterIRPIRP RP1RP1 RP0RP0 TOTO PDPD ZZ DCDC CC

bit 7 bit 0

IRP: Register Bank Select (used for Indirect addressing)

0 = Bank 0, 1 1 = Bank 2, 3

RP1:RP0: Register Bank Select Bits (used for direct addressing)

00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3

TO: Time-out bit

0 = A WDT time-out occurred

PD: Power-down bit

0 = SLEEP instruction executed

Z: Zero bit

1 = Result of arithmetic operation is zero

DC: Digit cary / borrow bit

1 = Carry out of 4 th low order bit occurred / No borrow occurred

C: Carry / borrow bit

1 = Carry out of MSb occurred / No borrow occurred

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PIC16 Addressing Modes

Data Memory Access:

Direct addwf ,

Indirect addwf INDF,

Immediate (Literal)movlw

Program Memory Access:

Absolute goto

Relative addwf PCL,f


Register Direct Addressing

FFFF

FFFF

FFFF

1818

FFFF

FFFF

FFFF

FFFF

FFFF

1C1C

FFFF

FFFF

00h

01h

02h

03h

04h

05h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

RP1

Bank 1 Bank 2 Bank 3

00 00 0x1830x18300

2-bits from

STATUS Register 7-bits Encoded in Instruction

9-bit Effective Address

(Use this when coding)

Bank 0

RP0 f Operand

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

00 00 00 00 00 00

Register File

Address BusAddress

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FFFFFF

FFFFFF

FFFFFF383838

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFFFFFFFF

Register Direct Addressing

80h : INDF

81h : OPTION

82h : PCL83h : STATUS

Bank 1

FFFFFF

FFFFFF

FFFFFF383838

Address

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFF

FFFFFFFFFFFF

84h : FSR

85h : TRISA

86h : TRISB

87h : TRISC

Bank 0

INDF: 00h

TMR0: 01h

PCL : 02hSTATUS: 03h

Address

FSR: 04h

PORTA: 05h

PORTB: 06h

PORTC: 07h

20h

22h

21h

23h

A0h

A2h

A1h

A3h

Register File

bsf STATUS,RP0

movlw b11110000

movwf TRISB

bcf STATUS,RP0clrf PORTB

000 000 000 000 000 000 000 000 000

9-Bit Effective Address:

7-bits from InstructionRP0RP1

Bin Dec Hex

Example: Initialize bits 0-3 of

PORTB as outputs

F0F0F0

W Register:


000

Register Indirect Addressing

FFFF

FFFF

FFFF

FFFF

1C1C

FFFF

FFFF

000h

001h

002h

003h

004h

005h

0FAh

0FBh

0FCh

0FDh

0FEh

0FFh

IRP

Bank 2,3

000 000 0x1FC0x1FC0x1FC

1-bit from

STATUS Register 8-bits from FSR Register

9-bit Effective Address

(Use this when coding)

Bank 0,1

FSR

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

000 000 000 000 000 000

Register File

Address Bus

100h

101h

102h

103h

104h

105h

1FAh

1FBh

1FCh

1FDh

1FEh

1FFh

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0000

FFFF

Register Indirect Addressing

00h : INDF

02h : PCL

03h : STATUS

04h : FSR

20h

21h

22h

23h

80h

7Fh

7Eh

7Dh

Register File

LOOP

movlw 0x20

movwf FSR

clrf INDF

incf FSR,f

btfss FSR,7goto LOOP

FFFF

1818

8080

Address

0000

0000

0000

0000

0000

0000

0000

FFFF

01h : TMR0

Example: Clear all RAM locations from 20h to 7Fh

bcf STATUS,IRP

00 00 00 00 00 00 00 00 00

9-Bit Effective Address:

FSRIRP

2020

W Register:


Program Memory Organization

Program memory is

divided into four 2k14

pages

Required to maintain

single word/single

cycle execution

Paging is only a

concern when using

the call or goto

instructions, or when

directly modifying the

program counter

Reset VectorReset Vector

Interrupt VectorInterrupt Vector

Page 0PCH = 00h

Page 0PCH = 00h

Page 1PCH = 08h

Page 1PCH = 08h

Page 2PCH = 10h

Page 2PCH = 10h

Page 3PCH = 18h

Page 3PCH = 18h

0000h

0004h

0800h

1000h

1800h

1FFFh

2k

2k

2k

2k

14-bits

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Program Counter

00 00 00 00 00

0123456789101112

PCLPCH

00 00 00 00 00 00 00 00Program Counter

13-bit PC can access up to 213 = 8192 words Contains address of NEXT instruction (pipelining)

Lower byte accessible in data memory as PCL

Upper byte indirectly accessible via PCLATH

Runs freely across page boundaries

Events that modify PC out of sequence:

Interrupts

Instructions: CALL, GOTO, RETURN, RETLW, RETFIE

Any instruction that uses the PCL register as an operand


PC Absolute Addressing0123456789101112

OpcodeOpcode 00 00 00 00 00

CALL and GOTO Instructions:

13

00 00 00 00 00 00

PC Absolute Addressing (Program Memory)

Jump to another program memory location out of PC sequence

Call a subroutine

Used by the CALL and GOTO instructions

11-bits of the required 13 address bits are encoded in the

instruction

2 additional bits will come from the PCLATH register

Used when performing Computed Goto operation

Address to jump to is calculated by the program

Computed address is written directly into the Program Counter

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00 00

1112

PC Absolute Addressing

0123456789101112


13

00 00 00 00 00 00

-- -- -- 00 00 00 00 00

01234567

PCLATH Register in Data Memory

14-Bit CALL or GOTO Instruction in Program Memory

012345678910

00 00 00 00 00 00 00 00 00 00 00

13-Bit Program Counter

2-Bits From PCLATH11-Bits From

Instruction

PCHPCHPCH PCLPCLPCL


-- 00 00

PC Absolute Addressing

MySubroutine

movlw HIGH MySubroutinemovwf PCLATHcall MySubroutineorg 0x1250return

Example: Jumping to code located in a different program memory page.

-- -- -- 00 00 00 00 00

01234567

PCLATH Register

0123456789101112


13

00 00 00 00 00 00

CALL Instruction in Program Memory

FFFF

W Register Program Counter - PCH:PCL

00 00 00 00 00 00 00 00 00 00 00

org 0x0020

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00200020

CALL / RETURN Stack13-bit Program Counter

13-bit x 8-LevelReturn Address Stack

movlw HIGH MySub1

movwf PCLATH

call MySub1

call MySub4

bsf PORTB,0

call MySub2

return

bsf PORTB,1

call MySub3

return

bsf PORTB,2

return

bsf PORTB,3

call MySub2

return

bsf PORTB,7

MySub1

1002

1001

1000

0024

0023

0022

0021

0020

1009

1008

1007

1006

1005

1004

1003

100A

MySub2

MySub3

MySub4

0

1

2

3

4

5

6

7


8-bit Data Bus

PC Relative Addressing

FFFFFF

FFFFFF FFFFFF

To write to PC:

Write high byte to

PCLATH

Write low byte to PCL

(PCH will be loaded withvalue from PCLATH)

PCLATH

PCH PCL

movlw HIGH 0x1250

movwf PCLATH

movlw LOW 0x1250

movwf PCL

FFFFFFW Register

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PC Relative Addressing: LookupTable

PIC

MCU

Example: Use a lookup

table with relative

addressing to retrieve the

bit pattern to display a digiton a 7-segment LED

ORG 0x0020 ;Page 0movlw HIGH SevenSegDecodemovwf PCLATHmovlw .5call SevenSegDecode

movwf PORTB

ORG 0x1800 ;Page 3SevenSegDecode:

addwf PCL,fretlw b00111111 ;0retlw b00000110 ;1retlw b01011011 ;2retlw b01001111 ;3retlw b01100110 ;4retlw b01101101 ;5

retlw b01111101 ;6retlw b00000111 ;7retlw b01111111 ;8retlw b01101111 ;9


Special FeaturesOverview

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POR, OST, PWRT

POR: Power On Reset

With MCLR tied to VDD, a

reset pulse is generated when

VDD rise is detected

PWRT: Power Up Timer

Device is held in reset for

72ms (nominal) to allow VDDto rise to an acceptable level

(after POR only)

OST: Oscillator Start-up Timer

Holds device in reset for 1024

cycles to allow crystal or

resonator to stabilize in

frequency and amplitude; not

active in RC modes; used

only after POR or Wake Up

from SLEEP


Events that wake processor from sleepEvents that wake processor from sleep

MCLRMCLR

WDTWDT

INTINT

TMR1TMR1

ADCADC

CMPCMP

CCPCCP

PORTBPORTB

SSPSSP

PSPPSP

Sleep Mode The processor can be put into a power-down

mode by executing the SLEEP instruction System oscillator is stopped

Processor status is maintained (static design)

Watchdog timer continues to run, if enabled

Minimal supply current is drawn - mostly due to leakage (0.1 -2.0A typical)

Master Clear Pin Asserted (pulled low)Master Clear Pin Asserted (pulled low)

Watchdog Timer TimeoutWatchdog Timer Timeout

INT Pin InterruptINT Pin Interrupt

Timer 1 Interrupt (or also TMR3 on PIC18)Timer 1 Interrupt (or also TMR3 on PIC18)

A/D Conversion Complete InterruptA/D Conversion Complete Interrupt

Comparator Output Change InterruptComparator Output Change Interrupt

Input Capture EventInput Capture Event

PORTB Interrupt on ChangePORTB Interrupt on Change

Synchronous Serial Port (I2C Mode) Start / Stop Bit Detect InterruptSynchronous Serial Port (I2C Mode) Start / Stop Bit Detect Interrupt

Parallel Slave Port Read or WriteParallel Slave Port Read or Write

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Watchdog Timer

Helps recover from software malfunction

Uses its own free-running on-chip RC oscillator

WDT is cleared by CLRWDT instruction

Enabled WDT cannot be disabled by software

WDT overflow resets the chip

Programmable timeout period: 18ms to 3.0s typical

Operates in SLEEP; on time out, wakes up CPU


BOR Brown Out Reset

When voltage drops below aparticular threshold, the device isheld in reset

Prevents erratic or unexpectedoperation

Eliminates need for external BORcircuitry

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PBOR ProgrammableBrown Out Reset

Configuration Option (set at program time)

Cannot be enabled / disabled in software

Four selectable BVDD trip points:

2.5V Minimum VDD for OTP PIC MCUs

2.7V

4.2V

4.5V

For other thresholds, use an externalsupervisor (MCP1xx, MCP8xx/TCM8xx, or

TC12xx)


(P)BOR Brown Out Reset Holds PICMCU in reset until ~72ms after VDD rises back above threshold

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PLVD Programmable LowVoltage Detect

Early warning

before brown out

16 selectable trippoints:

1.8V up to 4.5V

in 0.1 to 0.2V

steps

External analog

input

Internal VREF

VDD LVDIN

LVDIN

LVDCON

VREF

LVDIF

16-bitMultiplexer


In-Circuit SerialProgramming

Only two pins required forprogramming

Convenient for In-SystemProgramming of Calibration Data

Serialization Data

Supported by MPLABPM3 & ICD2

PinPinPin

VPPVPP

VDDVDD

VSS

VSS

RB6RB6

RB7RB7

FunctionFunctionFunction

Programming Voltage = 13VProgramming Voltage = 13V

Supply VoltageSupply Voltage

GroundGround

Clock InputClock Input

Data I/O & Command InputData I/O & Command Input

MCLR/VPP

VDD

VSS

RB6

RB7

To application circuit

VDD

VDD

Application PCB

ICSP Connector

Isolationcircuits

ICSP Connector

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I/O Ports

High Drive Capability

Can directly drive LEDs

Direct, single cyclebit manipulation

Each pin has individual

direction control under software

All pins have ESD protection diodes

Pin RA4 is usually open drain

All I/O pins default to inputs (high impedance) on

startup All pins multiplexed with analog functions default to

analog inputs on startup


I/O Pin Conceptual Diagram

Bit 1 of TRISB

Register

PORTB

Bit 1

Latch

RB1Bit 1 of

Data Bus

Read

Operation

Write

Operation

movwf PORTB

movf PORTB,w

1 = RB1 is input

0 = RB1 is output

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I/O Ports

Bit n in TRISx controls the data

direction of Bit n in PORTx 1 = Input, 0 = Output


Hands-onExercises

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MPLABICD2


PICDEM 2 Plus Board

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MPASM AssemblerTemplate

If not using interrupts, lines 8 and 9 could be omitted

The labels in the left column may be anything youwant; these are just examples

12

3456789

10111213

LIST p=16f877a ;Explicitly declare processor

#include ;Include register label definitions

org 0x0000 ;Put next line of code at address 0x0000RESET_V goto START ;Reset Vector

org 0x0004 ;Put next line of code at address 0x0004INT_V retfie ;Interrupt Vector

START {Begin your code here} ;Your code goes here

END ;Tell MPASM that this is the end

12

345678910111213

LISTp=16f877a ;Explicitly declare processor

#include ;Include register label definitions

org 0x0000 ;Put next line of code at address 0x0000RESET_V goto START ;Reset Vector

org 0x0004 ;Put next line of code at address 0x0004INT_V retfie ;Interrupt Vector

START {Begin your code here} ;Your code goes here

END ;Tell MPASM that this is the end


RadixRadix MPASM SyntaxMPASM Syntax

Specifying the Radix By default, MPASM assembler expects numbers in hexadecimal

Default can be changed through IDE or by adding r=hex or r=decas a parameter to the LIST directive:

Good programming practice suggests that a numbers radix bespecified explicitly:

LIST p=16f877a, r=decLIST p=16f877a, r=dec

BinaryBinary b10101010b10101010

DecimalDecimal d25 or .25d25 or .25

HexadecimalHexadecimal h2A or 0x2Ah2A or 0x2A

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Lab 1: The Task

Turn on LED connected to bit 0

of PORTB (RB0)


Lab 1: Program Structure

1 Instruction

4 Instructions

1 Instruction

1 Instruction: goto $(Go to self)

Switch to Bank 1

Load number into W

Move value toTRISB

Switch to Bank 0

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Lab 1: Template


Lab 1: Solution

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Lab 1: Results

You have learned:

How to program a device and run thecode using the MPLAB ICD2

How to configure an I/O port

How to manipulate I/O pins

How to code an infinite loop (theequivalent of while(1) in C)


Lab 2: The Task

Make the LED connected to bit 0of PORTB (RB0) blink

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Lab 2: The Task

A delay is required to make the

blinking slow enough for thehuman eye

At 4MHz, one instructionexecutes in 1s

A 16-bit software counter is

sufficient to implement the delay


NamingRegisters/Constants

Equate Method:MyReg0equ0x20 ;MyReg0 = 0x20MyReg1equ0x21 ;MyReg1 = 0x21MyReg2equ0x23 ;MyReg2 = 0x23

Constant Block Method:CBLOCK0x20MyReg0 ;MyReg0 = 0x20MyReg1: 2 ;MyReg1 = 0x21MyReg2 ;MyReg2 = 0x23ENDC

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Taken from Lab 1

1 Instruction

1 Instruction

Subroutine Call

1 Instruction

1 Instruction

Subroutine Call



1 Instruction

1 Instruction

1 Instruction

1 Instruction

1 Instruction

Delay Subroutine

Hint: Use decfsz

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Lab 2: Template Part 1



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Lab 2: Solution Part 1



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Lab 2: Results

You have learned:

How to define register labels How to implement a loop

How to implement software delays

How to use a skip instruction

How to call a subroutine


Lab 3: The Task

Using one of the rotateinstructions, move theilluminated LED across the lower4 bits of PORTB. When it

reaches one side, send it back tothe start.

RB0RB1RB2RB3

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1 Instruction

1 Instruction

Same setup code from Lab 1

1 Instruction

1 Instruction

1 Instruction

Call same subroutine from Lab 2

Rember: The rotate

instructions operate

on 9-bits, with the

Carry bit in the

STATUS register as

the 9th bit



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Lab 3: Results

You have learned:

How to use the rotate instructions

How to use the bit test & skipinstructions

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Lab 4: The Task

Same as Lab 3, but this time

make the direction of rotationchange when the LED is rotatedto either end



Set Carry Bit

Delay

Rotate Left

PORTB

RB3 = 1?

Yes

No

Setup PORTB

START

Rotate Right

PORTB

Delay

RB0 = 1?

No

Yes

bsf STATUS,C

Same setup code from Lab 1

1 Instruction

1 Instruction

Subroutine Call

2 Instructions

1 Instruction

1 Instruction

Subroutine Call

2 Instructions

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Lab 4: Template

Setup is identical to Lab 3 up to the LOOPLab 3: Rotating LED - Continued

181920212223242526272829303132

3334353637

bsf STATUS,C ;Set carry bit for initial rotate

LEFT {1stInstruction} ;Rotate PORTB to left{2ndInstruction} ;Call delay routine{3rdInstruction} ;Is the LED on RB3 (PORTB,3) on?{4th Instruction} ;if no, rotate left again

RIGHT {5th Instruction} ;Rotate PORTB to right{6th Instruction} ;Call delay routine{7thInstruction} ;Is the LED on RB0 (PORTB,0) on?{8th Instruction} ;if no, rotate right again{9th Instruction} ;if yes, rotate left

DELAY decfsz COUNTERL ;Decrement COUNTERLgoto DELAY ;If not zero, keep decrementing COUNTERL

decfsz COUNTERH ;Decrement COUNTERHgoto DELAY ;If not zero, decrement COUNTERL againreturn ;Return to main subroutine

END

Lab 3: Rotating LED - Continued

1819202122232425262728293031323334353637

bsf STATUS,C ;Set carry bit for initial rotate

LEFT {1stInstruction} ;Rotate PORTB to left{2ndInstruction} ;Call delay routine{3rdInstruction} ;Is the LED on RB3 (PORTB,3) on?{4th Instruction} ;if no, rotate left again

RIGHT {5th Instruction} ;Rotate PORTB to right{6th Instruction} ;Call delay routine{7thInstruction} ;Is the LED on RB0 (PORTB,0) on?{8th Instruction} ;if no, rotate right again{9th Instruction} ;if yes, rotate left

DELAY decfsz COUNTERL ;Decrement COUNTERLgoto DELAY ;If not zero, keep decrementing COUNTERL

decfsz COUNTERH ;Decrement COUNTERHgoto DELAY ;If not zero, decrement COUNTERL againreturn ;Return to main subroutine

END


Lab 4: Solution

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Lab 4: Results

You have learned:

How to make decisions in softwareand take different courses of action


Lab 5: The Task

Use a lookup table to obtain thebit pattern to be displayed onPORTB

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Lab 1 Setup Code

1 Instruction

2 Instructions

1 Instruction

1 Instruction

1 Instruction

1 Instruction

Subroutine Call

1 Instruction

3 Instructions

1 Instruction


Lab 5: Template Part 1Lab 5: Lookup Table

12345678910

11121314151617181920

LISTp=16f877a

#include

cblock0x020 COUNTERL COUNTERHendc

org 0x0000

RESET_V goto START ;Reset Vector

START clrf PORTB ;Clear PORTB output latchesbsf STATUS,RP0 ;Switch to bank 1movlw b11110000' ;Load value to make lower 4 bits outputsmovwf TRISB ;Move value to TRISBbcf STATUS,RP0 ;Switch to bank 0{1stInstruction} ;Clear index into table{2ndInstruction} ;Load W with high byte of TABLE address{3rdInstruction} ;Move W to PCLATH

;CONTINUED ON NEXT SLIDE

Lab 5: Lookup Table

12345678910

11121314151617181920

LISTp=16f877a

#include


org 0x0000

RESET_V goto START ;Reset Vector

START clrf PORTB ;Clear PORTB output latchesbsf STATUS,RP0 ;Switch to bank 1movlw b11110000' ;Load value to make lower 4 bits outputsmovwf TRISB ;Move value to TRISBbcf STATUS,RP0 ;Switch to bank 0{1stInstruction} ;Clear index into table{2ndInstruction} ;Load W with high byte of TABLE address{3rdInstruction} ;Move W to PCLATH


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Lab 5: Solution Part 1Lab 5: Lookup Table

1234

56789101112131415161718

1920

LISTp=16f877a

#include


org 0x0000RESET_V goto START ;Reset Vector

START clrf PORTB ;Clear PORTB output latchesbsf STATUS,RP0 ;Switch to bank 1movlw b11110000' ;Load value to make lower 4 bits outputsmovwf TRISB ;Move value to TRISBbcf STATUS,RP0 ;Switch to bank 0clrf INDEX ;Clear index into table

movlw HIGHTABLE ;Load W with high byte of TABLE addressmovwf PCLATH ;Move W to PCLATH


Lab 5: Lookup Table

1234

56789101112131415161718

1920

LISTp=16f877a

#include


org 0x0000RESET_V goto START ;Reset Vector

START clrf PORTB ;Clear PORTB output latchesbsf STATUS,RP0 ;Switch to bank 1movlw b11110000' ;Load value to make lower 4 bits outputsmovwf TRISB ;Move value to TRISBbcf STATUS,RP0 ;Switch to bank 0clrf INDEX ;Clear index into table

movlw HIGHTABLE ;Load W with high byte of TABLE addressmovwf PCLATH ;Move W to PCLATH




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Lab 5: Results

You have learned:

How to implement a lookup table

How to retrieve data from a lookuptable

How to call a subroutine on anotherpage

How to perform a computed goto

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Summary

PIC16 Architecture

PIC16 Instruction Set PIC16 Memory Organization

Simple Programming Techniques


References

PICMCU Mid-Range FamilyReference Manual (DS33023A)Microchip Technology

Programming and Customizing

PICmicro Microcontrollersby Myke Predko

Design with PIC

Microcontrollersby John B. Peatman

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References

123 PICMicrocontrollerExperiments for the Evil Geniusby Myke Predko


Thank You

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC,KeeLoq, KeeLoq logo, microID, MPLAB, PIC, PICmicro, PICSTART,PRO MATE, rfPIC and SmartShunt are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV,MXLAB, SEEVAL, SmartSensor and The Embedded Control SolutionsCompany are registered trademarks of Microchip Technology Incorporatedin the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM,dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM,fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM,PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool,REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance,UNI/O, WiperLock and ZENA are trademarks of Microchip TechnologyIncorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respectivecompanies.

Documents

11002_GS2.pdf