Upload
siddhu-redz
View
216
Download
0
Embed Size (px)
Citation preview
8/2/2019 11 Peripheral(Step Motors)
1/50
1-1
Stepper Motors
more accurately controlled than a normal
motor allowing fractional turns or n
revolutions to be easily donelow speed, and lower torque than a
comparable D.C. motor
useful for precise positioning for roboticsServomotors require a position feedback
signal for control
8/2/2019 11 Peripheral(Step Motors)
2/50
1-2
Stepper Motor Diagram
8/2/2019 11 Peripheral(Step Motors)
3/50
1-3
Stepper Motor Step Angles
8/2/2019 11 Peripheral(Step Motors)
4/50
1-4
Terminology
Steps per second, RPM
SPS = (RPM * SPR) /60
Number of teeth
4-step, wave drive 4-step, 8-step
Motor speed (SPS)
Holding torque
8/2/2019 11 Peripheral(Step Motors)
5/50
1-5
Stepper Motor Types
Variable Reluctance
Permanent Magnet
8/2/2019 11 Peripheral(Step Motors)
6/50
1-6
Variable Reluctance Motors
8/2/2019 11 Peripheral(Step Motors)
7/50 1-7
Variable Reluctance Motors
This is usually a four wire motor thecommon wire goes to the +ve supply and thewindings are stepped through
Our example is a 30o motorThe rotor has 4 poles and the stator has 6
poles
Example
8/2/2019 11 Peripheral(Step Motors)
8/50 1-8
Variable Reluctance Motors
To rotate we excite the 3 windings insequenceW1 - 1001001001001001001001001
W2 - 0100100100100100100100100
W3 - 0010010010010010010010010
This gives two full revolutions
8/2/2019 11 Peripheral(Step Motors)
9/50 1-9
Unipolar Motors
8/2/2019 11 Peripheral(Step Motors)
10/50 1-10
Unipolar Motors
To rotate we excite the 2 windings insequenceW1a - 1000100010001000100010001
W1b - 0010001000100010001000100
W2a - 0100010001000100010001000
W2b - 0001000100010001000100010
This gives two full revolutions
8/2/2019 11 Peripheral(Step Motors)
11/50
8/2/2019 11 Peripheral(Step Motors)
12/50 1-12
Unipolar Motors
To rotate we excite the 2 windings insequenceW1a - 1100110011001100110011001
W1b - 0011001100110011001100110
W2a - 0110011001100110011001100
W2b - 1001100110011001100110011
This gives two full revolutions at 1.4 timesgreater torque but twice the power
8/2/2019 11 Peripheral(Step Motors)
13/50 1-13
Enhanced Waveforms
better torque
more precise control
8/2/2019 11 Peripheral(Step Motors)
14/50 1-14
Unipolar Motors
The two sequences are not the same, so bycombining the two you can produce halfstepping
W1a - 11000001110000011100000111W1b - 00011100000111000001110000
W2a - 01110000011100000111000001
W2b - 00000111000001110000011100
8/2/2019 11 Peripheral(Step Motors)
15/50 1-15
Motor Control Circuits
For low current options the ULN200xfamily of Darlington Arrays will drive thewindings direct.
8/2/2019 11 Peripheral(Step Motors)
16/50 1-16
Interfacing to Stepper Motors
8/2/2019 11 Peripheral(Step Motors)
17/50 1-17
Example
8/2/2019 11 Peripheral(Step Motors)
18/50 1-18
Digital to Analog Converter
8/2/2019 11 Peripheral(Step Motors)
19/50 1-19
Example Step Ramp
8/2/2019 11 Peripheral(Step Motors)
20/50 1-20
Analog to Digital
8/2/2019 11 Peripheral(Step Motors)
21/50
1-21
Vin Range
8/2/2019 11 Peripheral(Step Motors)
22/50
1-22
Timing
8/2/2019 11 Peripheral(Step Motors)
23/50
1-23
Interfacing ADC
8/2/2019 11 Peripheral(Step Motors)
24/50
1-24
Example
8/2/2019 11 Peripheral(Step Motors)
25/50
1-25
Temperature Sensor
8/2/2019 11 Peripheral(Step Motors)
26/50
1-26
Printer Connection
8/2/2019 11 Peripheral(Step Motors)
27/50
1-27
IO Base Address for LPT
8/2/2019 11 Peripheral(Step Motors)
28/50
1-28
Printers Ports
8/2/2019 11 Peripheral(Step Motors)
29/50
1-29
8255
8051 has limited number of I/O ports one solution is to add parallel
interface chip(s)
8255 is a Programmable PeripheralInterface PPI
Add it to 8051 to expand number ofparallel ports
8051 I/O port does not havehandshaking capability
8255 can add handshaking capabilityto 8051
8/2/2019 11 Peripheral(Step Motors)
30/50
1-30
8255Programmable Peripheral Interface (PPI)
Has 3 8_bit ports A, B and CPort C can be used as two 4 bit ports CL and Ch
Two address lines A0, A1 and a Chip select CS
8255 can be configured by writing a control-wordin CR register
8/2/2019 11 Peripheral(Step Motors)
31/50
1-31
8255 Control Word
8/2/2019 11 Peripheral(Step Motors)
32/50
1-32
8/2/2019 11 Peripheral(Step Motors)
33/50
1-33
8255 Operating Modes
Mode 0 : Simple I/O Any of A, B, CL and CH can be programmed as input or
output
Mode 1: I/O with Handshake A and B can be used for I/O C provides the handshake signals
Mode 2: Bi-directional with handshake A is bi-directional with C providing handshake signals
B is simple I/O (mode-0) or handshake I/O (mode-1) BSR (Bit Set Reset) Mode
Only C is available for bit mode access
Allows single bit manipulation for control applications
8/2/2019 11 Peripheral(Step Motors)
34/50
1-34
8255 Mode Definition Summary
8/2/2019 11 Peripheral(Step Motors)
35/50
1-35
Mode 0
Provides simple input and output operationsfor each of the three ports.No handshaking is required, data is simply
written to or read from a specified port.Two 8-bit ports and two 4-bit ports.
Any port can be input or output.
Outputs are latched.
Inputs are not latched
8/2/2019 11 Peripheral(Step Motors)
36/50
1-36
Mode 1
Mode 1 Basic functional Definitions:Two Groups (Group A and Group B).
Each group has one 8-bit data port and one 4-bitcontrol/data port.
The 8-bit data port can be either input or output.Both inputs and outputs are latched.
The 4-bit port is used for control and status ofthe 8-bit data port.
8/2/2019 11 Peripheral(Step Motors)
37/50
1-37
8255 mode 1 (output)
8/2/2019 11 Peripheral(Step Motors)
38/50
1-38
Mode 1 Control Signals
Output Control Signal DefinitionOBF (Output Buffer Full F/F). (C7 for A, C1 for B)
The OBF output will go low to indicate that the CPUhas written data out to the specified port. A signal to the device that there is data to be read.
ACK (Acknowledge Input). (C6 for A, C2 for B)A low on this input informs the 8255 that the data
from Port A or Port B has been accepted. A response from the peripheral device indicating that it
has read the data.
INTR (Interrupt Request). (C3 for A, C0 for B)A high on this output can be used to interrupt the
CPU when an output device has accepted datatransmitted by the CPU.
8/2/2019 11 Peripheral(Step Motors)
39/50
1-39
Timing diagram for mode1(output)
8/2/2019 11 Peripheral(Step Motors)
40/50
1-40
8255 mode 1 (input)
8/2/2019 11 Peripheral(Step Motors)
41/50
1-41
Mode 1 Control Signals
Input Control Signal Definition STB (Strobe Input). (C4 for A, C2 for B)
A low on this input loads data into the input latch.
IBF (Input Buffer Full F/F) (C5 for A, C1 for B)
A high on this output indicates that the data hasbeen loaded into the input latch; in essence, anacknowledgement from the 8255 to the device.
INTR (Interrupt Request) (C3 for A, C0 for B)
A high on this output can be used to interrupt the
CPU when an input device is requesting service.
8/2/2019 11 Peripheral(Step Motors)
42/50
1-42
Timing diagram for mode1(input)
8/2/2019 11 Peripheral(Step Motors)
43/50
1-43
Mode 2 - Strobed BidirectionalBus I/O
MODE 2 Basic Functional Definitions:Used in Group A only.
One 8-bit, bi-directional bus port (Port A) and a
5-bit control port (Port C).Both inputs and outputs are latched.
The 5-bit control port (Port C) is used forcontrol and status for the 8-bit, bi-directional
bus port (Port A).
8/2/2019 11 Peripheral(Step Motors)
44/50
1-44
Mode 2Output Operations
OBF (Output Buffer Full). The OBF outputwill go low to indicate that the CPU haswritten data out to port A.
ACK (Acknowledge). A low on this inputenables the tri-state output buffer ofPort A to send out the data. Otherwise,
the output buffer will be in the highimpedance state.
Input Operations STB (Strobe Input). A low on this input
loads data into the input latch. IBF (Input Buffer Full F/F). A high on this
output indicates that data has been loadedinto the input latch.
Pin Function
PC7 /OBF
PC6 /ACK
PC5 IBF
PC4 /STB
PC3 INTR
PC2 I/O
PC1 I/O
PC0 I/O
8/2/2019 11 Peripheral(Step Motors)
45/50
1-45
8/2/2019 11 Peripheral(Step Motors)
46/50
8/2/2019 11 Peripheral(Step Motors)
47/50
1-47
BSR Mode example
Move dptr, 0093h
Up: Move a, 09h ;set pc4
Movx @dptr,a
Acall delay
Mov a,08h ;clr pc4
Movx @dptr,a
Acall delaySjmp up
8/2/2019 11 Peripheral(Step Motors)
48/50
1-48
Interfacing 8255 with 8051 CS is used to interface 8255 with 8051
If CS is generated from lets say Address linesA15:A12 as follows,A15:A13 = 110
Address of 8255 is 110 xxxxx xxxx xx00b
Base address of 8255 is 1100 0000 0000 0000b=C000H
Address of the registers A = C000H B = C001H C = C002H CR = C003H
8/2/2019 11 Peripheral(Step Motors)
49/50
1-49
Interfacing 8255 with 8051
8255
8051
7413838 decoder
74373
P0.7-P0.0(AD7-AD0)
D7-D0
D7-D0
/CS
A0
A1O0
O1
O7
A2
A1
A0
P2.7(A15)
P2.6(A14)
P2.5(A13)
ALE
/RD
/WR
/RD
/WR
8/2/2019 11 Peripheral(Step Motors)
50/50
8255 Usage: Simple Example 8255 memory mapped to 8051 at address C000H base
A = C000H, B = C001H, C = C002H, CR = C003H
Control word for all ports as outputs in mode0 CR : 1000 0000b = 80H
test: mov A, #80H ; control word mov DPTR, #C003H; address of CR movx @DPTR, A ; write control word
mov A, #55h ; will try to write 55 and AA; alternatively
repeat:mov DPTR,#C000H ; address of PA movx @DPTR, A ; write 55H to PAinc DPTR ; now DPTR points to PB movx @DPTR, A ; write 55H to PB
inc DPTR ; now DPTR points to PC movx @DPTR, A ; write 55H to PCcpl A ; toggle A (55AA, AA55)acall MY_DELAY ; small delay subroutinesjmp repeat ; for (1)