A 4 bit 10GS/s Flash ADC frontend in SiGetechnology with very low power consumption

Philipp Ritter, Michael MollerChair of Electronics and Circuits

Saarland UniversityCampus, C6.3 OG 8

D-66123 Saarbrucken, GermanyPhone: (+49) 681 302 648 74

Email: p.ritter@eus.uni-saarland.de

AbstractThe work on hand demonstrates the feasibility ofhigh sampling frequency (10GS/s), high input bandwidth (5GHz)but yet low power consuming (50mW from -2.5V supply) flashADC frontend in SiGe bipolar technology. This is accomplishedby employing a differential emitter follower (EF) incorporating aresistor ladder (which supersedes a dedicated reference ladder)and by applying a new latch architecture with active load.

Index TermsFlash ADC, SiGe technology, latch with activeload, high speed, low power consumption.

I. I

INTEGRATED circuits realized in SiGe-bipolar technolo-gies have a reputation for operating at very high speed(e.g. 100Gbit/s [1]) but being very power consuming whereascircuits in the latest CMOS technologies are expected to op-erate at only somewhat lower speed (e.g. 60Gbit/s [2]) but toconsume significantly less power. The low power consumptionfor CMOS technologies is true as long as the circuits applya Complementary-MOS topology and the operation speed islow enough to benefit from the inherent negligible static powerconsumption.However, at medium speeds (e.g. 10Gbit/s) the

Complementary-MOS topology has a poor electricalperformance and, therefore, needs to be replaced by adifferentially operated symmetrical circuit topology like theCurrent Mode Logic (CML). Such a topology offers a vastvariety of advantages (e.g. virtual ground, TML matching, cellbased design, [1, 3]) if the design strictly obeys the complexconjugate impedance mismatch concept at interfaces betweenadjacent transistor stages. Optimizing such CML circuits forspeed requires improving the mismatch at the transistor stageinterfaces. Here, the bipolar transistor benefits from its wellknown inherent advantage owing to his comparatively hightransconductance (gm). On the other hand, if operation atmaximum speed is not required, the high speed potentialcan be traded for low power consumption. If this trade-off isapplied to a state-of-the-art SiGe bipolar technology ( fT, fmaxabout 200GHz), which can reach maximum operating speedsof about 100Gbit/s, high performing circuits with moderatespeed (e.g. 10Gbit/s) and very low power consumption canbe realized. This changes the paradigm of power consumingbipolar designs. The full low power potential of SiGe bipolar

d

i

g

i

t

a

l

p

a

r

tl

a

t

h

l

a

t

h

l

a

t

h

l

a

t

h

r

e

f

e

r

e

n

e

v

in

v

out;i

v^

out;i

quantizer sampler buer

b

r

a

n

h

e

s

2

b

1

Fig. 1. Block diagram of b = 4 bit flash ADC frontend. Examined in detailare the quantizer (Sec. II)- and sampler (Sec. III) block.

technology can be further exhausted if transistor models(e.g. HICUM) are used in circuit simulation that allow fortransistor optimization in the high current- and the VCEsaturation area.

The aforementioned low power potential is demonstrated bythe simulation results of the low power 4 bit 10GS/s flash ADCfrontend in pure SiGe bipolar technology shown in the blockdiagram in Fig. 1. The ADC frontend employs a differentialemitter follower (EF) stage followed by a resistor ladder whichdrives 15 comparator stages in parallel (quantizer block). Thisarchitecture, its advantages and performance limitations assignal delay along the ladder and load currents drawn from theladder are identified, detailed, and assessed in Sec. II. In orderto assess the performance of the latches (sampling block),new figures of merit are introduced and optimization-methodsare proposed. These figures of merit incorporate both the eyeopening and the polarity of the latch output signal. It is shownin Sec. III that the standard latch architecture comprisinga tracking current switch pair (CS) and a cross coupledlatching current switch pair mainly suffers from the RC timeconstant at the output node. The improvement with respectto the aforementioned figures of merit due to employing atransimpedance stage instead of the load resistors is presented.The simulation results of this ADC frontend are in Sec. IVcompared with measurement results of an ADC realized in astate-of-the-art CMOS technology. This paper closes with theconclusion in Sec. V.

Vref

omparators

signal

buer

1

st

ref.

(2

b

1)

th

ref.

V

EE

V

EE

v

in

v

ref

v

out

ba

I

01

I

02

R

E

R

E

Fig. 2. a) Typical single ended b bit flash ADC topology with resistor ladderand signal buffer. b) Differential comparator consisting of two (linear) currentswitches with differential input voltage vin and differential reference voltagevref.

II. L

A. Ordinary flash architecture

In typical (single ended) ADC flash topologies [4] followingthe principle shown in Fig. 2.a), each comparator is fed by adedicated reference signal and a data signal common to allcomparators. The buffer employed here distributes the datasignal to all comparators and decouples their inputs from thesignal source output. The reference voltage levels can forexample be generated by a resistor ladder. This topology hasthe inherent disadvantage of requiring currents to generate thereference levels in the resistor ladder and currents for the inputsignal buffer(s). Moreover, if the ADC shall convert differentialsignals, not only the reference- and buffer currents doublebut also comparators have to consist of at least two currentswitches (one for the data signal, one for the reference level,see Fig. 2.b). The output currents of these current switches(CS) sum in the common collector branches and thus generatea differential output current. This differential output currentmust have the same sign as the difference vsigvref of the signalvoltage vsig and the reference voltage vref in order to cause avoltage drop at a load (not shown in Fig. 2.b) representing thecomparator decision. The output currents of both CS thereforehave to linearly depend on their respective input voltage, whichis accomplished by adjusting their linear range large enoughto cover the entire input voltage dynamic range. The linearrange of a CS is bounded by the knee voltage [5]

VK = I0 (RE + rE + rB/0) + 2VT , (1)where RE is the emitter degeneration resistance, rE is theemitter contact resistance, rB is the base resistance, 0 isthe DC current gain and VT is the temperature voltage ofone transistor of the CS; I0 is the tail current of the CS.For input voltages vin above that threshold, the linearizedtransfer curve iout(vin) reaches saturation of the output currentiout = I0. From (1) it becomes obvious that a large dynamicrange demands for high comparator tail currents I01, I02 asthe emitter degeneration resistance RE is limited by layoutcapacitances. As this increases the power consumption of theADC frontend significantly (2b1 comparators), a more powersaving architecture is proposed in the following section.

V

EE

R

R

R

R

R

R

R

R

I I

v

in

v

out;1

v

out;B

v^

out;1

v^

out;B

Fig. 3. Enhanced b bit quantizer which simultaneously buffers the inputsignal, performs the comparison with B = 2b1 reference levels and distributesthe result of the comparison to succeeding stages (e.g. latches).

B. Transfer characteristics of enhanced quantizer

In the enhanced architecture of Fig. 3, the differential outputvoltage vout,i at each tap of the ladder represents already theresult of the comparison of the input voltage vin with the ith

reference level:

vout,i = vin (i 2b1) VLSB , (2)where VLSB = 2RI is the quantization step size given by thetap resistance R and the EF tail current I. Therefore, the com-parators shown in Fig. 3 consist of ordinary current switches(CS) without requirement for linearity instead. Moreover, theemitter followers decouple and distribute the signal from thesource to all comparators, which supersedes a dedicated bufferstage.Because of capacitive loading C of the taps (resistor capac-

itance, input capacitance of comparators, layout capacitancesof interconnects thereof), signals are delayed along the resistorladder. As the signal and the complementary signal passthrough different counts of RC lowpasses in that particularladder architecture, they exhibit different phase shifts and arenot opposite in phase. Hence, the differential amplitude of tapvoltages vout,i is decreased with respect to the input voltage vin.In order to estimate the influence thereof, an ideal AD-DAconversion simulation environment which takes propagationdelays in the reference ladder into account is set up in thefollowing. In step 1 the signal propagation delays themselvesare determined and used to compute the respective tap volt-ages. In step 2, the behavior of the comparators of Fig. 3 ismodeled. In step 3, the thermometer code constituted by thecomparator output voltages vout,i is ideally DA converted. Instep 4, commonly used performance metrics such as ENOB,THD, SFDR etc. are computed in order to assess the influenceof propagation delay in the reference ladder.1) Each emitter follower with resistor ladder is modeled by

a chain of RC elements as shown in Fig. 4 (single endedvoltages are marked with an apostrophe ). The input EF

V0

out;1

V

0

out;B

tap

1

tap

B

open

V

in

'

R

C C

R

EF

V

0

in

Fig. 4. Ideal voltage buffer and chain of B RC lowpasses as a simple modelof input emitter follower (EF) with resistor ladder.

is modeled as an ideal unity voltage gain buffer, the EFbias current source I is considered as open circuit forsignal frequencies. The input impedance of any tap isdominated by the capacitance as | j2pi fC|1 300R atf = 5GHz, C = 20 fF, and R = 5. Therefore, the ith

tap is a lowpass with capacitance (B (i 1))C, whereB = 2b 1 is the number of reference levels (taps),i.e. all taps to the right hand side of tap i are reducedto their capacitance. The voltage transfer function Hi =V out,iV in

from the input to the ith tap is then given by theproduct of transfer functions of each of the first i taps:

Hi B(i1)k=B

11 + j2pi f (kC)R

. (3)

(3) can be simplified further by neglecting all addendscontaining higher order powers of 2pi fCR 0.003. Itfollows

Hi 1

1 + j2pii(B i12

)CR

. (4)

The signal propagation delay between the input of theEF and the ith tap is then for monofrequent signals givenby the phase arc(Hi). For a sinusoidal input voltage v

in =

A2 sin

(2pi fsigt

)of amplitude A/2 and frequency fsig, the

ith tap voltage results in

vout,i =Hi( fsig) A2 sin (2pi fsigt arc(Hi)) . (5)

As this testbench shall only reveal performance degra-dation due to delays, the amplitude attenuation

Hi isomitted here:

vout,i =A2sin

(2pi fsigt arc(Hi)

). (6)

The ith differential tap voltage then results (cf. (2) andFig. 3) as the difference of the ith tap in the positive EFbranch and the (B (i 1))th tap of the complementaryEF branch in

vout,i =A2

[sin

(2pi fsigt arc(Hi)

)+ sin

(2pi fsigt arc(HB(i1))

)](i 2b1) VLSB . (7)

2) The resistor ladder output voltages vout,i of (7) carrythe result of the comparison of the input signal withthe respective reference level in their signs (see (2)).

0 100 200 300 400 500

3.0

3.2

3.4

3.6

3.8

4.0

-0.2 ENOB

100 fs

ENOB

RC=f s

Fig. 5. ENOB degradation (solely) due to propagation delay in the quantizerin dependence of tap time constant RC.

Ideal comparators evaluate the sign and set their outputvoltages

vout,i B sgn(vout,i

)(8)

to 1 or -1 in dependence of the signs of their inputvoltages.

3) Ideal thermometer code (vout,i of (8), where i {1 . . . B})to analog conversion.

4) Computation of performance metrics of the analog sig-nal obtained in the previous step. Fig. 5 shows thedecrease in Effective Number Of Bits (ENOBs) independence of the RC time constant of one single tap. Asthe total capacitance (resistors, input cap. of comparatorwith Miller Effect, interconnects) of one tap is aboutC = 20 fF, the designer can expect a decrease of 0.2 ENOB if R = 5, a decrease of 0.4 ENOBif R = 10, and so onsolely due to the differentpropagation delays in both EF branches.

The tap resistance R is not only limited by the delay in thereference ladder but also by the load currents drawn from thecomparators. Each current into a comparator connected to tapi causes a voltage drop at all taps above the ith. If the inputsignal amplitude is half an LSB below positive fullscale, thebottommost (Bth) comparator has an input voltage of vout,B =12VLSB (cf. (2)). All comparators at taps i < B also have apositive input voltage, and base currents iB,i,p of the CS in thecomparators are drawn from the positive EF branch of resistorladder; the base currents iB,i,n drawn from the complementaryEF branch can be neglected if the CS in the comparator istoggled completely (saturated). If the positive base currentsiB,i,p = IL are considered equal and constant, the distortion Vat the input of the Bth comparator is given by

V = B ILR + + 1 ILR !< 12VLSB (9)and must not exceed half the quantization step size VLSB inorder not to alter the polarity of the bottommost comparator.(9) can be rearranged to

R