10Gbps Active Optical Cable - Samtec Microelectronicscloud.samtec.com/ebrochures/TNB-Series-Users-Manual.pdf · TNB Series Ceramic Miniature Optical Engine 4 Product Features 4 Applications

User Manual

March 2012 Covering: TNB Series

Product Specification

AIO-TNB40G – Datasheet – Rev. 006, March, 2012 Page 1 of 31

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TABLE OF CONTENTS

INTRODUCTION

TNB Series Ceramic Miniature Optical Engine 4

Product Features 4

Applications 5

FUNCTIONAL DESCRIPTION

Ceramic Miniature Optical Engine 7

Transmitter Block 7

Receiver Block 8

Control Interface 8

SPECIFICATIONS

Characteristics

Electrical 9

Optical 10

Interfaces

Control Interface 11

Transmitter/Receiver Digital Interface 11

EEPROM Digital Interface

INITIALIZATION PROCEDURE

Memory Map

EEPROM 15

Transmitter 17

Receiver Register Map 18

Control, Status, and Monitor 20

Initialization

Firmware 21

Electrical Interface 23

FIBER CONNECTORS

MT Ferrule 25

MTP Connector 25



MECHANICAL CHARACTERISTICS

Package Outline 26

Interposer Mechanical Outline 27

Host Board Mechanical Footprint 28

Host Board Layout Example 28

Compression Hardware 29

TECHNICAL INFORMATION

Regulatory and Compliance 30

TNB Series Ceramic Miniature Optical Engine Part Number 30

Definitions 31

Application Support 31



INTRODUCTION

TNB Series Ceramic Miniature Optical Engine

Samtec’s TNB Series is a highly integrated 4 channel, surface mount optical transceiver that provides increased port density and total cost savings for high bandwidth system I/O. This full-duplex optical module offers 4 independent transmit and receive channels, each capable of 10 Gbps for an aggregate bandwidth of 40 Gbps. The module is designed to operate with multimode fiber systems using a nominal wavelength of 850nm. The optical interface uses an MTP® (MPO) 1x12 fibers connector. The transceiver mounts directly to an LGA interposer interfacing with the host board, which can be placed very close to the switch fabric or I/O ASIC. This proximity eliminates the need to drive long, lossy copper traces and unnecessary costly, power hungry buffer chips. The module incorporates high performance, highly reliable, short wavelength optical devices coupled with proven circuit technology to provide long life and consistent service.

Figure 1: Ceramic Miniature Optical Engine

Product Features

4 high-speed channels full duplex transceiver

Multi-rate: 1 – 10.5 Gbps per channel

1 optional sideband transmit and receive channel

Bit Error Rate better than 10-12

SFI and PPI electrical interface compliant

LGA electrical interface (1mm pitch)

Links up to 100m at 10Gbps with OM3 fibers

10G-BASE-SR interoperable

Standard MTP® connector interface

0 to 70C package temperature operating range

Proven high reliability 850nm VCSEL technology

Serial digital control interface



Applications

Computer Interconnects

Optical Backplanes

High Density Switches and Routers

Can be used for most protocols: - Infiniband - Ethernet - Fiber Channel - SAS/SATA - PCIe - Hyper Transport…

A typical schematic example is given in Figure 2 for reference. Note that this particular schematic is for a PCIe application and includes EXB24AT attenuators in each data line to emulate termination required by the PCIe standard. These are not necessary in most applications.



Figure 2: Host Board Schematic Example

TNB O



FUNCTIONAL DESCRIPTION

Ceramic Miniature Optical Engine

The surface mount transceiver includes 4 independent transmit, 4 independent receiver channels, and an EEPROM used to store calibration values. The transmitter section consists of a 4-channel VCSEL (Vertical Cavity Surface Emitting Laser) array, a 4-channel input buffer and laser driver. The receiver section consists of a 4-channel PIN photodiode array, a 4-channel TIA array, and a 4-channel output buffer. Each transmit and receive sections use a SPI bus to control, monitor and diagnose the different channels. The EEPROM is accessible via the same SPI bus. A functional block diagram of the transceiver is shown in Figure 3.

Figure 3: Transceiver Functional Block Diagram

When integrated in a host system, the transceiver must be connected to a microcontroller via the SPI bus/interface. During system initialization, it is the host microcontroller responsibility to read the calibration data from the transceiver EEPROM, then load the values into the transmitter and receiver chips (see the chapter 0 for more details). This necessary initialization operation has to be repeated for each transceiver if there are several of them on board.

Transmitter Block

The optical transmitter section of the Ceramic Miniature Optical Engine incorporates a 4-channel VCSEL (Vertical Cavity Surface Emitting Laser) array, a 4-channel input buffer and laser driver, diagnostic monitors and control interface. The transmitter input buffer provides CML compatible differential inputs presenting a nominal differential input impedance of 100 Ohms. AC coupling capacitors are required on the host board. A serial digital control interface is used to control and monitor the laser drivers, and also provides access to an EEPROM where the transmitter calibration values are stored. A transmitter interrupt signal is generated to inform the host when a fault condition occurs. All register flags are

Driver

TIA

EEPROM

MT

SPI bus

Tx Data

Rx Data

LGA electrical interface

MT or MPO optical interface

INT_Tx

INT_Rx



latched and remain set even if the condition initiating the latch clears and operation resumes. The interrupt can be masked and flags are reset by reading the appropriate flag register. Fault detection or channel de-activation through the serial digital interface will disable the channel. Fault information is available via the serial digital interface.

Receiver Block

The optical receiver section of the Ceramic Miniature Optical Engine incorporates a 4-channel PIN photodiode array, a 4-channel TIA array, a 4 channel output buffer, diagnostic monitors and a control interface. The Rx Output Buffer provides CML compatible differential outputs for the high speed electrical interface presenting nominal single-ended output impedances of 50 Ohms to AC ground and 100 Ohms differentially that should be differentially terminated with 100 Ohms. AC coupling capacitors are required on the host board. A serial digital control interface is used to control and monitor the TIA, and also provides access to an EEPROM where the receiver calibration values are stored. Flags are set and an interrupt is generated for loss of optical input signal (LOS). All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset upon reading the appropriate flag register. The electrical output will squelch when loss of input signal occurs, or when channel de-activation is selected through the serial digital interface. Status and alarm information are available via the serial digital interface. To reduce the need for polling, an interrupt signal is automatically generated to inform hosts of an alarm and/or LOS condition.

Control Interface

The transceiver uses a digital control interface to control, monitor and diagnose the transmitters, receivers and EEPROM sections on the module. The digital interface is based on a serial SPI-like communication link, in a star configuration where the transmitter, receiver and EEPROM are slave devices. The basic transceiver control functions are:

Enable/Disable individual channels

Read transmitter and receiver calibration of the EEPROM

Load transmitter and receiver calibration values to the laser driver (transmitter) and TIA (receiver) chips

Also, the transceiver will generate Interrupt signals, by asserting the INT_TX or INT_RX signal line, when an operational fault occurs. The host can then identify the source of the interrupt by reading the appropriate registers through the SPI digital interface. The following Interrupt Flags are provided:

Rx LOS – receiver loss of signal, provided for each channel.

Tx Fault – provided for each channel. This indicates a VCSEL open or short circuit.

Transceiver Temperature High and Low Alarm, and High and Low warning.

Transceiver supply voltage High and Low alarm, and High and Low warning.



SPECIFICATIONS

Characteristics

Electrical Characterization

Table 1: Absolute Maximum Rating

Specifications Symbol Unit Min Typ Max Notes

Storage Temperature range Tsto ºC -40 85

Powered case temperature Tcase ºC 0 70 Heat sink temperature

Operating Humidity RH % 5 90 Non-condensing

Supply voltage range VCC1 V -0.5 4.0

Any stress beyond the maximum rating may result in permanent damage to the device. Specifications are guaranteed only under recommended operating conditions.

Table 2: Recommended Operating Conditions


Operating case temperature Tcase ºC 0 70 Heat sink temperature

Power supply voltage VCC1 V 3.1 3.3 3.5

DC common mode voltage VCM V 0 3.6

Data rate Gbps 1 10.5

Table 3: Power Supply Requirements


Power supply voltage VCC1 V 3.15 3.3 3.45

Power supply current ICC1 mA 300

Power consumption W 0.8 1.0

Table 4: Low Speed Electrical Interface


Digital input logic high VDI_H V 2.0 Vcc SS_Xx, SCK, MOSI, WP_ROM

Digital input logic low VDI_L V 1.0 SS_Xx, SCK, MOSI, WP_ROM

Digital input current ID mA 0.0

Digital output logic high VDO_H V 2.0 Vcc INT_X, MISO

Digital output logic low VDO_L V 1.0 INT_X, MISO

Digital output current ID mA 8 INT_X, MISO



Table 5: Transmitter Electrical Input


Input AC Common mode voltage mV 15 RMS

Differential input amplitude VDI mV 300 1200 Peak to peak diff.

Differential input S parameter SDD11 dB SFP+ MSA compliant

Differential to common mode conversion

SCD11 dB -10 0.1 – 11.1GHz

Jitter and eye mask tolerance SFP+ MSA compliant

Table 6: Receiver Electrical Output


Output AC Common Mode Voltage mV 7.5 RMS

Differential Output Amplitude VDO mV 340 700 Peak to peak diff.

Differential Output Amplitude in squelched state

mV 50 Peak to peak diff.

Output rise/fall times (20-80%) tRH , tFH ps 34

Differential output return loss SDD22 dB SFP+ MSA compliant

Common mode output return loss SCC22 dB SFP+ MSA compliant

Skew between channels ns 5

Jitter and eye mask tolerance SFP+ MSA compliant

Optical Characterization

The transceiver is designed to interoperate with 10GBASE-SR (10 Gb Ethernet) parts with up to 100 meters of OM3, 2000 MHz·km fiber. The transceiver meets the dispersion and stress requirements of the 10GBASE-SR specification; however, the guaranteed interoperable link distance is limited to 100 meters.

Table 7: Transmitter Optical Output


Average Optical Output PAVG dBm 1.0 Up for discussion – class 1M?

Extinction Ratio ER dB 3

Center Wavelength λC nm 840 860

Spectral Width Δλ 0.65

RIN RIN dB/Hz -128



Table 8: Receiver Optical Input


Maximum Input Power PMAX dBm 1.0

Receiver Sensitivity PIN(OMA) dBm -11.1

Stressed Receiver Sensitivity

PIN(OMA) dBm -6.5 VECP = 1.93dB

LOS Asserted Threshold – OMA

PAV_AS dBm -26

SLOS De-asserted - OMA POMA_DEAS dBm -13

Interfaces

Control Interface

The transceiver digital interface consists of a four-wire connection that is compatible with a standard SPI bus. The four wires are: clock (SCK or CLK), data out (MOSI or D_Out), data in (MISO or D_In) and Chip Select (SS_X or STB) as seen in Figure 4. The EEPROM serial interface uses the standard SPI - Mode 0. The clock polarity is idle low (CPOL = 0) and data is sampled on the leading edge (CPHA = 0). The digital interface of the Transmitter and Receiver analog ICs are compatible with SPI, but incorporate an additional extension that ensures data integrity before committing the data to the internal shift registers. All three can safely share SCK, MOSI, and MISO signals with other standard SPI devices.

Figure 4: Functional Block Diagram of the Control Interface

Transmitter/Receiver Digital Interface

Please refer to Figure 7 for timing diagrams. Digital transactions to the Transmitter or Receiver can either be a standard 160 bits read/write to the entire Shift Register, or a short 8 bit transaction to read the status bits only. The type of transaction depends on the polarity of the SCK line when the SS_X is asserted. Data is clocked into the Shift Register on the rising edge of SCK and is clocked out of the Shift



Register on the falling edge of SCK as seen in Figure 7. This means that the host should sample MISO on the rising edge of SCK and expect the Shift Register to sample MOSI on the falling edge of SCK. The least significant bit is always transmitted first. In order to complete a 160 bit transaction the SS_X line must be deasserted while the SCK line is high. If the SS_X is not properly deasserted the IO registers will not be committed to the internal registers and the operation will be ignored. If the byte sequence is valid and the SS_X is properly deasserted, the IO registers will be committed to the internal registers. Upon power-up of the IC, the shift registers default to their Power On Reset (POR) values. The shift register is segmented such that byte 0 contains read only status information, the next segment contains global controls, and finally individual channel controls. Byte 0 is defined as the first 8 bits clocked in/out of the Shift Register.

Figure 5: SPI Slave Principle of Operation

Standard mode (160-bit) The “standard” mode is selected by a falling edge on SS while SCK is low. In the standard mode, all 160 bits of the IO shift register are active (IOR [159:0]) – refer to Figure 5. In standard mode, the falling SS line triggers the first update of the MISO line. As long as the master samples the first bit after the rising edge of the subsequent clock, the first bit is read in the same way as all of the other bits. Note that because the polarity of the SCK line during SS_X transitions is critical, 162 clock pulses are required to read 160 bits of data in and out of the register as shown in Error! Reference source not found.. i.e. in the daisy-chain configuration, 1+n×160 falling edges on SCK are required to read and write all bits. The extra clock pulses frame the transaction with start and stop commands to guarantee the integrity of the transaction.



Reading and Writing The Transmitter/Receiver digital interface operates in full duplex mode. Reading and writing the SPI slave registers happens simultaneously. During a read/write session the serial clock SCK will shift the content of the SPI slave IO register so that the value in byte #0, bit #0 is moved to the MISO output, bit #1 is moved to bit #0 etc., and the value at the MOSI input is moved to byte #19, bit #7 as shown in Figure 6.

Figure 6: Memory Registers

The 160 bit standard transaction is a full duplex read/write operation. The 8 bit transaction is a read only operation. This implies that a read only operation of bytes 1- 19 is not supported. In order to read/write any of these registers you must read/write them all. Random or partial register read/writes are not supported. Byte 19 in the register map is the data align byte used to validate the transaction. Having too few clock edges in a transaction will (most likely) result in an invalid byte sequence due to an alignment error (see below). Delayed writing In some cases, the controller will need to process the readout before writing new values. To allow time for the controller to do this, two schemes are possible: 1) stop generating clock edges on SCK while keeping the device(s) selected (SS=0), or 2) maintain a constant clock frequency, but remembering that only the final 160 bits are actually written to the devices (n times 160 in the case of daisy-chaining). Additional bits between the readout and write are dummies, which are discarded (shifted through the SPI slave registers and back to the controller without ever being latched to the internal registers or the slave).

Alignment check Byte 19 of all 160 bit read/write transactions is the align byte used to validate the data sequence. The align byte must be equal to 8Eh (142 decimal). An alignment error causes the SPI slaves to ignore the written data, flag all fault/squelch bits and disable all channels. This feature is implemented to avoid unwanted settings in the event of a system error causing extra or missed clock edges during a read/write-session. Standard read/write abort The alignment check feature described above can be used to deliberately abort a long standard read/write session and immediately shut down the device. This requires that byte #19 is different from 8Eh. In order to ensure that byte #19 is not accidentally equal to 8Eh (due to a similar bit pattern elsewhere in the string), abort should only occur after n´ 160 + 1 bits. There is a minimum requirement of 6 negative clock edges within every read/write session. This requirement must be observed, even when aborting the session. Aborting a standard read/write session will cause all channels to be disabled (EN=0).



8 bit read transaction If only a read of the fault/status information is required, the 8 bit read transaction is sufficient. In order to start the 8 bit read transaction, the SS must be asserted during the transaction start clock pulse while the SCK line is high as shown in Figure 7. There is no aligning byte required.

Figure 7: Transmitter/Receiver Digital Interface Timing and Protocol



EEPROM Digital Interface

The EEPROM digital interface is a standard SPI bus in Mode 0. This means that the clock polarity is idle low (CPOL = 0) and the data is sampled on the leading edge of the clock (CPHA = 0). The EEPROM always operates as an SPI slave device. The EEPROM also features a Write Protect line (WP) that is active low. When the WP line is low, the EEPROM data is protected. In order to write data to the WP pin must be high. Each transaction with the EEPROM starts by writing an 8 bit opcode. The READ opcode is 0x03. All EEPROM read transactions must begin by issuing the READ opcode.

Reading EEPROM data:

1. Master asserts SS line. 2. Master transmits 8 bits of READ opcode (0x03) MSB first on the MOSI line. MISO can be

ignored. 3. Master transmits 8 bits of data address MSB first on the MOSI line. MISO is ignored. 4. Master clocks in n data bytes MSB first on the MISO line. The EEPROM will ignore MOSI. 5. Master de-asserts the SS line.

Figure 8: EEPROM Digital Interface Timing and Protocol

INITIALIZATION PROCEDURES

Memory Map

EEPROM

The memory map of the EEPROM is shown in Table 9. Of importance to the end user are the Receiver Register Map Initialization Image (RX_MAP, 160 bits) and Transmitter Register Map Initialization Image (TX_MAP, 160 bits) blocks. These two 160 bit blocks should be read from the EEPROM and written in their entirety into the Transmitter and Receiver registers at power up. This is easily accomplished using standard 160 bit read and write transactions described in chapter 0. Pseudo code for this initialization operation is provided in chapter 0.



Table 9: EEPROM Memory Map

Byte 7 6 5 4 3 2 1 0 ASCII

0

1 Memory Map Configuration

2

3-8 Vendor Name

9

10-16 Memory Map Document Number

17

18-20 Memory Map Document Revision Level

21

s22-28 Transceiver Part Number

29

30-32 Transceiver Revision Level

33

34-43 Transceiver Serial Number

44

45-52 Manufacturing Date Code (ASCII)

53

54-59 Manufacturing Time Code (ASCII)

60

61 Transceiver Configuration

70

71 Production Level

72

73-92 Receiver Register Map Initialization Image (RX_MAP)

93 `

94-113 Transmitter Register Map Initialization Image (TX_MAP)

114-253

254 CRC-16

255 CRC-16

These two data blocks contain the parameters needed for correct operation of the transmitter and receiver. For example, they contain parameters such as laser bias current, modulation amplitude, thermal control, etc… Parameter values are calibrated and loaded in the EEPROM at the factory. Users do not need to be concerned by the values, and they should never modify them. However, the data blocks need to be read from the EEPROM and loaded without modification into the receiver and transmitter chip at each power up. Failure to do so will result in the transceiver chips loading inadequate default values and a non-functioning transceiver.



Transmitter

The Transmitter Register Map is shown in Table 10. To set the PMD parameters to their correct initial values, the entire 160 bit register map needs to be overwritten at initialization by the image stored in the EEPROM Transmitter Register Map Initialization Image (see Table 9), including overwriting the first user accessible bytes.

After this operation, the user should not modify the PMD parameters, and should only access the user accessible fields documented in Table 11.

Table 10: Transmitter Register Map

Byte 7 6 5 4 3 2 1 0

0 FLT4 FLT3 FLT2 FLT1

1 FE3 FE2 FE1 FE0 EN3 EN2 EN1 EN0

2

PMD PAREMETERS

(To be loaded at initialization from EEPROM image)

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19 ALGN



Table 11: User Accessible Transmitters Register Fields

Symbol Characteristic Type Default

ENx Enable channel no. x. ENx=0 turns the data channel off (no laser light). Cleared on fault if FEx=1.

1 bit RAM 1

FLTx

Fault condition for channel no. x. Cleared after fault readout.

00: VCSEL OK

01: VCSEL shorted

10: VCSEL open

11:Refer to ALGN

2 bit ROM 00

FEx Fault detect enable for channel no. x. Cleared on fault

1bit RAM 0

ALGN

Alignment check byte. Must be 8E hex. All other values will be interpreted as alignment errors due to too many or too few failing edges on SCK during the

preceding read/write session. ALGN≠8Eh will cause write operation to be disregarded, INT=1, and al channels to be shut down (ENx=0).

RAM 8E hex

Receiver Register Map

The Receiver Register Map is shown in Table 12. To set the PMD parameters to their correct initial values, the entire 160 bit register map needs to be overwritten at initialization by the image stored in the EEPROM Receiver Register Map Initialization Image, including overwriting the first user accessible bytes. After this operation, the user should not modify the PMD parameters, and should only access the user accessible fields documented in Table 13.



Table 12: Receiver Register Map

Byte 7 6 5 4 3 2 1 0

0 AE SQ4 SQ3 SQ2 SQ1

1 unused

2 NE0 NE1 NE2 NE3

SC4 SC3 SC2 SC1

3

PMD PAREMETERS

(To be loaded at initialization from EEPROM image)

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19 ALGN

Table 13: Receiver Memory Registers Definition

Symbol Characteristic Type Default

NEx Disable receiver no. x. NEx= 1 turns the data channel off, and the output will be decided by SCx.

RAM 0

SCx

Slow Clock select. Determines the channel output in case of channel disable (NEx=1) or squelch. SCx=1 causes the output to be slow (MHz) clock pulses. SCx=0 causes the output to be constant logic “1”

RAM 0

SQx Squelch history for amplifier x (1 = input below threshold at some point in time since the last SPI access.). Cleared on positive edge of SS.

ROM 0

AE

Alignment error. Indicates alignment error on previous SPI access. Cleared on positive edge of SS at the end of the subsequent SPI session. See also ALGN.

ROM 0

ALGN

Alignment check byte. Must be 8E hex. All other values will be interpreted as alignment errors due to too many or too few failing edges on SCK during the preceding read/write session. ALGN≠8Eh will cause write operation to be disregarded, INT=1, and al channels to be shut down (ENx=0).

RAM 8E hex

Unused Unused/test. Factory use only. Leave at 0. Unused 0



Control, Status and Monitor Interface

The following tables provide the specifications of the control, status and monitoring interface.

Table 14: I/O Timing for Control, Status and Monitoring


Management interface clock frequency

fSCK MHz 0.4 25

Management interface clock duty cycle

DSCK % 45 55

Management interface input rise/fall time (threshold to threshold)

tRF,DI ns 12.5

Management interface input hold time (negative clock edge to data)

tH,DI ns 12.5

Management interface input setup time (data to negative clock edge)

tS,DI ns 6.25

Management input setup time (SCK to SS)

tS,SS ns 6.25

Management interface input hold time (SS to SCK)

tH,SS ns 12.5

Management output clock falling edge to data delay

tclkd ns 0 25.0 Cload <10pF

Management interface data output rise/fall time

tRF,DO ns 5 MISO, 20-80%, Cload <10pF

Fault detect to interrupt assertion delay

tINT ns 10 Cload <10pF

Table 15: I/O Timing for Squelch and Disable


Rx squelch assert time tON_RXSQ us 80 Time from loss of Rx input signal until the squelched output condition is reached.

Rx squelch de-assert time tOFF_RXSQ us 80 Time from resumption of Rx input signals until normal Rx output condition is reached.

Rx output disable assert time

tON_RXDIS ms 100 Time from Rx Output Disable bit set (value = 1b)1 until Rx output falls below 10% of nominal

Rx output disable de-assert time

tOFF_RXDIS ms 100

Time from Rx Output Disable bit cleared (value= 0b)1 until Rx output rises above 90% of nominal

Note 1. Measured from falling clock edge after stop bit of write transaction.



Initialization

Firmware

The transceiver (TNB) will not operate unless properly initialized by firmware. During regular operation, firmware can also monitor the TNB. The following details the necessary firmware actions.

Initialization Initializing the TNB consists in two steps. The first is to read the calibration values from the TNB internal EEPROM into memory. The second step is to write these values to the Tx and Rx PMD (Physical Media Device) driver chips on the TNB.

Reading the EEPROM The internal EEPROM is accessible through a standard SPI digital interface. The EEPROM operates in SPI mode 0, meaning clock polarity CPOL=0 and clock phase CPHA=0. In other words the clock idles at low and the data samples on the clock leading edge. The EEPROM has a chip select line that must be pulled low to initiate communication and released when the exchange is complete.

The following pseudocode reads 20 bytes from the Rx calibration map into rx_buffer and 20 bytes from the Tx calibration map into tx_buffer.

ALLOCATE_RX_MEMORY // 20 bytes

ALLOCATE_TX_MEMORY //20 bytes

EEPROM_CHIP_SELECT_LOW

SET count = 20

//The first two bytes of the exchange are the command code and the data address.

//The values read back may be safely ignored.

SPI_EXCHANGE_BYTE (out_byte=0x03)


WHILE count > 0:

//input byte is a “don’t care” byte. Store output byte to the rx buffer.

SPI_EXCHANGE_BYTE (out_byte=0x00, in_byte->rx_buffer)

SET count = count -1

EEPROM_CHIP_SELECT_HIGH

//now read the tx calibration map into tx_buffer

EEPROM_CHIP_SELECT_LOW

SET count=20

//The first two bytes of the exchange are the command code and the data address.

//The values read back may be safely ignored.


SPI_EXCHANGE_BYTE (out_byte=0x5E)

WHILE count > 0:

//input byte is a “don’t care” byte. Store output byte to the rx buffer.

SPI_EXCHANGE_BYTE (out_byte=0x00, in_byte->tx_buffer)

SET count = count -1

EEPROM_CHIP_SELECT_HIGH

The Rx calibration values will now be stored in rx_buffer and the Tx calibration values will be stored in rx_buffer.



Writing to the transmitter and receiver chips The PMD Tx and Rx chips have identical digital interfaces. The only difference is the physical slave select lines are different. The following pseudocode assumes that you are writing 20 bytes in write_buffer to the PMD and reading back 20 bytes into read_buffer.

//write the digital interface start

PMD_SCLK_HIGH

PMD_SCLK_LOW

// Chip select falls while SCLK is high. Tx/Rx slave select, depending on which

chip is being written.

PMD_SLAVE_SELECT_LOW //line will be different for tx/rx

// Shift each byte out and sample each incoming byte.

SET byte_index = 0

SET bit_index = 0

WHILE byte_index < 20:

read_buffer[byte_index] = 0;

// Least significant bit is expected first.

WHILE bit_index < 8:

SET bit_value = 1 << bit_index;

// Test MISO pin.

IF MISO_PIN_HIGH THEN

read_buffer[byte_index] |= bit_value;

PMD_SCLK_HIGH

// Update MOSI.

IF write_buffer[byte_index] & bit_value > 0 THEN

PMD_MOSI_HIGH

ELSE

PMD_MOSI_LOW

PMD_SCLK_LOW();

SET bit_index = bit_index + 1

SET byte_index = byte_index + 1

//write the digital interface stop

PMD_MOSI_LOW

PMD_SCLK_HIGH

PMD_SLAVE_SELECT_HIGH //line will be different for tx/rx

PMD_SCLK_LOW

The transceiver is now setup for regular operation.



Reading PMD Status After initialization, only one byte of data is necessary to be read or written to read or change the status of the transceiver. Reading the PMD status is similar to the write, but the start procedure is slightly different and only one byte is read from the chip. The following procedure illustrates a read of the status information.

PMD_SCLK_HIGH

//For status read, slave select falls while the clock is high.

PMD_SLAVE_SELECT_LOW //line will be different for tx/rx

PMD_SCLK_LOW

// Least significant bit is expected first.

WHILE bit_index < 8:

SET bit_value = 1 << bit_index;

// Test MISO pin.

IF MISO_PIN_HIGH THEN

pmd_status|= bit_value;

PMD_SCLK_HIGH

PMD_SCLK_LOW

SET bit_index = bit_index + 1

//write the digital interface stop

PMD_MOSI_LOW

PMD_SCLK_HIGH

PMD_SLAVE_SELECT_HIGH //line will be different for tx/rx

PMD_SCLK_LOW

Electrical Interface

Figure 9 shows the contact numbering for the surface mount transceiver. The diagram shows the module from the bottom view. There are 99 pins intended for high speed low speed signals, power and ground connections. Table 16 provides the signal function and symbols for each of the 99 pins.

Figure 9: Connector Pinout (bottom view)



Table 16: Electrical Pin Description Pin Type Name Description

A1 – A15

B2, B5, B8, B11, B14

C2 – C14

D1, D2, D14, D15

E2, E14

F2, F14

G1, G2, G14, G15

H2, H14,

J1, J2, J14, J15

GND Ground Ground

E1, F1 Hi-Speed RX0P, RX0N CH0 Rx electrical output (differential)

B1, C1 Hi-Speed RX1P, RX1N CH1 Rx electrical output (differential)

B4, B3 Hi-Speed RX2P, RX2N CH2 Rx electrical output (differential)

B7, B6 Hi-Speed RX3P, RX3N CH3 Rx electrical output (differential)

F15, E15 Hi-Speed TX0P, TX0N CH0 Tx electrical input (differential)

C15, B15 Hi-Speed TX1P, TX1N CH1 Tx electrical input (differential)

B13, B12 Hi-Speed TX2P, TX2N CH2 Tx electrical input (differential)

B10, B9 Hi-Speed TX3P, TX3N CH3 Tx electrical input (differential)

D3, D13 Control PA, PB Thru for presence detect

H1 Hi-Speed RX_SB Sideband Rx electrical output (single-ended)

H15 Hi-Speed TX_SB Sideband Tx electrical input (single-ended)

K1 Control INT_RX Rx interrupt signal

K2 Control SS_RX Rx slave select

K14 Control MOSI Master out/slave in (SPI)

K15 Control MISO Master in/slave out (SPI)

L1 Control SS_ROM ROM slave select

L2 Control WP_ROM ROM write protect

L14 Control SS_TX Tx slave select

L15 Control INT_TX Tx interrupt signal

M1 Control TEMP Thermistor

M15 Control SCK Serial clock (SPI)

N2,

P2, P3

R2, R3

Power 3.3RX Positive supply voltage for Rx side

N14

P14, P15

R14, R15

Power 3.3TX Positive supply voltage for Tx Side

M2, M14, N1, N15

P1, P15 R1, R15 NC NC No connect



FIBER CONNECTORS The transceiver can accommodate different types of fiber connectors.

MT Ferrule

The MT ferrule is a multi-fiber connector ferrule. It follows the IEC standard 1754-5. The transceiver MT ferrule has a total of 12 fibers disposed inline (see figure 10):

4 transmit fibers

4 receive fibers

4 dark fibers in the center

Figure 10: MT ferrule

Table 17: Optical port description

MTP Connector

An MTP connector consists of an MT ferrule enclosed in a push-on housing to provide easy connections for fiber cables, active, or passive component packages. The transceiver MTP connector has a total of 12 fibers disposed inline (see table 17), similar to the MT ferrule layout:

4 transmit fibers

4 receive fibers

4 dark fibers in the center



Figure 11: MTP Connector (male)

Table 18: Optical port description

MECHANICAL CHARACTERISTICS

Package Outline

Figure 12: Transceiver Mechanical Outline



Interposer Mechanical Outline

Figure 13: Interposer Mechanical Outline



Host Board Mechanical Footprint

Figure 14: Host Board Mechanical Footprint

Host Board Layout Example

Figure 15: PCB layout Example



Compression Hardware

Compression hardware is required to properly mount the transceiver and interposer on the board. For correct operation, the transceiver and the interposer must be pressed to the board with a force of 2.5 kg. Samtec offers a compression hardware kit for purchase, consisting of a spring, a heat sink and spring anchoring hardware, as shown in Figure 16. For part numbers, see ordering information in the following Technical Information Section.

Figure 16: Samtec Compression Hardware Exploded View



TECHNICAL INFORMATION

Regulatory & Compliance

Table 19: Regulatory and Compliance

Electrostatic Discharge (ESD) to the electrical contact

JEDEC Human Body Model (HBM) (JESD22-A114-B)

JEDEC Machine Model (MM) (JESD22-A115-A)

1kV

TBD

Electrostatic Discharge (ESD) to module case

Variation of IEC 61000-4-2 15kV

Electromagnetic Interference (EMI)

FCC part 15 CENELEC EN55022 (CISPR 22A) VCCI class1

TBD

EMI Immunity Variation of IEC 61000-4-3 10V/m, 80 – 1000Mz

Laser eye safety IEC 60825-1 amendment 2 CFR 21 section 1040

Class 1

RoHS compliance RoHS 6/6 directive 2002/95/EC amendment 4054 (2005/747/EC)

40 Gbps On Board Transceiver Part Number

Transceiver Part Number NR TNB 40G 00.00 01 01 M

Product Category Male/Female

Transceiver Bandwidth End Option40Gbps 40G (QDR) -01 MTP Down

56Gbps 56G (FDR) -03 MT

Pigtail length -04 LC

.15m 00.15

.30m 00.30

Other lengths xx.xx

Specific Product Variant01 Standard black fiber sleeving

02 Bare ribbon no sleeving

Bolster Plate - Samtec Part Number: ASP-168609-01-C Heatsink - Samtec Part Number: ASP-168610-01-C Spring Clip - Samtec Part Number: ASP-168611-01-C Interposer Socket - Samtec Part Number: ASP-168612-01-C



Definitions

This document uses the following conditions:

All voltages are referred to GND unless otherwise specifically noted.

Currents are defined positive out of the pin.

Application Support

Contact [email protected] for technical support.

mailto:[email protected]

Documents

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