SREE SASTHA INSTITUTE OF ENGINEERING AND TECHNOLOGY, CHEMBARAMBAKKAM DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING LAB MANUAL LAB CODE & NAME: EC2207 & DIGITAL ELECTRONICS LAB III SEMESTER 2012 PREPARED BY: K.SUJA PRIYA STALIN S. ANITA PRIYADARSINI

DIGITAL ELECTRONICS LAB MANUAL EC 2207 DIGITAL ELECTRONICS LAB LIST OF EXPERIMENTS 0 0 3 2 1. 2. Design and implementation of Adder and Subtractor using logic gates. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa 3. 4. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 Design and implementation of 2 bit Magnitude Comparator using logic gate s 8 Bit Magnitude Comparator using IC 7485 5. 6. Design and implementation of 16 bit odd/even parity checker generator using IC74 180. Design and implementation of Multiplexer and De-multiplexer using logic gat es and study of IC74150 and IC 74154 7. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 8. 9. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter 10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flop s. 11. Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description L anguage Page 2

DIGITAL ELECTRONICS LAB MANUAL LIST OF EXPERIMENTS CYCLE I 1. Verification of logic gates. 2. Verification of B oolean theorems. 3. Design and implementation of half adder and full adder. 4. D esign and implementation of half Subtractor and full Subtractor. 5. Design and i mplementation of code converters using logic gates a. Binary to gray b. gray to binary c. BCD TO excess 3 d. Excess 3 to BCD 6. Design and implementation of 4 b it binary Adder/ Subtractor using IC 7483 7. Design and implementation of BCD Ad der using IC 7483. 8. Design and implementation of 2-bit Magnitude Comparator us ing logic gates. 9. Design and implementation of 8-bit Magnitude Comparator usin g IC 7485. 10. Design and implementation of encoder and decoder and study of IC 7445 and IC 74147. CYCLE - II 11. Design and verification of odd & even parity g enerator. 12. Design of 16-bit odd & even parity generator/checker using IC 7418 0. 13. Design and implementation of Multiplexer and De-multiplexer using logic g ates and study of IC 74150 and IC 74151. 14. Implementation of shift registers u sing D Flip- flop. 15. Construction and verification of 4-bit ripple counter. 16 . Construction and verification of Mod-10 / Mod-12 Ripple counters. 17. Design a nd implementation of 3-bit synchronous up/down counter. 18. Simulation of combin ational circuits using Verilog HDL 19. Simulation of sequential circuits using V erilog HDL Page 3

DIGITAL ELECTRONICS LAB MANUAL EXPT NO.:1 STUDY OF LOGIC GATES AIM: To study about logic gates and verify their truth tables. APPARATUS REQUIRED: S.No. 1. NOT GATE NAND GATE 2 I/P NOR cting wires SPECIFICATION IC 0 QTY 1 1 1 1 1 1 1 1 As per 2. 3. 4. 5. 6. 7. 8. 9. COMPONENT AND GATE OR GATE GATE X-OR GATE NAND GATE 3 I/P IC TRAINER KIT Conne 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 IC 741 reqd.

THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR are known as universal gates. AND GATE: The AND gate per forms a logical multiplication commonly known as AND function. The output is hig h when both the inputs are high. The output is low level when any one of the inp uts is low. OR GATE: The OR gate performs a logical addition commonly known as O R function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low. Page 4

DIGITAL ELECTRONICS LAB MANUAL NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high. NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high. NOR GATE : The NOR gate is a contraction of OR-NOT. The output is high when both inputs a re low. The output is low when one or both inputs are high. X-OR GATE: The outpu t is high when any one of the inputs is high. The output is low when both the in puts are low and both the inputs are high. PROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (i ii)Observe the output and verify the truth table. Page 5

DIGITAL ELECTRONICS LAB MANUAL AND GATE: SYMBOL: PIN DIAGRAM: OR GATE: Page 6

DIGITAL ELECTRONICS LAB MANUAL NOT GATE: SYMBOL: PIN DIAGRAM: X-OR GATE : SYMBOL : PIN DIAGRAM : Page 7

DIGITAL ELECTRONICS LAB MANUAL 2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM: 3-INPUT NAND GATE : Page 8

DIGITAL ELECTRONICS LAB MANUAL NOR GATE: RESULT: Thus the logic gates are verified by the truth table. Page 9

DIGITAL ELECTRONICS LAB MANUAL EXPT NO.: DESIGN OF ADDER AND SUBTRACTOR AIM: To design and construct half adder, full adder, half subtractor and full su btractor circuits and verify the truth table using logic gates. APPARATUS REQUIRED: S.No. 1. 2. 3. 4. 5. 6. COMPONENT AND GATE X-OR GATE NOT GATE OR GATE IC TRAINER KIT Connecting Wires SPECIFICATION IC 7408 IC 7486 IC 7404 IC 7432 QTY. 1 1 1 1 1 As reqd. THEORY: HALF ADDER: A half adder has two inputs for the two two outputs one from the sum S and other from the carry osition. Above circuit is called as a carry signal from the significant bits sum from the X-OR Gate the carry out from bits to be added and c into the higher adder p addition of the less the AND gate.

FULL ADDER: A full adder is a combinational circuit that forms the arithmetic su m of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum out put will be taken from X-OR Gate, carry output will be taken from OR Gate. Page 10

DIGITAL ELECTRONICS LAB MANUAL HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and b orrow. The difference can be applied using X-OR Gate, borrow output can be imple mented using an AND Gate and an inverter. FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gate s. In a full subtractor the logic circuit should have three inputs and two outpu ts. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output will be difference output of full subt ractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR. Page 11

DIGITAL ELECTRONICS LAB MANUAL HALF ADDER TRUTH TABLE: A B CARRY SUM 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 K-Map for SUM: K-Map for CARRY: SUM = AB + AB CARRY = AB HALF ADDER Page 12

DIGITAL ELECTRONICS LAB MANUAL FULL ADDER TRUTH TABLE: A B C CARRY SUM 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 K-Map for SUM: SUM = ABC + ABC + ABC + ABC Page 13

DIGITAL ELECTRONICS LAB MANUAL K-Map for CARRY: CARRY = AB + BC + AC LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER Page 14

DIGITAL ELECTRONICS LAB MANUAL HALF SUBTRACTOR TRUTH TABLE: A B BORROW DIFFERENCE 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 K-Map for DIFFERENCE: DIFFERENCE = AB + AB K-Map for BORROW: BORROW = AB LOGIC DIAGRAM: Page 15

DIGITAL ELECTRONICS LAB MANUAL FULL SUBTRACTOR TRUTH TABLE: A B C BORROW DIFFERENCE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1 K-Map for Difference: Difference = ABC + ABC + ABC + ABC K-Map for Borrow: Borrow = AB + BC + AC Page 16

DIGITAL ELECTRONICS LAB MANUAL LOGIC DIAGRAM: FULL SUBTRACTOR FULL SUBTRACTOR USING TWO HALF SUBTRACTOR: PROCEEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the trut h table. RESULT: Thus the basic adders and subtractors have been implemented and verified using logic gates. Page 17

DIGITAL ELECTRONICS LAB MANUAL EXPT. NO.: AIM: DESIGN AND IMPLEMENTATION OF CODE CONVERTOR To design and implement following code convertor using logic gates. (i) (ii) (ii i) (iv) 4 bit Binary to gray code converter 4 bit Gray to binary code converter BCD to excess-3 code converter Excess-3 to BCD code converter APPARATUS REQUIRED: S.No. 1. 2. 3. 4. 5. 6. COMPONENT X-OR GATE AND GATE OR GATE NOT GATE IC TRAINER KIT Connecting wires SPECIFICATION IC 7486 IC 7408 IC 7432 IC 7404 QTY. 1 1 1 1 1 As per reqd. THEORY: The availability of large variety of codes for the same discrete element s of information results in the use of different codes by different systems. A c onversion circuit must be inserted between the two systems if each uses differen t codes for same information. Thus, code converter is a circuit that makes the t wo systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses f our bits to represent a decimal digit. There are four inputs and four outputs. G ray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is de signed. The Boolean functions are obtained from K-Map for each output variable. Page 18

DIGITAL ELECTRONICS LAB MANUAL A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by cod e and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a func tion of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram t hat implements this circuit. Now the OR gate whose output is C+D has been used t o implement partially each of three outputs. A) 4 BIT BINARY TO GRAY CODE CONVER TOR TRUTH TABLE: Binary 0 0 0 1 1 1 1 B1 0 0 1 G3 0 0 0 0 0 0 0 0 G1 0 0 1 1 1 1 Page 19 Code B3 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 B2 1 0 0 1 1 B0 0 1 0 1 0 Gray Code G2 0 0 0 0 1 G0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 0 0

DIGITAL ELECTRONICS LAB MANUAL K-Map for G3: G3 = B 3 K-Map for G2: = Hence, = + . This is similar to X-OR gate. Page 20

DIGITAL ELECTRONICS LAB MANUAL K-Map for G1: = Hence, K-Map for G0: = + . This is similar to X-OR gate. = Hence, = + . This is similar to X-OR gate. Page 21

DIGITAL ELECTRONICS LAB MANUAL BINARY TO GRAY CODE CONVERTOR LOGIC DIAGRAM: Page 22

DIGITAL ELECTRONICS LAB MANUAL B) 4 Bit GRAY TO BINARY CODE CONVERTOR TRUTH TABLE: Gray Code G3 G2 G1 G0 B3 Binary Code B2 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Page 23

DIGITAL ELECTRONICS LAB MANUAL K-Map for B3: B3 = G3 K-Map for B2: = Hence, B = + . This is similar to X-OR gate. Page 24

DIGITAL ELECTRONICS LAB MANUAL K-Map for B1: = = Hence, K-Map for B0: = = = (

+ + + + )+ where = ( + + + ). = . Using Boolean theorems, = + + + + + + + Page 25

DIGITAL ELECTRONICS LAB MANUAL This expression cannot be reduced by K Map. Will try to reduce the expression us ing Boolean theorems. Taking common terms, = ( + = ( = = = = = = ( ( + + ) + where )+ + ( ) ( ) )+G3G2 ( ) ) + G3 ( ) ( + )+ ( + ) + G3G2 X + G3 )+ ( = + where X = (G1G0) replace X and Y LOGIC DIAGRAM: Page 26

DIGITAL ELECTRONICS LAB MANUAL C) BCD TO EXCESS 3 CODE CONVERTOR: TRUTH TABLE: BCD CODE B3 B2 B1 B0 G3 EXCESS 3 CODE G2 G1 G0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 K-Map for E3: = + + B3+B2 (B1=B0) Page 27

DIGITAL ELECTRONICS LAB MANUAL K-Map for E2: = + = ( + = + + ) + ( + ) Picking the common terms out where = K-Map for E1: = + Page 28 = = + =>

DIGITAL ELECTRONICS LAB MANUAL K-Map for E0: LOGIC DIAGRAM: Page 29

DIGITAL ELECTRONICS LAB MANUAL D) EXCESS 3 TO BCD CODE CONVERTOR: TRUTH TABLE: X1 X2 X3 X4 A B C D 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 K-Map for A: A = X1 X2 + X3 X4 X1 Page 30

DIGITAL ELECTRONICS LAB MANUAL K-Map for B: B = X2X3 + X2 X4 + X2X3X4 Picking the common terms out. ) where = K-Map for C: = + => Page 31 = = + => = ( =( ( + + + )

DIGITAL ELECTRONICS LAB MANUAL K-Map for D: LOGIC DIAGRAM: Page 32

DIGITAL ELECTRONICS LAB MANUAL PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables. RESULT: Thus the given code converters have been designed and verified. Page 33

DIGITAL ELECTRONICS LAB MANUAL EXPT. NO.: DESIGN OF 4-BIT ADDER AND SUBTRACTOR AIM: To design and implement 4-bit adder and subtractor using IC 7483. APPARATUS REQUIRED: S.No. 1. 2. 3. 3. 4. IC EX-OR GATE NOT GATE IC TRAINER KIT C onnecting wires COMPONENT SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. 1 1 1 1 As per reqd. THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces th e arithmetic sum of two binary numbers. It can be constructed with full adders c onnected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bit s of B are designated by subscript numbers from right to left, with subscript 0 de noting the least significant bits. The carries are connected in chain through th e full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4. 4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder wi th inverters, placed between each data input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction. 4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be com bined into one circuit with one common binary adder. The mode input M controls t he operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtr actor. Page 34

DIGITAL ELECTRONICS LAB MANUAL LOGIC DIAGRAM OF 4-BIT BINARY ADDER LOGIC DIAGRAM of 4-BIT BINARY SUBTRACTOR Page 35

DIGITAL ELECTRONICS LAB MANUAL LOGIC DIAGRAM OF 4-BIT BINARY ADDER/SUBTRACTOR: PIN DIAGRAM FOR IC 7483: Page 36

DIGITAL ELECTRONICS LAB MANUAL TRUTH TABLE: Input Data A Input Data B Addition Subtraction NO. A4 A3 A2 A1 B4 B 3 B2 B1 C S4 S3 S2 S1 1 0 0 0 0 0 1 0 0 1 0 1 0 NO. 10 B D4 D3 D2 D1 1 0 1 1 0 N O. 6 1 0 0 0 1 0 0 0 1 0 0 0 0 16 1 0 0 0 0 0 0 0 1 0 1 0 0 0

0 1 0 1 0 10 0 1 0 1 0 -6 0 0 0 1 0 1 1 1 0 1 0 0 0 8 0 1 0 1

0 -6 RESULT: Thus the Binary adder and Subtractor have been implemented using IC 7483 and verified. Page 37

DIGITAL ELECTRONICS LAB MANUAL EXPT. NO.: AIM: DESIGN OF BCD ADDER To design and implement 4-bit adder and subtractor using IC 7483. APPARATUS REQUIRED: S.No. 1. 2. 3. 3. 4. IC EX-OR GATE NOT GATE IC TRAINER KIT C onnecting wires COMPONENT SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. 1 1 1 1 As per reqd. THEORY: 4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being a n input carry. The output of two decimal digits must be represented in BCD and s hould appear in the form listed in the columns. A BCD adder that adds 2 BCD digi ts and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum. Page 38

DIGITAL ELECTRONICS LAB MANUAL TRUTH TABLE: BCD SUM S4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 K MAP S3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CARRY C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Y = S4 (S3 + S2) Page 39

DIGITAL ELECTRONICS LAB MANUAL LOGIC DIAGRAM: BCD ADDER PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables. RESULT: Thus the BCD adder have been designed using IC 7483 and verified. Page 40

DIGITAL ELECTRONICS LAB MANUAL EXPT. NO.: DESIGN OF 2-BIT MAGNITUDE COMPARATOR AIM: To design and implement 2 bit magnitude comparator using basic gates. APPARATUS REQUIRED: S.No. 1. 2. 3. 4. 5. 6. AND GATE COMPONENT SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 QTY. 2 1 1 1 1 As per reqd. X-OR GATE OR GATE NOT GATE IC TRAINER KIT Connecting wires THEORY: The comparison of two numbers is an operator that determine one number i s greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine thei r relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) AB 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A = 0 + + Page 43DIGITAL ELECTRONICS LAB MANUAL K MAP (AB 0 1 0 0 A=B 1 0 0 0 A