10/12/2004 T0/V0 meetingP. Antonioli / INFN-Bologna TOF readout Reminder of TOF readout scheme and TOF readout modules Overview of specifications with

10/12/2004 T0/V0 meeting P. Antonioli / INFN-Bologna

TOF readout

• Reminder of TOF readout scheme and TOF readout modules• Overview of specifications with an emphasis on requirements for groups who want to use TOF electronis


TOF readout reminder

18 TOF supermodules

Crates with HPTDC

Front-End cards with ASIC (NINO)

8 mRad-tolerance issues for electronics inside crates


TOF readout reminder (2)6U depth x 9U height


TRM reminder

VM

E b

us

HPTDC

HPTDC

Output Fifo

ReadoutController VME

Interface

EventManager

SRAM

SRAM

32

32

TRG

TRG

32

32

32

32

32

x 15

x 15

L2r

L2a

L1

INPUTS (LVDS)

INPUTS (LVDS)

684 Tdc Readout Module inside crates

Tested all components during 2004 irradiationcampaigns

SRAMHPTDC LUT

EVENT BUFFERS

FLASH

C

FIRMWARE HPTDC LUT

Functionalities implemented by an FPGA

BOOTSEL WATCHDOG


Final TRM layout

To allow maintenance, easy mounting operation and matching with front end, HPTDC mounted on 24 ch piggy back

HPTDC

HPTDC

HPTDC

H11

-RA

A-1

00


Final TRM layout (2)

FP

GA

uC LVC543LVC543LVC543LVC543LVC543LVC543LVC543

LVC

543

SR

AM

SR

AM

DS

P

FIF

O

HP

TD

C

HP

TD

C

HP

TD

C

H11-RAA-100

5 piggyback cards per side, 1 central PCB for FPGAs and memories, central aluminium bar for heat dissipation

6U MB prototype housing 2 PB


Radiation levels reminder

Radiation levels expected at ALICE/TOF:

1.2 Gy/10 years (TID)

Total neutron fluence (>20 MeV): 1.6 109 /cm2/10 years.

Total charged hadrons (>20 MeV): 5.3 108 /cm2/10 years.

89 Hz/cm2 expected in PbPb MB events (hadrons+neutrons > 20 MeV).

For ALICE/TOF careful design needed to handle SEU, Degradation for TID effects neglectable.Latchup protections needed.

Some specifications modified in 2004 due to the need to implement radiation tolerant electronics.


DRM reminderTasks:1. Read data on VME backplane (from TRM)2. Send data to central Alice DAQ through DDL3. Provide interface with trigger (TTC)4. Provide Slow Control function/access to VME5. Actel reprogramming

Work done during 2004:Developed and tested DDL interfaceDeveloped and tested TTC interfaceRadiation test to check various slow control solutionsOn-going definition of crate/TRM specifications following tender won by CAEN and impacting on DRM specs.


Final DRM scheme

VM

E b

us

Readout VME interface

FPGA: Actel ProAsic+

Slow control accessFPGA: Actel ProAsic+

SRAM

SRAMEVENT BUFFERS

FLASH

C

FIRMWARE

BOOTSEL WATCHDOG

TTCrx

DDL SIU

Optical link to PC (PCI bus)

VM

E A

CC

ES

S

ARM(Actel reprogramming)

Eth0/ Slow Control backup


How we arrived here...

DDL integration tested with DRM prototype card (Dec ’03/Jan ’04)

TTC integration tested (July ’04) with DRM prototype card + TTCvi/TTCex + LTU (Sep/Oct ’04)

Tests done for TRM emphasized rad-tol problems with Altera FPGAs. Need to move FPGA TRM (now Actel) reprogramming to DRM (this makes DRM/TRM specifications much more interconnected)

PowerPC from Artesyn as slow control solution successfully tested in magnetic field (Dec ’03), but not encouraging test in radiation (PSI/May ’04). Looked for a different solution. Optical link tested in radiation.

The use of new DDL-D-RORC cards (with two optical links each) allows to avoid master/slave scheme between the two crates, simplifying our design (decision taken March ’04, without any impact on foreseen costs) and making readout much more robust (every crate is “independent”). NOT RELEVANT FOR T0


Rad tests and FPGA...

• PSI May & June ’04: Altera Stratix, Flash, RAM, C, low-drop, current limited p-switch, PowerPC• LNL July ’04: HPTDC with heavy ions• CRC/Louvain Nov ’04: optical link and ARM processor

• Assessed SEU rates for almost all components (not discussed here, see LECC2004 paper). Stratix for TRM is not a viable option.• Moved to reprogrammable Flash based FPGA (Actel ProAsic Plus) [rad tests in ALICE and LHCb ok)• BUT: Additional logic needed to support Actel reprogramming


Actel reprogrammingDue to the technology inherently more robust (Flash vs RAM) configuration upset absent.

Need of special voltages during reprogramming: +16.2, -13.5 V

Configuration is not simply a matter of handlong a download through a passive serial Flash, but the firmware code needs to be interpreted while downloading (RAM also needed for staging)

We added 2 power supply (x crate) providing +16.2 and -13.5 V (we will use +/- 12 V pins).

We wil use one external (to the TRM) C and use JTAG on the backplane (MTM bus on VME64X)


Actel reprogramming (2)

High integration neededPrescriptive steps to start reprogramming (power up / addressing / etc)Crate VME ... Now not so standard!


Move slow control outside

The “big” change is related to the choice of the slow control/configuration solution: we move outside the “intelligent” part (18 PC in control room, each connected to 4 crates).

Optical PCI-VME adapters commercially available. Make it rad-tolerant implementing FPGA with Actel + use serializer/deserializer tested in radiation[successfully tested at Louvain in Nov. ’04]

V2718 from CAEN


VME mastering

Test carried out jointly with CAENModified firmware of their VME Master(V1718/V2818/A2818). FPGA initiating VME cycles when in DAQ mode(end Oct ’04)

HPTDC

Trigger

DS

DTACK

CDM prototype

250 ns!


CPDMClock and pulser distribution module

- Hosted only in one crate every two- “simple” but “delicate” card- No VME interface required, latch-up protections as for TRM/DRM/LTM- tests carried out to check clock jitter of present clock distribution scheme defined clock cable and connectors - the pulser section of this card is not relevant for T0


Clock Distribution tests

-Over 16 channels tested in optical fan-out jitter alwayswell below 15 ps- Opt.rec/LVDS adaptation ok.


Clock jitter and distribuition

Defined high quality clock cable and connectors for distribution from CPDM to TRM/DRM/LTM,Tripolar connectors (including shield) from Tyco (CPDM) and Fischer

-Over 16 channels tested in optical fan-out jitter alwayswell below 15 ps- Opt.rec/LVDS adaptation ok.

Tyco: CPDM side

Fischer: TRM side


P2 bus

Through P2 main synch and trigger signals distributed to TRMs.

All signals LVTTL (the most time critical ones “LVTTL differential”)

DRDY and BUSY for readout.

ON/FAULT signals for control.


Guidelines for TRM users

Questions:- 48 channels leading edge only- 96 channels after your charge to time converter- correct?- others?

About demultiplexing story: Working in VHRM, leading edge only, 4 channels/HPTDC maximum bandwidth: 5 MHz (which is different from dead-time and different from buffer occupancy).

T0 needs 156 ch, but with only 4 ch/HPTDC, so T0 needs two TRMs


• Input signals must be LVDS• We use VHDCI connectors, with custom pin-out, 24 pairs per cable.• We use Amphenol Skewclear cables.• Tested up to 7 m, using NINO as LVDS driver.• Please check carefully cable length and your LVDS driver.• You will need at least 156/12=13 cables (you will use one signal every 2)

Guidelines for TRM (2)


Guidelines for TRM (3)

Data are matched on L1 and moved in memory buffers, waiting for L2a. TRM memory size (512 kB) designed for Pb/Pb TOF occupancy and 240 channels/TRM. Please check if it is ok for your need.

In principle T0 doesn’t need CPDM but you need to provide to the 2 TRMs and 1 DRM, high quality LHC clock in LVDS standard, using the Fischer tripolar connector.

Our suggestion: use our CPDM. You need to bring to the CPDM LHC clock with unimodal fibre (could be interesting to send it from the same optical fan-out used for TOF crates).


Guidelines for crates

Please consider the following (just to use the crate as it is):- such a system needs water (but we should test if it is really necessary: just 4 cards over 12, and you can put fans around);- you need also a PC with optical link to handle the SCL- through a branch controller we power (48 V) and control LV (and ON/FAULT pins) of each card (could be managed by TOF directly but we must check cables, etc.). Communication through an OPC server (or may be TCP-IP/DIM interface to PVSS). To be checked if you can simply connect to our LV system

T0 crate:

DRM

CPDM

TRM

TRM


Guidelines for crates (2)If T0 wants to add other cards to the crate:- Do not put other VME masters inside, don’t use BR lines- Note voltages: 3.3 V only (even on 5 V pins) and +16.2/-13,5 V (normally not available) on +12/-12V pinshttp://www.bo.infn.it/alice-tof-hw/public/docs/TOFbusandcratespecs.pdf

- You need to use cardlok. No “guides”.http://www.bo.infn.it/alice-tof-hw/public/docs/cardlok.pdf

- Don’t interfere with P2 bus (rows A-C strictly defined) and implement ON/FAULT signalshttp://www.bo.infn.it/alice-tof-hw/public/docs/TOFbusandcratespecs.pdf

- Please note distance of P1 from bottom is not standard + 6Ux9U format (not P3, P1 in the middle) + VME64X connectorshttp://www.bo.infn.it/alice-tof-hw/public/docs/TOFcrates-P1P2positions.pdf


Conclusions

Working out the TOF readout project, precise specifications now have been elaborated. Unfortunately (essentially for radiation tolerance and magnetic field issues) crates are not so standard as we originally hoped.

T0 is welcome to use our readout electronics, but please be aware of specifications to be followed and the need for deployement near T0 electronics.

Please be in touch with us, especially consider we don’t have spares for T0 and specific orders must be put in place (funding to be defined)!


DDL integration reminder(results already presented at CR4/March 2004)

DRM prototype with DDL SIU

• Bandwidth of 60-90 MB/s with fixed packet size of 2 – 5 kB

• DATE Version 4.7, Readout Version 4.6

• Event rate up to 330 Hz

• No errors over 60 M events

Event rates vs Packet Size

0

100

200

300

400

1 2 5 10 20

Packet Size (Kb)

Ra

tes

(Hz)

Avg Rate


TTC integration reminderTTCrm mounted on DRMprototype

Trigger distributionto HPTDC cards

TTCvi TTCex

HPTDC cards

Tested decoding of L1/L2 messages

Tested LTU (received at October)

No problem foreseen

Documents

10/12/2004 T0/V0 meetingP. Antonioli / INFN-Bologna TOF readout Reminder of TOF readout scheme and TOF readout modules Overview of specifications with