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The Simplified Instructional Computer (SIC)

Hsiang-Fu YuNational Taipei University of Edu

cation

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Outline The Simplified Instructional

Computer (SIC) (Sec. 1.3) Traditional CISC Machines (Sec.

1.4) RISC Machines (Sec. 1.5)

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SIC Architecture Two versions

SIC SIC/XE (extra equipments or extra

expensive) SIC program can be executed on SIC/XE. (upward

compatible)

Memory consists of 8-bit bytes. 3 consecutive bytes form a word (24 bits)

There are 215 (32K) bytes in the memory

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Registers There are 5 registers Each is 24 bits in length

Mnemonic Number Special useA 0 Accumulator; used for arithmetic operationsX 1 Index register; used for addressingL 2 Linkage register; JSUB stores the return address in this register

PC 8 Program counterSW 9 Status word, including a Condition Code (CC)

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Data Format Integer

24-bit binary numbers 2’s complement representation is

used for negative numbers Character

store using their 8-bit ASCII codes There is no floating-point hardware

on SIC

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Instruction Format All machine instructions on SIC has

the following 24-bit format

Only two addressing modes

X is used to indicate indexed-addressing mode

8 1 15opcode x address

Mode Indication Target address calculationDirect x=0 TA=addressIndexed x=1 TA=address+(X)

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Instruction Set Load and store registers

LDA, LDX, STA, STX Integer arithmetic

ADD, SUB, MUL, DIV, all involve register A and a word in memory

Comparison COMP, involve register A and a word in

memory set a condition code CC to indicate the

compare result

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Instruction Set (cont.) Conditional jump

JLE, JEQ, JGT, etc. test the setting of CC and jump accordingly

Subroutine linkage JSUB

jump to the subroutine, placing the return address in register L

RSUB return by jumping to the address contained in register L

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Input and Output One byte at a time to or from the

rightmost 8 bits of register A Each device has a unique 8-bit ID code Test device (TD)

test if a device is ready to send or receive a byte of data

Read data (RD) read a byte from the device to register A

Write data (WD) write a byte from register A to the device

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SIC/XE Architecture Memory size

1 megabytes (220 bytes) An address (20 bits) cannot be fitted into a

15-bit field as in SIC Standard Lead to changes in instruction formats and

addressing modes Extra registers

Mnemonic Number Special useB 3 Base register; used for addressingS 4 General working register - no special useT 5 General working register - no special useF 6 Floating-point acumulator (48bits)

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Data Format The same as that of SIC There is a floating-point data type with

the following format fraction is between 0 and 1 exponent is between 0 and 2047 Zero is presented as all 0

1 11 36s exponen

tfraction

(-1)s*fraction*2(exponent-1024)

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Instruction Formats

e = 0

e = 1

8opcode

8 4 4opcode r1 r2

Format 1 (1 byte)

Format 2 (2 bytes)

6 1 1 1 1 1 1 12opcode n i x b p e dispFormat 3 (3 bytes)

6 1 1 1 1 1 1 20opcode n i x b p e addressFormat 4 (4 bytes)

Formats 1 and 2 do not reference memory at all

Bit e distinguishes between formats 3 and 4Large memory extends addressing capacity

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Addressing Modes

n i x b p e

opcode 1 0 0 disp (12bits)

b=1, p=0, TA=(B)+disp (0disp 4095)

n i x b p e

opcode 0 1 0 disp (12bits)

b=0, p=1, TA=(PC)+disp (-2048disp 2047)

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Addressing Modes (cont.)

n i x b p e

opcode 0 0 0 disp (12bits)Format 3: b=0, p=0, TA=disp (0disp 4095)

n i x b p e

opcode 0 0 0 1 addr (20bits)Format 4: b=0, p=0, TA=addr

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Addressing Modes (cont.) Indexed addressing mode

n i x b p e

opcode 1 0 0 0 disp (12bits)TA=(X)+disp

n i x b p e

opcode 1 0 1 0 disp (12bits)TA=(X)+disp+(PC)

n i x b p e

opcode 1 1 0 0 disp (12bits)TA=(X)+disp+(B)

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Addressing Modes (cont.)

Immediate addressing mode (n = 0, i =1) The target address is used as the operand

Indirect addressing mode (n = 1, i = 0) The word at the location given by the target address is

fetched The value contained in this word is then used as the

address of the operand value Simple addressing mode

The target address is taken as the location of the operand (n = 1, i = 1) used by SIC/XE (n = 0, i = 0) used by SIC

Indexed addressing cannot be used with immediate or indirect modes.

For formats 3 and 4:

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4: Format 4 instructionD: Direct-addressing instruction , i.e., non-relative addressing , b = 0 and p = 0A: Assembler selects either program-counter relative or base- relative modeS: Compatible with SIC

18All of these instructions are LDA.

PC-relative simple addressing: (PC) + dispBase-relative indexed simple addressing: (B) + disp + (X)PC-relative indirect addressing: (PC) + dispImmediate addressing: dispSIC simple addressing: b/p/e + dispSimple addressing: addr

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Instruction Set LDB and STB Floating-point operations

ADDF, SUBF, MULF, DIVF Register move

RMO Register-to-register operations

ADDR, SUBR, MULR, DIVR Supervisor call for generating system calls into

the operating system SVC

I/O channel operation similar to DMA SIO: start, TIO: test, HIO: halt

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Complete Instruction Set

P: privileged instruction X: available only on XEF: floating- point InstructionC: condition code CC set to indicate result of operation

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SIC Programming Examples

Immediate addressing makes the program run faster because it need not fetch five from the memory.

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BETA <- (ALPHA + INCR - 1) DELTA <- (GAMMA + INCR - 1)

SIC Programming Example (Fig. 1.3a)

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This program will execute faster becauseit need not load INCR from memory each time when INCR is needed.

SIC/XE Programming Example (Fig. 1.3b)

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SIC Programming Example (Fig. 1.4a) Looping and indexing: copy one

string to another

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This program will execute faster becauseTIXR need not compare the index valueto a memory variable.

SIC/XE Programming Example (Fig. 1.4b)

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Gamma [] <- Alpha [] + Beta []

SIC Programming Example (Fig. 1.5a)

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This program will execute fasterbecause it uses register-to-registeradd to reduce memory accesses.

SIC/XE Programming Example (Fig. 1.5b)

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Input and Output Example

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SIC Programming Example (Fig. 1.7a)

Read 100 words into the record buffer

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SIC/XE Programming Example (Fig. 1.7b)

Use TIXR makes this program run faster

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Reduced Instruction Set Computer (RISC) Machines RISC system

Instruction Standard, fixed instruction format Single-cycle execution of most instructions Memory access is available only for load and store

instruction Other instructions are register-to-register

operations A small number of machine instructions, and

instruction format A large number of general-purpose registers A small number of addressing modes

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Some RISC machines SPARC family PowerPC family Cray T3E ARM MIPS

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Traditional (CISC) Machines Complex Instruction Set Computers

(CISC) Complicated instruction set Different instruction formats and lengths Many different addressing modes

Examples VAX Intel x86 Processors