1. S. Lin, Y.B. Kim and F. Lombardi, "Design of a Ternary Memory Cell Using CNTFETs,” IEEE...
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Department of Electrical, Computer and Information Technology Islamic Azad University of Qazvin Subject: presentation an article Student:Framarz aghaei Master:Dr. Dr. Shah-Hosseini 1
1. S. Lin, Y.B. Kim and F. Lombardi, "Design of a Ternary Memory Cell Using CNTFETs,” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 5, SEPTEMBER 2012
S. Lin, Y.B. Kim and F. Lombardi, "Design of a Ternary Memory
Cell Using CNTFETs, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11,
NO. 5, SEPTEMBER 2012 Abstract, Index Terms I.INTRODUCTION
II.CARBON NANOTUBE FIELD-EFFECT TRANSISTOR III.TERNARY LOGIC DESIGN
A.Review of Ternary Logic B.Ternary Inverter IV.PROPOSED CELL
DESIGN V.EVALUATION A.Static Noise Margin B.Power Consumption
C.Area VI.CONCLUSION 2
Slide 3
AbstractThis paper presents a novel design of a ternary memory
cell using carbon nanotube field-effect transistors (CNTFETs).
Ternary logic is a promising alternative to conventional binary
logic because it allows simplicity and energy efficiency in modern
digital design due to the reduced circuit overhead in interconnects
and chip area. In this paper, a novel design of a ternary memory
cell based on CNTFETs is proposed; this cell uses a transmission
gate for the write operation and a buffer for the read operation to
make them separate. Chirality of the CNTFETs is utilized for
threshold voltage control, thus avoiding the use of additional
power supplies. 3
Slide 4
Extensive simulation results using SPICE are reported to show
that the two memory operations of the proposed ternary cell perform
correctly at 0.9 V power supply. The static noise margin and
read/write delay of the proposed ternary memory cell are also very
good; by utilizing the latest CNTFET layout design tools, it is
shown that the proposed ternary memory cell achieves a significant
saving in area (41.6%) compared with its CMOS ternary counterpart
at 32 nm. Index TermsCarbon nanotube field-effect transistor,
multiplevalued memory design. 4
Slide 5
I.INTRODUCTION TRADITIONALLY, digital computation is performed
using two-valued logic, i.e., there are only two possible values (0
or 1, true or false) in the Boolean (binary) space. Multiplevalued
logic (MVL) has attracted considerable interest due to its
potential advantages over binary logic for designing high
performance digital systems [1], [2]. Theoretically, MVL has the
potential of improving circuit performance for applications, such
as arithmetic and digital signal processing. [1] M. Mukaidono,
Regular ternary logic functions - ternary logic functions suitable
for treating ambiguity, IEEE Trans. Comput., vol. C-35, no. 2, pp.
179183, Feb. 1986. [2] K. C. Smith, The prospects for multi-valued
logic: A technology and applications view, IEEE Trans. Comput.,
vol. C-30, no. 9, pp. 619634, Sep. 1981. 5
Slide 6
Compared to a binary design, a ternary logic (or three-valued
logic) implementation requires fewer operations, less gates, and
signal lines; hence, it is possible for ternary logic to achieve
simplicity and energy efficiency in digital design, because this
type of logic reduces the complexity of interconnects and chip area
[3]. In a ternary system, it only takes bits to represent an n-bit
binary number; with more and more information and complex
computation in todays computers, ternary logic systems are capable
of providing significant power and area efficiency compared to
traditional binary systems. Furthermore, serial and serialparallel
arithmetic operations can be carried out faster if ternary logic is
employed. [3] P. C. Balla and A. Antoniou, Low power dissipation
MOS ternary logic family, IEEE J. Solid-State Circuits, vol. 19,
no. 5, pp. 739 749, Oct. 1984. 6
Slide 7
Extensive research on the design and implementation of ternary
logic using complementary metal-oxide semiconductor (CMOS) can be
found in the technical literature [3], [4]. Chip area and power
dissipation can be reduced by more than 50% using an efficient MVL
implementation for a signed 32-bit multiplier compared to its
fastest binary counterpart [5]. MVL modules have been inserted in
binary CMOS ICs to enhance performance[6]. [3] P. C. Balla and A.
Antoniou, Low power dissipation MOS ternary logic family, IEEE J.
Solid-State Circuits, vol. 19, no. 5, pp. 739 749, Oct. 1984. [4]
A. Heung and H. T.Mouftah, Depletion/enhancement CMOS for a lower
power family of three-valued logic circuits, IEEE J. Solid- State
Circuits, vol. 20, no. 2, pp. 609616, Apr. 1985. [5] A.
Raychowdhury and K. Roy, Carbon-nanotube-based voltage-mode
multiple-valued logic design, IEEE Trans. Nanotechnol, vol. 4, no.
2, pp. 168179, Mar. 2005. [6] D. A. Rich, A survey of multi-valued
memories, IEEE Trans. Comput., vol. 35, no. 2, pp. 99106, Feb.
1986. 7
Slide 8
Ternary memory systems, which allow three logic levels instead
of the two of a binary memory, have been studied for years. There
are many designs for implementing combinational ternary logic
circuits with CMOS technology [3], [4]; however, the design of a
simple and robust CMOS ternary memory cell has been very
challenging and mostly elusive. For example, the designs of [23]
use multiple supply voltages to achieve the ternary design. [3] P.
C. Balla and A. Antoniou, Low power dissipation MOS ternary logic
family, IEEE J. Solid-State Circuits, vol. 19, no. 5, pp. 739 749,
Oct. 1984. [4] A. Heung and H. T.Mouftah, Depletion/enhancement
CMOS for a lower power family of three-valued logic circuits, IEEE
J. Solid- State Circuits, vol. 20, no. 2, pp. 609616, Apr. 1985.
[23] H. T. Mouftah and I. B. Jordan, Design of ternary
COS/MOSmemory and sequential circuits, IEEE Trans. Comput.,
vol.C-26, no. 3, pp. 281288, Mar. 1977. 8
Slide 9
However, additional supplies introduce significant complexity
in power grid design and are often very costly. In the design of
[24], only one power supply is used, but this design requires
multiple threshold voltages (in which one threshold voltage level
needs to be very close to the power supply); therefore, it is
difficult to implement it using todays CMOS fabrication process.
The design of a ternary memory cell in [25] uses a transistor of
large size; this makes such ternary design inappropriate for high
density integration. [24] U. Cilingiroglu and Y. Ozelci,
Multiple-valued static CMOS memory cell, IEEE Trans. Circuits Syst.
II, Analog Digit. Signal Process., vol. 48, no. 3, pp. 282290, Mar.
2001. [25] Z. Kamar and K. Nepal, Noise margin-optimized ternary
CMOS SRAM delay and sizing characteristics, in Proc. IEEE Int.
Midwest Symp. Circuits Syst., Aug. 2010, pp. 801804. 9
Slide 10
The carbon nanotube field-effect transistor (CNTFET) is a
promising alternative to a traditional bulk silicon transistor for
low-power and high- performance designs due to the ballistic
transport and the low OFF- current properties [8][10]. Moreover in
a CNTFET, the threshold voltage is determined by the CNT diameter;
therefore, a multi-threshold design can be accomplished by
employing CNTs with different diameters (chirality) in a CNTFET.
[8] J. Appenzeller, Carbon nanotubes for high-performance
electronicsprogress and prospect, Proc. IEEE, vol. 96, no. 2, pp.
201211, Feb. 2008. [9] H. Hashempour and F. Lombardi, Device model
for ballistic CNFETs using the first conducting band, IEEE Des.
Test Comput., vol. 25, no. 2, pp. 178186, Mar./Apr. 2008. [10] Y.
Lin, J. Appenzeller, J. Knoch, and P. Avouris, High-performance
carbon nanotube field-effect transistor with tunable polarities,
IEEE Trans. Nanotechnol, vol. 4, no. 5, pp. 481489, Sep. 2005.
10
Slide 11
The design of a ternary logic family using CNTFETs has been
proposed in [11]; the basic ternary gates/operators (inverters,
NAND, NOR) have been presented. Ternary arithmetic circuits such as
a full adder and multiplier have been designed as examples of the
application of a ternary gate technique. Simulation results have
confirmed [11] that significant power and delay improvements are
possible by utilizing this ternary logic family at both gate and
circuit levels. The authors of [11] show that a design approach
using the CNTFETbased ternary logic is a viable solution for
low-power and highperformance VLSI design in the nanoscaled ranges.
[11] S. Lin,Y. B. Kim, and F. Lombardi, The CNTFET-based design of
ternary logic gates and arithmetic circuits, IEEE Trans.
Nanotechnol., vol. 10, no. 2, pp. 217225, Mar. 2011. 11
Slide 12
Embedded memory occupies the largest percentage area in todays
high-performance designs and this trend has continued unabated over
the years; the demand for larger memories continues also in
computer systems. Solutions to store more information are therefore
been investigated. The use of a larger basis than binary is one of
the possible solutions to meet the demand of increased memory
capacity. So together with the previously proposed ternary logic
family [11], it is also vital to have a high-performance ternary
memory system such that ternary information can be stored and
accessed. [11] S. Lin,Y. B. Kim, and F. Lombardi, The CNTFET-based
design of ternary logic gates and arithmetic circuits, IEEE Trans.
Nanotechnol., vol. 10, no. 2, pp. 217225, Mar. 2011. 12
Slide 13
To the best knowledge of the authors, this paper introduces the
first circuit design of a ternary memory cell using CNTs as
emerging technology. This ternary cell utilizes the chirality
feature of CNTFETs for threshold voltage control, such that there
is no need to provide additional power supply levels for ternary
operation. The separate features of the proposed circuit for the
write and read operations make this design very efficient. 13
Slide 14
The rest of this paper is organized as follows. Section II
starts with a brief introduction of carbon nanotube transistors,
followed by the review of ternary logic in Section III. A ternary
memory cell is then proposed, analyzed, and evaluated with respect
to the write and read operations in Section IV. Traditional
performance measures for a memory cell design, such as area, power
and delay are simulated by HSPICE in Section V, which is followed
by conclusion in Section VI. 14
Slide 15
II.CARBON NANOTUBE FIELD-EFFECT TRANSISTOR CNTFETs utilize
semiconducting single-wall CNTs to assemble electronic devices [8].
A single-wall carbon nanotube (or SWCNT) consists of one cylinder
only, and the simple manufacturing process of this device makes it
very promising as an alternative to todays MOSFET. An SWCNT can act
as either a conductor or a semiconductor, depending on the angle of
the atom arrangement along the tube. This is referred to as the
chirality vector and is represented by the integer pair (n, m). A
simple method to determine if a carbon nanotube is metallic or
semiconducting is to consider its indices (n, m): the nanotube is
metallic if n = m or nm = 3i, where i is an integer. Otherwise, the
tube is semiconducting. [8] J. Appenzeller, Carbon nanotubes for
high-performance electronics progress and prospect, Proc. IEEE,
vol. 96, no. 2, pp. 201211, Feb. 2008. 15
Slide 16
The diameter of the CNT can be calculated based on the
following equation [12][14]: (1) where a 0 = 0.142 nm is the
inter-atomic distance between each carbon atom and its neighbor.
16
Slide 17
Similar to a traditional siliconbased device, the CNTFET has
four terminals too. As shown in Fig. 1, undoped semiconducting
nanotubes are placed under the gate in the channel region, while
heavily doped CNT segments are placed between the gate and the
source/drain to allow for a low series resistance in the ON-state
[8]. As the gate potential increases, the device is
electrostatically turned ON or OFF, i.e., via the gate. [8] J.
Appenzeller, Carbon nanotubes for high-performance electronics
progress and prospect, Proc. IEEE, vol. 96, no. 2, pp. 201211, Feb.
2008. Fig. 1. Schematic diagram of a carbon nanotube transistor:
(a) cross sectional view and (b) top view. 17 Fig. 1 shows the
schematic diagram of a CNTFET [12][14]. [12] (2008). Stanford
University CNFET Model website [Online]. Available:
http://nano.stanford.edu/model.php?id=23. [13] J. Deng and H.-S.
P.Wong, A Compact SPICE model for carbon-nanotube field-effect
transistors including nonidealities and its applicationPart I:
Model of the intrinsic channel region, IEEE Trans. Electron.
Devices, vol. 54, no. 12, pp. 31863194, Dec. 2007. [14] J. Deng and
H.-S. P.Wong, A Compact SPICE model for carbon-nanotube
field-effect transistors including nonidealities and its
applicationPart II: Full device model and circuit performance
benchmarking, IEEE Trans. Electron Device, vol. 54, no. 12, pp.
3195 3205, Dec. 2007.
Slide 18
The currentvoltage (IV) characteristics of the CNTFET are
similar to those of a MOSFET. The threshold voltage is defined as
the voltage required to turn ON the transistor; the threshold
voltage of the intrinsic CNT channel can be approximated to the
first order as the half-bandgap that is an inverse function of the
diameter [12][14]: [12] (2008). Stanford University CNFET Model
website [Online]. Available:
http://nano.stanford.edu/model.php?id=23. [13] J. Deng and H.-S.
P.Wong, A Compact SPICE model for carbon-nanotube field-effect
transistors including nonidealities and its applicationPart I:
Model of the intrinsic channel region, IEEE Trans. Electron.
Devices, vol. 54, no. 12, pp. 31863194, Dec. 2007. [14] J. Deng and
H.-S. P.Wong, A Compact SPICE model for carbon-nanotube
field-effect transistors including nonidealities and its
applicationPart II: Full device model and circuit performance
benchmarking, IEEE Trans. Electron Device, vol. 54, no. 12, pp.
3195 3205, Dec. 2007. (2) where a = 2.49 A is the carbon to carbon
atom distance, is the carbon - bond energy in the tight bonding
model, e is the unit electron charge, and D CNT is the CNT
diameter. 18
Slide 19
As DCNT of a (19, 0) CNT is 1.487 nm, the threshold voltage of
a CNTFET using (19, 0) CNTs in the channel is 0.293 V [from (2)].
Simulation results have confirmed the correctness of this threshold
voltage analysis. As the chirality vector changes, the threshold
voltage of the CNTFET will also change. Assume that m in the
chirality vector is always zero; then, the ratio of the threshold
voltages of two CNTFETs with different chirality vectors is given
as (3) Equation (3) shows that the threshold voltage of a CNTFET is
inversely proportional to the chirality vector of the CNTs. For
example, the threshold voltage of a CNTFET using (13, 0) CNTs is
0.428 V, compared to a (19, 0) CNTFET with a threshold voltage of
0.293 V. 19
Slide 20
Fig. 2. Threshold voltage of P-type CNTFET with different
chirality vectors. Fig. 2 shows the threshold voltage of a P-type
CNTFET (PCNTFET) with CNTs of different values of a chirality
vector. For an N-type CNTFET (NCNTFET), the threshold voltage
distribution is the same as the P-typeCNTFET, but with opposite
sign [12]. 20
Slide 21
CNTFETs provide a unique opportunity to control the threshold
voltage by changing the chirality vector, i.e., the diameter of the
CNT [5]. [15], [16] have reported advances in manufacturing
processes for well- controlled CNTs. The authors of [17] have
demonstrated a post- processing technique to adjust the threshold
voltage of multiple-tube CNTFETs. In this paper, a multi-tube
CNTFET-based design is utilized when designing the ternary memory
cell. [12] (2008). Stanford University CNFET Model website
[Online]. Available: http://nano.stanford.edu/model.php?id=23. [5]
A. Raychowdhury and K. Roy, Carbon-nanotube-based voltage-mode
multiple-valued logic design, IEEE Trans. Nanotechnol, vol. 4, no.
2, pp. 168179, Mar. 2005. [15] Y. Li, W. Kim, Y Zhang, M Rolandi,
and D. Wang, Growth of singlewalled carbon nanotubes from discrete
catalytic nanoparticles of various sizes, J. Phys. Chem., vol. 105,
pp. 1142411431, 2001. [16] Y. Ohno, S. Kishimoto, T. Mizutani, T.
Okazaki, and H. Shinohara, Chirality assignment of individual
single-walled carbon nanotubes in carbon nanotube field-effect
transistors bymicro-photocurrent spectroscopy, Appl. Phys. Lett.,
vol. 84, no. 8, pp. 1368 1370, Feb. 2004. [17] A. Lin, N. Patil, K.
Ryu, A. Badmaev, L. G. De Arco,C. Zhou, S. Mitra, and H.-S. P.
Wong, Threshold voltage and onoff ratio tuning for multipletube
carbon nanotube FETs, IEEE Trans. Nanotechnol., vol. 8, no. 1, pp.
49, Jan. 2009. 21
Slide 22
IV.TERNARY LOGIC DESIGN In this section, a brief review of the
basic principles of ternary logic design inclusive of the ternary
inverter of [11] (as basic gate) is presented. [11] S. Lin,Y. B.
Kim, and F. Lombardi, The CNTFET-based design of ternary logic
gates and arithmetic circuits, IEEE Trans. Nanotechnol., vol. 10,
no. 2, pp. 217225, Mar. 2011. Ternary logic functions are defined
as the functions having significance if a third value is introduced
to the binary logic. In this paper, 0, 1, and 2 denote the ternary
values to represent false, undefined, and true, respectively. Any
n-variable {X1,...,Xn} ternary function f(X) is defined as a logic
function mapping {0,1,2}n to {0,1,2}, where X = {X1,...,Xn}.
A.Review of Ternary Logic 22
Slide 23
The basic operations of ternary logic can be defined as
follows, where Xi,Xj#{0,1,2} [18]: [18] S. C. Kleene, Introduction
to Metamathematics. Amsterdam,, The Netherlands: North Holland,
1952, pp. 332340. [4] A. Heung and H. T.Mouftah,
Depletion/enhancement CMOS for a lower power family of three-valued
logic circuits, IEEE J. Solid- State Circuits, vol. 20, no. 2, pp.
609616, Apr. 1985. (4) X i + X j = max{X i,X j } X i *X j = min{X
i,X j } where denotes the arithmetic subtraction, the operations +,
* and are referred to as the OR, AND, and NOT in ternary logic,
respectively. The ternary gates are designed according to the
convention defined in (4). 23
Slide 24
B.Ternary Inverter A standard ternary inverter (STI) has been
proposed in [11] and shown in Fig. 3; the STI in Fig. 3 consists of
six CNTFETs with the following characteristics [11]. [11] S. Lin,Y.
B. Kim, and F. Lombardi, The CNTFET-based design of ternary logic
gates and arithmetic circuits, IEEE Trans. Nanotechnol., vol. 10,
no. 2, pp. 217225, Mar. 2011. 1)The chiralities of the CNTs used in
T1/T5, T2/T6, and T3/T4 are (19, 0), (10, 0), and (13, 0),
respectively. 2)The diameters of T1/T5, T2/T6, and T3/T4 are 1.487,
0.783, and 1.018 nm, respectively. 3)The threshold voltages of T1,
T2, and T3 are 0.289, 0.559, and 0.428 V, respectively. 4)The
threshold voltages of T5, T6, and T4 are 0.289, 0.559, and 0.428 V,
respectively. Fig. 3. CNTFET-based STI design of [11]. 24
Slide 25
When the input voltage changes from low to high (at a power
supply voltage of 0.9 V), initially the input voltage is lower than
300 mV. This turns ON both T5 and T6, and both T1 and T2 are turned
OFF; the output voltage is 0.9 V, i.e., logic 2. As the input
voltage increases beyond 300 mV, T6 is OFF and T5 is still ON.
Meanwhile, T1 is ON and T2 is OFF. TABLE I LOGIC SYMBOLS 25
Slide 26
The diode connecting the CNTFETs T4 and T3 produces a voltage
drop of 0.45 V from node n2 to the output and from the output to n1
due to the threshold voltages of T4 and T3. Therefore, the output
voltage becomes 0.45 V, i.e., half of the value of the power supply
voltage. As shown in Table I, half Vdd represents logic 1. Once the
input voltage exceeds 0.6 V, both T5 and T6 are OFF, and T2 is ON
to pull the output voltage down to zero. The input voltage
transition from high to low is similar to the low to high
transition. 26
Slide 27
IV.PROPOSED CELL DESIGN Back to back inverters are used in
traditional memory cells as basic components of the storage element
for the correct states; access transistors (such as pass or
transmission gates) are commonly used to read and write from the
back to back inverters. The design requirement for a memory cell is
usually specified as follows: when the cell is holding the data
(i.e., the access transistors are OFF), the back to back inverters
must be able tohold the bi-stable states; when the cell is ready to
write or read (i.e., the access transistors are ON), then the
access transistors must be able to update the correct state from
the wordlines, or pass the current state to the wordlines. 27
Slide 28
The traditional CMOS cell in a binary memory system uses six
transistors (6T); two NMOS access transistors and two back to back
CMOS inverters. The STI shown in Fig. 3 can be used as a basic
storage element of the ternary memory cell. For the read and write
operations, single-ended read and write access mechanisms are used
as described in more detail next. 28
Slide 29
Fig. 4. Proposed CNTFET-based ternary memory cell. Fig. 5.
Proposed CNTFET-based ternary memory cell (transistor level
implementation). The proposed ternary memory cell design is shown
in the schematic form in Fig. 4; its transistor- level
implementation is shown in Fig. 5. As shown in Fig. 4, the proposed
memory cell consists of two transmission gates: one connected to
wbl for the write operation and one connected to rbl for the read
operation. 29
Slide 30
The basic storage element of the proposed ternary memory cell
consists of two back to back STIs, whose arrangement is very
similar to a conventional binary cell. As shown in Fig. 5, the
basic storage element of this ternary memory cell consists of
transistors T3T14; they keep logic 0, 1, and 2 when the memory cell
is holding data. The threshold voltages of T3 and T9, T4 and T10,
T5 and T11 are 0.289, 0.559, and 0.428 V, respectively, [from (2)].
The threshold voltages of the P-type CNTFETs (T7 and T13, T8 and
T14, T6 and T12) are 0.289, 0.559, and 0.428 V, respectively.
30
Slide 31
The operation of the proposed memory cell can be described as
follows. 1)When the memory cell is holding logic 1, transistors T3,
T5, T6, T7, T9, T11, T12, T13 are ON to hold both nodes q and qb to
the value of 1/2 Vdd; 2)When the memory cell is holding logic 0,
transistors T6, T7, T8, T9, T10, T11 are on to hold node q to 0 and
node qb to the value of Vdd; 3)When the memory cell is holding
logic 2, transistors T3, T4, T5, T12, T13, T14 are ON to hold node
q to Vdd and node qb to 0. 31
Slide 32
The write transmission gate forces the correct data to be
written into the back to back STIs. Fig. 5 shows single-ended
transmission gates T1 and T2 (with the threshold voltages of 0.289
and 0.289 V); these gates are used for the write operation and
ensure that the correct voltage level is written into the memory
cell without dropping any threshold voltage. When the write
wordline wwl is high and wwlb is low, the data on the write bitline
wbl is written into the memory cell. The read buffer consists of
one P-CNTFET (with the threshold voltage of 0.559 V) and one
N-CNTFET (with the threshold voltage of 0.559 V). 32
Slide 33
This read buffer inverts the logic state 0 and 2 stored in node
qb. Its operation is as follows. 1)When the cell is storing a 0
(i.e., node qb is Vdd), T15 is ON and a 0 is read by the
transmission gates T17 andT18. 2)When the cell is storing a 2
(i.e., node qb is 0), T16 is ON and a 2 is read by the transmission
gates T17 and T18. 3) When the cell is storing a 1 (i.e., node qb
is 1/2 Vdd), both T15 and T16 are OFF and the bitline rbl remains
at 1/2 Vdd. 33
Slide 34
The addition of the read buffer avoids the read disturb problem
[20], thus alleviating the static noise margin (SNM) for the
ternary memory (a reduced noise margin has been a major concern in
a multi-valued system design). The read operation is performed by
the read buffer consisting of transistors T15, T16, T17, and T18,
with the threshold voltages of 0.559, 0.559, 0.289, and 0.289 V,
respectively. The read bitline rbl is precharged to 1/2 Vdd in the
ternary memory. Both the read and write operations will be
discussed in more detail next. [20] E. Seevinck, F. J. List, and J.
Lohstroh, Static-noise margin analysis of MOS SRAM cells, IEEE J.
Solid-State Circuits, vol. SSC-22, no. 5, pp. 748754, Oct. 1987.
34
Slide 35
A 1128 ternary memory cell array is simulated to check the
functionality of the proposed memory cell. The write operation of
the proposed ternary cell is performed as follows: the write
bitline wbl is driven to the logic 0, or 1, or 2 and the write
wordlines wwl and wwlb are Fig. 6. Write operation of the proposed
ternary memory cell. accessed with logic 2 and logic 0,
respectively. HSPICE simulation of the write operation is shown in
Fig. 6. As shown in Fig. 6, the write transmission gate (T1 and T2)
allows the correct data (from data_in to wbl) to be written into
the memory cell (q and qb). 35
Slide 36
The read operation of the proposed ternary cell is performed as
follows: rbl is precharged to 1/2 Vdd prior to the read operation,
and the read transmission gates (T17 and T18) are accessed to read
the correct data from the memory cell. The read operation of the
proposed ternary memory cell has been simulated by HSPICE (see Fig.
7) and operates as follows. 1)The ternary memory cell is storing a
logic 2; then, the read bitline rbl is charged to logic 2 when the
read wordlines rwl and rwlb are accessed. 2)The ternary memory cell
is storing a logic 0; the read bitline rbl is discharged to logic 0
when the read wordlines rwl and rwlb are accessed. 3)The ternary
memory cell is storing logic 1; rbl remains at logic 1. A ternary
STI is then connected to the read bitline rbl to sense the voltage
at rbl. 36
Slide 37
TABLE II READ AND WRITE DELAY OF THE TERNARY MEMORY CELL Fig.
7. Read operation of the proposed ternary memory cell. 37
Slide 38
Table II summarizes the read and write delays of the ternary
memory cell at 0.9 V power supply; the write and read delays have
been estimated by the HSPICE simulation as follows. 1)The write
delay is estimated as the time required to flip the cell data after
the write wordline is turned ON during the write operation. The
write delay in HSPICE is measured from the 50% of the write
wordline wwl rising edge to the 50% of the rising/falling edge of
the storage node q, as shown in Fig. 6. 2)The read delay is
estimated as the time required to sense the cell data to the output
after the read wordline is turned ON during read. Therefore, the
read delay in HSPICE is measured from the 50% of the read wordline
rwl rising edge to the 50% of the rising/falling edge of the output
read_out, as shown in Fig. 7. 38
Slide 39
In Table II, the write delay is very small when the original
data in the memory cell is logic 1, i.e., it is easier for the
memory cell to exit the logic 1 state than the logic 0 or 2 state.
V.EVALUATION In this section, a detailed assessment of the proposed
memory cell is presented through a simulation by HSPICE. A CMOS
ternary memory cell design at 0.18 m has been proposed in [25];
however, this design uses multiple power supplies and has very
large read and write delays (3.9 and 1.23 ns, respectively).
Moreover, 30 and 70 transistor widths are used in this design
leading a very large area and power penalties for a memory cell
design. Since there is no CMOS ternary memory cell of similar
dimension as a CNTFET, the proposed CNTFET-based ternary memory
cell is compared with a binary memory cell at 32 nm CMOS technology
for fair comparison. [25] Z. Kamar and K. Nepal, Noise
margin-optimized ternary CMOS SRAM delay and sizing
characteristics, in Proc. IEEE Int. Midwest Symp. Circuits Syst.,
Aug. 2010, pp. 801804. 39
Slide 40
A.Static Noise Margin The stability of a binary memory cell is
usually represented by the SNM; the SNM is defined as the maximum
value of dc noise voltage that can be tolerated by a memory cell
without changing the stored bit [20]. The SNM can be graphically
found on the butterfly curve plot by drawing the voltage transfer
characteristics (VTC) of the inverter and mirroring the VTC for the
same Fig. 8. SNM of the proposed ternary memory cell under process
variations. plot. The same approach used on the binary memory cell
is also applied to the proposed ternary memory cell shown in Fig.
4; the resulting butterfly plot is plotted in Fig. 8. [20] E.
Seevinck, F. J. List, and J. Lohstroh, Static-noise margin analysis
of MOS SRAM cells, IEEE J. Solid-State Circuits, vol. SSC-22, no.
5, pp. 748754, Oct. 1987. 40
Slide 41
As shown in Fig. 8, the butterfly plot of the ternary memory
cell has two more squares (eyes) than the binary memory cell; the
diagonal between the smallest square defines the SNM of the ternary
memory cell. Simulation results show that the SNM is 154.2 mV at
0.9 V power supply voltage for the proposed ternary memory cell
when the memory cell is storing logic 1. Since the read and write
operations are separated, there is no read-disturb problem in the
proposed ternary memory cell. This has been a major concern in a
traditional six transistor (6T) binary memory cell (for the 6T
memory cell, the read SNM is 100.8 mV at 0.9 V power supply, as
shown in Fig. 8). The simulation results for the SNM are consistent
with the results of Table II, i.e., the SNM of the logic 1 state is
the smallest so it is faster to exit the state 1 than to exit
states 2 and 0. 41
Slide 42
It is widely known that process variations significantly affect
performance of nanoscale and MOSFET devices during the fabrication
process (such as oxide thickness and gate width). For CNT-based
devices, the variations in the oxide and gate width have no
negligible impact [27]; due to the nature of CNTFETs, the diameter
of the tubes (thus the chirality), the distance between tubes
(pitch), and the number of tubes under the gate (that determine the
effective width of the transistor) affect CNTFETbased circuits and
devices. The Monte Carlo simulation has been performed to assess
process variations; for simulation, chirality and pitch are modeled
as a 10% Gaussian distribution with variation at the 3 level. The
simulation results are given in Fig. 8. Fig. 8 shows that with
process variation, the worst SNM of the proposed CNTFET ternary
memory cell is 101.8 mV at 0.9 V power supply, hence close to the
32 nm CMOS binary cell in the ideal case. [27] B. C. Paul, S.
Fujitam,M. Okajima, T. H. Lee, H.-S. P.Wong, and Y. Nishi, Impact
of a process variation on nanowire and nanotube device performance,
IEEE Trans. Electron. Devices, vol. 54, no. 9, pp. 23692376, Sep.
2007. 42
Slide 43
B.Power Consumption Power consumption, especially the standby
power consumption, has been a significant concern for memory
systems that usually occupy a large area in a chip design. Compared
to the high-leakage nano-CMOS device, a CNTFET has a significantly
smaller OFF current; therefore, the power consumed when the
transistor is OFF is greatly reduced in CNTFET designs [8]. The
CNTFET has a significantly higher ONOFF current ratio compared to
the MOSFET in the deep sub-micrometer range. Therefore, the standby
power of the CNTFET memory cell is lower compared to its CMOS
counterpart. [8] J. Appenzeller, Carbon nanotubes for
high-performance electronics progress and prospect, Proc. IEEE,
vol. 96, no. 2, pp. 201211, Feb. 2008. 43
Slide 44
The standby power consumption of the proposed CNTFET-based
ternary memory cell is listed in Table III. As shown in Table III,
TABLE III STANDBY POWER OF THE TERNARY MEMORY CELL when the ternary
memory cell is storing 0 or 2, the power consumption is less than
1% of the CMOS 6T binary memory cell, but when storing 1, the
standby power of the ternary cell is nine times larger than the
CMOS 6T binary memory cell due to the diode-connected T5, T6, T11,
and T12 in Fig. 5. 44
Slide 45
C.Area A system-level CNTFET-based design approach and the
layout technique for CNTFET technology have been proposed in [21].
The layout of the proposed ternary memory cell, using the
guidelines presented in [21], is shown in Fig. 9. The write bitline
wbl and the read bitline rbl are connected by the higher layer
metal (not shown in Fig. 9). In the CNTFET-based layout, the
minimum distance between the PUN (P-CNTFET) and PDN (N-CNTFET) is
just limited by lithography (3); this is significantly less than
the minimum distance between PUN and PDN in CMOS (10) [21]. The
area of the ternary memory cell is 57 32 (1824 2 ), compared to
1562 2 as the area of the conventional 6T CMOS (binary) memory cell
at 32 nm bulk CMOS technology [22]. [21] D. Atienza, S. K. Bobba,
M. Poli, G. De Micheli, and L. Benini, Systemlevel design for
nano-electronics, in Proc. 14th IEEE Int. Conf. Electron., Circuits
Syst., Dec. 2007, vol. 1, no. 1, pp. 747751. [22] Y. Morita, H.
Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M.
Yoshimoto, An area- conscious low-voltage- oriented 8T-SRAM design
under DVS environment, in Proc. Symp. VLSI Circuits, Jun. 2007, pp.
256257. 45
Slide 46
For representing ternary logic without the use of additional
power supplies, two 6T binary memory cells can be used. The area of
the proposed ternary cell is only 1.168 times larger than the one
for a single 6T memory cell, i.e., 41.6% area saving is achieved by
the CNTFET- based ternary memory cell design compared to a CMOS
ternary implementation for the same function (utilizing two binary
6T cells). Furthermore, one of the attractive features of the
CNTFET is that it has been reported to be scalable down to 10 nm
channel length or less [12]. Therefore, it is possible for the
proposed CNTFET-based ternary memory cell to achieve even smaller
area than CMOS technology in the next few years. [12] (2008).
Stanford University CNFET Model website [Online]. Available:
http://nano.stanford.edu/model.php?id=23. 46
Slide 47
VI.CONCLUSION This paper has presented the first design of a
ternary memory cell based on CNTFETs. As the threshold voltage of
the CNTFET is a function of the geometry of the CNTFET (i.e., the
chirality and diameter), a novel multidiameter (multithreshold
voltage) CNTFET-based ternary memory cell design has been pursued
in this paper. This memory cell does not require additional power
supplies and the read/write operations are correctly executed by
introducing in the design a transmission gate and a buffer to make
these operations separate. 47
Slide 48
Simulation results using HSPICE have showed that the proposed
CNTFET-based ternary cell performs the correct function during the
read and write operations. It has also been shown that the proposed
ternary cells achieve a high SNM due to the separate read and write
operations, more than 90% lower standby power consumption for the 0
and 2 states and low area compared to a conventional binary CMOS
implementation. The impact of process variations on stability has
also been simulated; simulation results show that the proposed
CNTFET- based ternary memory cell with substantial process
variations still achieves the same SNM as its CMOS binary
counterpart at 32 nm under ideal conditions (i.e., with no process
variations). Therefore, the detailed technology assessment of this
paper demonstrates that CNTFET is a viable candidate for ternary
memory design in the nanoscale era. 48