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RapidIO Testbed Update

Chris Conger

Honeywell Project

1/25/2004

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Outline

RapidIO Cores Calibration Plan and Approach Tundra Switch Testbed Application Target Publication Targets Conclusions

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RapidIO Cores Core information

Logical/Transport Layers supported PHY layer still *assumed* to be supported

Speed grade OK, device family OK, pin count different

Unanswered question on forum Able to generate bit file for complete RapidIO

endpoint Need to edit user constraints file (UCF) to generate

correct bitfile for our FPGAs Current bitfile for Virtex-II Pro 2VP20FF896-5 FPGA

We have Virtex-II Pro 2VP20FF1152-5

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Core Information Example implementation instantiates two endpoints

within single FPGA One endpoint connects target design

Simple block RAM accepts writes, services reads

Other endpoint connects simulation host Generates read and write requests, compares data for validity

Target Design Simulation Host

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Simulation Model Calibration First order of business to validate simulations

Series of simple benchmarks to isolate individual model parameters, tune simulation results Initial tests will be using two endpoints instantiated within same

FPGA Later tests will move to two-board testbed

Concluded by relatively complex application Minimal computation in benchmarking

Proposed benchmarking Series of one-way messages, 32B – 64KB

Tune basic latency, throughput results Repeat above with Rx/Tx-controlled flow control Priority-tweaking useless for 2-node system? After basic model calibration, use testbed to verify conclusions of

simulated experiments when possible 2-node testbed size may limit repeatability of simulated experiments

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Tundra Switch 4-port, 250/500MHz, 8-bit RapidIO switch BGA package, Tundra donated the chip only

Collected and read all documents provided by Tundra User Manual Layout Guidelines Schematic Checklist BGA Application Note

Good news Very complete and detailed documentation Everything we would need to design a PCB to house the switch

Bad news Recommends at least a 12- to 16-layer board ($$$) PCB requirements may be beyond our means to realistically fabricate At very best, it may be a long-shot to hope to include switch this semester

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Potential Testbed Applications At conclusion of basic benchmarking, implement

more full-blown application Would like to target communication-heavy application May use PowerPCs embedded in Virtex-II Pros Physically limited by two nodes

JPEG 2000 compression May be complicated, but Honeywell expressed interest (?)

Fast-Fourier Transform Large portion of our SBR algorithms for Honeywell

Any other VHDL application already implemented on other RC devices in the lab “Plan-B”-type solution, prefer something new

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Conclusion Current status, next steps

Have bit file for RapidIO endpoint Xilinx indicates need for “buffer” between PHY and

Transport layers Looking at why, may need to incorporate into sim. env.

Endpoint provided with simple user application Made for easy expandability for more complex custom

apps Supplied version uses two endpoints within same FPGA

Potential target publication(s) for work LCN ’05 – Local Computer Networks

Abstract: N/A Submission: May 10th

PACT ’05 - Parallel Architectures and Compilation Techniques Abstract: March 23rd

Submission: March 30th