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1
ORTC 2012/13 ITRS WorkIRC and CTSG Plenary
Alan Allan 04/23/2012
Based on [WAS] ORTC Final Rev 1a, 12/13/11[plus backup]
CORRECTED/UPDATED04/23/12
FOR 2012 IRC &CTSG WORK to prepare for
2013 ITRS
2
1) Unchanged for 2010/11: MPU contacted M11) 2-year cycle trend through 2013 [27nm (“14nm” node)]; then 3-year trend to 2026
consider for 2013 ITRS proposal: extend 2yr cycle to 2017/14nm (”7nm” node)2) 60f2 SRAM 6t cell Design Factor Proposal for 2013 ITRS consideration: tbd3) 175f2 Logic Gate 4t Design Factor Proposal for 2013 ITRS consideration: tbd4) Ongoing - evaluate alignment of “nodes” with latest M1 industry status and
also High Performance/Low Power timing needs2) Unchanged for 2010/11 Tables: MPU Functions/Chip and Chip Size Models 1) Design TWG Model for Chip Size and Density Model trends – tied to technology
cycle timing trends and cell design factors2) ORTC line item OverHead (OH) area model, includes non-active area3) Proposal for 2013 ITRS consideration: tbd; based on final consensus of new
proposals3) Updated for 2010/11 Tables: MPU GLpr, GLph – trends “smoothed” by PIDS
modeling; but close to previous targets Proposal for 2013 ITRS consideration: tbd; targeted for 8% CAGR (1/CV/I) intrinsic transistor performance vs. present 2011 ITRS 13% trend
4) Updated for 2010/11 Tables: Vdd Low operating and standby line items from PIDS model track “smoothed” gate length changes Proposal for 2013 ITRS consideration: tbd; targeted for 8% CAGR (1/CV/I) intrinsic transistor performance vs. present 13%
5) Added in 2011 – Table ORTC-6 Battery Energy Storage (Watt-hours) Line Item from iNEMI Roadmap [will update based on 2013 iNEMI roadmap work]
2011 Renewal ITRS ORTC Technology Trend Pre-Summary [and including updates for 2012 Proposals and 2013 ITRS Renewal Preparation]
3
6) Updated in ORTC 2011 Tables - DRAM contacted M1:1) 1-year pull-in of M1 and bits/chip trends; [unchanged]2) no Flattening of DRAM M1 as with Flash Poly** [unchanged]3) 4f2 push out [to 2013]; 2012 Update: 2014/4f24) Increased array efficiency from 56% to 59% [unchanged; needs review]
7) Updated in ORTC 2011 Tables - Flash Un-contacted Poly:1) 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend
to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm; [unchanged]
2) and 3bits/cell extended to 2018; 4bits/cell delay to 2022 [unchanged]8) Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model:
1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 – 2x/2.5yrs) [unchanged]
9) Updated in ORTC 2011 Tables - Flash Bits/Chip and Chip Size Model:1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr
acceleration; then flat @ 1-2Tbits; keep chip size <160mm2); [unchanged]2) New 3D layers Models vs. relaxed half-pitch tradeoffs are now included
in the 2011 Renewal for maximum bits per chip [2012 Update Survey Proposal: 2016 increased from 8/32nm -128/18nm Layers to 16/48nm – 128/24nm Layers (option C in 2011 ORTC Table 2)]
2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
4
10) Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, 1) Flash Survey inputs Updated2) Also IC Knowledge (ICK) model contribution to extend mask levels range3) Proposal for 2013 ITRS consideration: tbd; based on survey plus
modeling consensus of Litho, PIDS, FEP, Design11) Unchanged for 2011[and 2012 Update] - IRC 450mm Position: 1) Timing Status (as of July, 2011 – to be updated by G450C in July, 2012)
1) Consortia work underway2) IDM and Foundry Pilot lines: 2013-14; 3) Production: 2015-162) SEMATECH/ISMI making good progress on 450mm program activities to meet the ITRS Timing
1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development
2) 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers’ schedules [for stated “1xnm technology” goal; note: 19nm-10nm M1 = “10nm-5nm” “nodes”= 2015-2022 (ITRS) – see Inchon Litho public presentation]
3) 450mm increasing silicon demand is needed from consortium demonstrations to support development
3) Europe momentum building - EEMI status reviewed with IRC in Potsdam [update due at Netherlands IRC meetings Apr’12]
4) FI TWG extended 300mm wafer generation in parallel line item header with 450mm; 1) Including Technology upgrade assumptions through end of roadmap2) Assuming compatibility of 300mm productivity extensions into the 450mm generation ;
5) Utilizing a new ITRS-based ICK Strategic commercial model , SEMATECH has developed 300mm and 450mm 2009-2024 Range Scenarios for silicon and equipment demand ; ICK has updated to 2011 ITRS www.itrs.net
12) Updated in 2011 - More than Moore white paper online at www.itrs.net 1) New “Moore’s Law and More” Graphic update included in 2011 ITRS Executive Summary2) MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting3) New MEMS TWG and Chapter added to 2011 ITRS4) Proposals for 2013 ITRS consideration: tbd; ITRS MtM cross-TWG work; plus Weds, 4/25 Europe workshop
includes new iNEMI applications driver presentation (Grace O’Malley/Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al)
)
2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
5
Technology Pacing Cross-TWG Study Group (CTSG) work preparation for 2012 Update [move to 2013 ITRS Renewal (kickoff Dec’12) including new cooperation with PIDS, M&S, and the NIST, ST (MASTAR), and Purdue (TCAD) modeling teams]:
2011 Renewal ITRS ORTC Technology Trend Summary (cont.)
– IRC Equivalent Scaling Graphic Update• Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility
materials pathway• Proposals for pull-in placement of MuGFET [2012 Update work] [preparation for 2013 ITRS]
and III/V Ge Timing [consider in 2013 ITRS work] (one IDM or Foundry company may lead technology production ramp)
– PIDS and FEP Memory Survey Proposal Updates • Additional acceleration will be monitored [see 2012 ITRS Update Proposals]
– FEP and Design and System Drivers Logic Monitor• Monitor MPU and Leading Edge Logic technology trends [2012 Proposals for 2013 ITRS]
– A&P/Design Power (Thermal) Model [2012 proposals for 2013 ITRS]• Possible proposals for Power Dissipation "hot spot" model rather than chip area basis
– PIDS/Design Max On-chip Frequency vs Intrinsic Modeling• Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010
plus 4% CAGR trend)• TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from
unchanged 2011 13% trend (supported past 8% Design Frequency trend)]• PIDS Updates include MASTAR static modeling near-term and TCAD dynamic
long-term modeling• Also “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional
scaling; timing to include IRC proposal for “Leading Co.” driver timing– YE Defect Density Modeling
• New ORTC Defect Density model work moved to 2012 Update due to loss of modeling resources [2012 proposals for 2013 ITRS]
6
More than Moore: DiversificationM
ore
Mo
ore
: M
inia
turi
zati
on
Combining SoC and SiP: Higher Value SystemsBa
se
lin
e C
MO
S:
CP
U,
Me
mo
ry,
Lo
gic
BiochipsSensors
Actuators[e.g. MEMS]
HVPower
Analog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Source: 2011 ITRS - Exec. Summary Fig. 4
Figure 4 The Concept of Moore’s Law and More
7
More Poly Dense Lines added in 2010 ITRS Update[Note: The ITRS does not utilize any single-product “node” designation reference; Flash Poly and DRAM M1 half-pitch are still Lithography drivers; however, other product technology trends may be drivers on individual TWG tables]
Source: 2011 ITRS - Exec. Summary Fig. 1
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
32-64 Lines
Poly Pitch
Exec. Summary - Figure 1 Definition of Half-Pitch
Work in Progress - Do Not Publish8
Months
0-24
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
Proposal: First 1-2 Companies
Reaching
Combined Production
(work in Progress) 2
20
200
2K
20K
200K
AdditionalLead-time:ERD/ERM
Research andPIDS Transfer
Volum
e (Wafers/M
onth)
Source: 2009 ITRS - Exec. Summary Fig. 2a
Figure 2a- (within an established wafer generation*)- *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also- Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production “Ramp Curves”
Production Ramp-up Model and Technology/Cycle Timing
Proposal *For 2012 Update Note:Fewer leadingIDM Companies Requires Adaption of DefinitionTo allow oneIDM CompanyOr a Foundry RepresentingMany Fabless CompaniesTo Lead aTechnology Production Ramp Timing
*Proposal Note:Leadership company First Manu-facturing could set more aggressive first production target, since “fast followers” may trail 1-3 years
9
Months
Alpha
Tool
Development Production
Beta
Tool
Product
Tool
Vol
ume
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200KResearch
-72 0 24-48 -24-96
Transfer to PIDS/FEP(96-72moLeadtime)
First Tech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021Hi-Channel
Example:
1st 2 Co’s
Reach
Product
First Tech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
Hi-Channel Proposal - for 2013 ITRS work
Source: 2011 ITRS - Exec. Summary Fig. 2b; plus:
Figure 2b A Typical Technology Production “Ramp” Curve for ERD/ERM Research and PIDS Transfer timing - including an example for III/V Hi-Mobility Channel Technology Timing Scenario
- Acceleration to 2015 Scenario for the 2012 Update work
[http://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option ]
ITRS Near Term(2011 – 2019)
ITRS Long Term(2019 – 2025)
Work in Progress - Do Not Publish
2009 ITWG Table Timing: 2007 2010 2013 2016 2019
68nm 45nm 32nm 22nm 16nm2011 IS ITRS DRAM M1 :
2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm/28” “22/20nm” “16/14nm” “11/10nm” “8/7nm”
2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 22nm 15nm 11nm2011 IS ITRS Flash Poly : 54nm
Source: Proposal 2011 ITRS - Executive Summary Fig tbd
450mm Production Ramp-up Model 2012 ITRS Proposal[ Modified from 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Versus “Node” vs. actual contacted M1 and un-contacted Poly Half-Pitch alignment
[ 7/27 Note for 450mm Special Topic:Need Consortium Development and Demonstration Update and Silicon Consumption model in light of latest Consortium plans… ]
[Backup]
*Note: At ITRS/USA, the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Roadmap guidance; based onguidance from SEMATECH suggestions for modification and commentary in an Executive Summary Topic.
Vo
lum
e
Years
Alpha
Tool
Beta
ToolSilicon is supporting development using partially-patterned and processed test wafers --IDM & Foundry -
Pilot Lines
Manufacturing
Demonstrations focus on 1xnm M1 half-pitch capable tools
Development Production
Increasing450mm Silicon Demand
From Demonstrations
Beta
Tool
Production
Tool
<--------------------- Consortium --------------------------
2012 ITRS 450mm Production Ramp-up Model[Modified from 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Demonstration
2010
2011
2012
2015
2016
2013
2014
202111.3nm
“1x nm”
10
2012MPU =DRAM
2013/14 MPU <DRAM
2015 onM1: 2-yrCycle?
2017 onM1: 2-yrCycle?
Proposal for consideration in 2012 ITRS Update work for Proposals for
2013 ITRS Kickoff Hsinchu Dec, 2012: continue to extend
M1:on 2-yrCycle through 2017/13nm (“8/7nm”
“node”)?
11
[See Litho Inchon December Public ITRS acrobatFoil #4,5]
Work in Progress - Do Not Publish12
Year of Production 2019 2020 2021 2022 2023 2024 2025 2026Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 10.9 10.0 8.9 8.0 8.0 8.0 8.0 8.0DRAM ½ Pitch (nm) (contacted)[1,2] 14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0
MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 6.79 5.87
MPU High-Performance Physical Gate Length (GLph) (nm)[1] 11.7 10.6 9.7 8.9 8.1 7.4 6.6 5.9
ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 6.8 5.8ASIC/Low Operating Power Physical Gate Length (nm)[1] 11.9 10.8 9.8 8.9 8.1 7.3 6.5 5.8ASIC/Low Standby Power Physical Gate Length (nm)[1] 12.7 11.4 10.2 9.2 8.2 7.4 6.6 5.9MPU High-Performance Etch Ratio GLpr/GLph [1] 1.2013 1.1725 1.1444 1.1169 1.0901 1.0640 1.0315 1.0000MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.1766 1.1558 1.1352 1.1151 1.0953 1.0759 1.0372 1.0000
Long-term Years
Table ORTC-1 ITRS Technology Trend Targets
Year of Production 2011 2012 2013 2014 2015 2016 2017 2018Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 22 20 18 17 15 14.2 13.0 11.9DRAM ½ Pitch (nm) (contacted)[1,2] 36 32 28 25 23 20.0 17.9 15.9MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 38 32 27 24 21 18.9 16.9 15.0
MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 35 31 28 25 22 19.8 17.7 15.7
MPU High-Performance Physical Gate Length (GLph) (nm)[1] 24 22 20 18 17 15.3 14.0 12.8
ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 41 35 31 25 22 19.8 17.7 15.7ASIC/Low Operating Power Physical Gate Length (nm)[1] 26 24 21 19.4 17.6 16.0 14.5 13.1ASIC/Low Standby Power Physical Gate Length (nm)[1] 30 27 24 22 20 17.5 15.7 14.1MPU High-Performance Etch Ratio GLpr/GLph [1] 1.4589 1.4239 1.3898 1.3564 1.3239 1.2921 1.2611 1.2309MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.5599 1.4972 1.4706 1.2869 1.2640 1.2416 1.2196 1.1979
Near-term Years
2011 ORTC Table 1 [Unchanged for 2012 Update; tbd 2013 ITRS Renewal]
450mm Production Target : 2015-2016
‘11 ITRS EUV Intro:DRAM&Flash: 2013MPU: 2015
MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0”
2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021 2023 2025
2-year “Node” Cycle (@ 0.7071/2yrs = 0.8409/yr
2011 ITRS M1 2yr cyc(nm): 76 65 54 45 38 32 27 22.5 19 16 13.4 11.25 9.5 8.0 6.7 5.6 4.73 4.0 3.34
2011 ITRS M1 3yr cyc (nm): 76 65 54 45 38 32 26.8 23.8 21.2 18.9 16 .9 15.0 13.4 11.9 10.6 9.5 8.43 7.5 6.69 ??
13
2011 ITRS Figure 11 – ORTC Table 1 Graphical Trends – Memory Half Pitch[With 2011 Flash 3D Scenario Overlay]
Source: 2011 ITRS - Executive Summary Fig 3
UNCHANGEDHowever,
FOR 2012 CTSGWORK: DRAM
4f2/’14; 3D Flash2016/’16 Layers
@ 48nm – op. C ?
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nan
om
eter
s (1
e-9)
Year of Production
2011 ITRS - Technology Trends
2011 ITRS Flash ½ Pitch (nm) (un-contacted Poly) -[2-yr cycle to 2009; then 8-yr cycle to 2020; then 3-yr cycle to 2022/8nm; then flat]
2011 ITRS DRAM ½ Pitch (nm) (Contacted M1) -[2.5-yr cycle to 2008; 45nm pull-in to 2009; then 3-yr cycle to 2026]
2011 ITRS: 2011-2026
3D - 8 layers
3D - 128 layers
PIDS 3DFlash :
Looser Polyhalf-pitch
2016-18/32;Then
2019-21/28nmThen
2022-25/24nmThen
2025-26/18nm ~5.5-yr Cycle
Long-Term ’19-’26
16nm
3D -16layers/48nm?
3D -256layers/24nm?4-yr cycle?
5.5-yr cycle
14
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nan
om
eter
s (1
e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term ’19-’26
16nm
2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
UNCHANGEDFOR 2012 CTSG
WORK; butProposals to
be Considered
15
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nan
om
eter
s (1
e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term ’19-’26
16nm
2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
Flash Trends
DRAM Trends
UNCHANGEDFOR 2012 CTSG
WORK; butProposals to
be Considered
[ MPUvs. Memory ]
16
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nan
om
eter
s (1
e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term ’19-’26
16nm
2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
Flash Trends
DRAM Trends
?
2012 ITRS Work:“22nm” (ITRS 2011 Planar M1=38nm ; GL=24nm)
MugFET M1=??nm; 3D Physical Gate Length = ??nm?
2-yearM1 pace
extension to
2017 ; then 3yrs
again
2012 ITRS Work Consider: “7nm” pull-in to 2017 (ITRS 2011 Planar M1=14nm);2019 ITRS GLph = 11.7nm unchanged; except for
MugFET M1=??nm; 3D and FDSOI Physical Gate Length = ??nm?Logic and Flash (3yr cycle) both drive Lithography after 2017; Logic M1 after 2022?
MuG-FET
FDSOI
2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and III/V Ge acceleration for 2012 ITRS Update work
Metal
High kGate-stack material
2009 2012 2015 2018 2021
Bulk
FDSOI
Multi-gate(on bulk or SOI)Structure
(electrostatic control)
Channelmaterial
Metal
High k
2nd generation
Si + Stress
S D
High-µ InGaAs; Ge
S D
PDSOI
Metal
High k
nth generation
PossibleDelay
Possible Pull -in
17
68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :
2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16/14nm” “11/10nm” “8/7nm”
2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm
2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 11nm2011 ITRS Flash Poly : 54nm2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021
Proposals - for 2013 ITRS preparation
22-248nm
20248nm
22nm 15nm
11nm
Source: 2011 ITRS - Executive Summary Fig 5
*Proposal Note:Leadership company First Manu-facturingcould set more Aggressive first production target, since “fast followers” may trail 1-3 years
With 2012 ITRS IRC Guidance Update Proposal Note*:
[ PIDS/FEP/DesignHP/LOP/LSTP
Sub-Team Transistor
Modeling Work Underway ]
450mm1st Production
Source: 2011 ITRS - Executive Summary Fig 5
2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and III/V Ge acceleration for 2012 ITRS Update work
Metal
High kGate-stack material
2009 2012 2015 2018 2021
Bulk
FDSOI
Multi-gate(on bulk or SOI)Structure
(electrostatic control)
Channelmaterial
Metal
High k
2nd generation
Si + Stress
S D
High-µ InGaAs; Ge
S D
PDSOI
Metal
High k
nth generation
PossibleDelay
Possible Pull -in
18
68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :
2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16nm/14nm” “11/10nm” “8/7nm”
2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm
2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 11nm2011 ITRS Flash Poly : 54nm2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021
Proposals - for 2013 ITRS preparation
22-248nm
20248nm
22nm 15nm
11nm
Proposal - for 2013 ITRS prep.
2012MPU =DRAM
2015 onM1 2-yrCycle?
2013-14 MPU <DRAM
2017 onM1 2-yrCycle?
FDSOI MugFET pull-in to “14nm”/2014?
Multiple companies with Bulk MugFET pull-in to “14nm”/2014?
*Proposal Note:Leadership company First Manu-facturingcould set more Aggressive first production target, since “fast followers” may trail 1-3 years
19
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025 2030
Nan
om
eter
s (1
e-9)
Year of Production
2011 ITRS - Technology Trends
2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]
2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]
2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]
2011 ITRS: 2011-2026
Long-Term ’19-’26
16nm
2011 ITRS Figure 4 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
Source: 2011 ITRS - Executive Summary Fig 4
2009/2010 ITRS Unchanged (except extend to new end period): 2011 ITRS: 2011-2026; also includes 2012 Update “Equivalent Scaling” Proposals
Equiv. ScalingGate Length
Trade-off
Strain
HK/MG
MuG-FET
Hi-u,(tbd)
ITRS 1999P. Gargini
“EquivalentScaling”Concept
FDSOI
PDSOI
2011ITRS:
Extend M1;
& GLpr;to 2026
on3-yearCycle
GLph
versus M
1 in 2026
- analyzing
implic
ations
1995->2015“Nodes”
“360-11(10)”
ITRS M1 hp303-21nm
ITRS GLph‘95-’99-’03-’15360nm-90nm90nm-45nm45nm-17nm
Gate Length +
“EquivalentScaling”
=Power &
Performance
Half-Pitch +
“Design Factor”Scaling
[6t SRAM = 60f2;
4t Logic =175f2]
Enables“Moore’s
Law”
Functions/chip
Also III/V; Ge from 2019 -> 2015?
Proposal for 2013 ITRSPreparation Work
MugFET from 2015 -> 2011;Proposal for 2012 ITRS
Work for 2013 ITRS prep.
Updated “Equivalent Scaling” Proposal - for 2012 work
450mm 2015-16
MPU:EUVIntro.2015
ERD/ERM : What is Next?Optical interconnect?
Carbon NanoTubes/Graphene?; MRAM?; Quantum Dots Memory?
Half-Pitch +
“Design Factors”
Xf2=
“Moore’s Law”
?
2012 ITRS Work:“22nm” (ITRS 2011 Planar M1=38nm ; GL=24nm)
MugFET M1=??nm; 3D Physical Gate Length = ??nm?
2-year “Node” Cycle (@ 0.7071/2yrs = 0.8409/yr
2-yearM1 pace
extension to
2017 ; then 3yrs
again
20
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1995 2000 2005 2010 2015 2020 2025 2030
Sq
uar
e M
illi
met
ers
Year of Production
2011 ITRS - Function Size
2009 DRAM Cell area per bit (1 bits/cell) (um2)
2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)
2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)
2009 Flash MLC Ave area per bit (3 bits/cell) [SLC cell area/3] (um2)
2009 Flash MLC Ave area per bit (4 bits/cell) [SLC cell area/4] (um2)
2011 SRAM Cell (6-transistor) Area (um2)
2011 Logic Gate (4-transistor) Area (um2)
Long-Term ’19-’26
2011 ITRS: 2011-2026
PIDS NAND Flash Multi-Layer 3D Model
Plus “Slower” Dimensional Reduction Rate Trend Tradeoff
2011 ORTC Figure 6Product* Function Size Trends; plus
[transistor + capacitor]
Source: 2011 ITRS - Executive Summary Fig 6
Updated04/23/12
FOR 2012 CTSGWORKMPU/ASIC
AlignmentDesign TWG
Actual SRAM [60f2]& Logic Gate [175f2]
DRAM4f2
AddedWAS:Begin in
2011IS: DelayedTo 2013 ‘14
Flash [4f2]1) 2-yr CycleExtended to 2010;2) 3 bits/cell added2009-2011[and extended to 2026 in the 2011 ITRS];3) 4 bits/cell movedfrom 2012 [to 2021 in the 2011 ITRS]
3D - 8 layers
3D - 128 layers
3D -16layers/48nm?
3D -256layers/24nm?
4-yr cycle?
5.5-yr cycle
Flash Impact of:
Vs:
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
1995 2000 2005 2010 2015 2020 2025 2030
Gig
abit
s (1
e9)
and
Sq
uar
e M
illi
met
ers
Year of Production
2009 ITRS - Functions/chip and Chip Size
2011 ITRS DRAM Functions per chip (Gbits)
2011 ITRS Flash (Gbits) SLC [2-year cycle]
2011 ITRS Functions per chip (Gbits) MLC (2 bits/cell)
2011 ITRS Functions per chip (Gbits) MLC (3 bits/cell)
2011 Functions per chip (Gbits) MLC (4 bits/cell)
2011 Flash Chip size at production (mm2)
2011 DRAM Chip size at production (mm2)
Flash"Hwang's
Law"~ 2x/1yr
Flash~ 2x/3yrs
Flash MLCExceeds1Tera-bit
Average "Moore's Law" = 2x/2yrs
<160mm2(18 x 9)
<30mm2(8 x 4)
DRAM~ 2x/2.5yrs
Flash~ 2x/1.25yrs
Long-Term ’19-’26
2011 ITRS: 2011-2026
2011
21
Figure 7 2011 ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends
Source: 2011 ITRS - Executive Summary Fig 7
4Tbits Possible with PIDS NAND Flash Multi-Layer
3D Model Scenario Option3D - 128 layers/ ‘25
2025/32nm/3bits/cell4Tbits =128x33Gbits
2025/18nm/3bits/cell13Tbits =128x99Gbits
DRAM4f2
AddedWAS:Begin in
2013IS: DelayedTo 2013 ‘14
22
10
100
1000
10000
100000
1000000
10000000
1995 2000 2005 2010 2015 2020 2025 2030
Mil
lio
n T
ran
sist
ors
(1e
6) a
nd
Sq
uar
e M
illi
met
ers
Year of Production
2011 ITRS - Functions/chip and Chip Size
2011 ITRS Cost-Performance MPU Functions per chip at production (Mtransistorst)
2011 ITRS High-Performance MPU Functions per chip at production (Mtransistors)
2011 Cost-Performance MPU Chip size at production (mm2)
2011 High-Performance MPU Chip size at production (mm2)
<260mm2
<140mm2
MPU= 2x/3yrsMPU
= 2x/2yrs
Average "Moore's Law"
= 2x/2yrs
Long-Term ’19-’26
2011 ITRS: 2011-2026
2011ITRS:
Unchanged, but Extend ed
Transistors/chip& Chip Size
Modelsto 2026
On 3-yearCycle
MPU/hpASICM1 Technology Cycle and MPUTransistors/chip
areOn 3-year
Cycle after 2013
vs.Average
2-yearHistorical
Moore’s Law
“22nm”/(38nm M1)MPU Model Generations
Figure 8 2011 ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged from 2009, except extended to 2026]
Source: 2011 ITRS - Executive Summary Fig 8
2012 Unchanged- Must evaluate
Impact of04/23/12
ProposalsFOR 2012 IRC &
CTSG ConsensusWork
for 2013 ITRSConsideration
Backup for IRC and ITWG Plenary1. (23-26) Litho Mask Count (3 Foils)
2. (27-29) 4% Design/PIDS Frequency vs. PIDS 8% 1/(CV/I) Proposal
3. (30) MOS Transistor Scaling and Scaling Calculator
4. (31) SICAS Capacity analysis update
5. (32,33) DRAM Functions/Chip 2009 ITRS vs. 2011 ITRS (2 foils)
6. (34) Planar Transistor Diagram
7. (35) Interconnect with Flash M1 Diagram
8. (36) 2008 Consortium FinFET IEDM Paper Analysis
9. (37) Wikipedia Tri-Gate references
23
ORTC Table 5 Update: Litho TWG model for Mask Count – MPU survey-based, mask counts peak 2014/(54 masks peak) EUV
expected 2015 – DRAM referenced to MPU, mask counts peak 2012/(41 masks peak)
EUV expected 2013 – Flash survey-based, mask counts peak 2012/(43 masks peak) EUV
expected 2013 – Sidewall image transfer technology IEDM papers should be evaluated– Table 5 also includes NEW IC Knowledge (ICK)
www.icknowledge.com modeled comparison targeting ITRS 2011 Litho EUV timing; but extended out through 2024 using 2009-10 ITRS (www.itrs.net ) assumptions
– Limited YE Defect Density modeling resources requires delay of update response to 2012 ITRS Update work
24
25
Fig 7a - Litho 2011 Survey vs ICK 2011 ITRS-based* Model[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
SEMATECHSurvey
EUV timing:MPU
in 2015;
DRAM& Flash in
2013
Lit
ho
Mas
k C
ou
nt
by P
rod
uct
Cat
ego
ry
Actual < - > Forecast
Source: 2011 ITRS - Executive Summary Fig. 7a
450mm 2015-2016
ICKITRS-basedv2001MPU
300mm/”32nmNode”
59-54nm M1
2008-0951-52Masks
26
Fig. 7b - Litho 2011 Survey vs ICK 2011 ITRS-based* Model (cont.)[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
ICK Strategic Model*
*Based onITRS
2009-10 editions
EUV timing:MPU
in 2015;
DRAM & Flash EUV in
2013
Flash Charge Trap
in 2012;Multi-layer 3D begins
2016
MPU Delay EUV to
2017
Lit
ho
Mas
k C
ou
nt
by P
rod
uct
Cat
ego
ry
Actual < - > Forecast
Source: 2011 ITRS - Executive Summary Fig. 7b
450mm 2015-2016
ICKITRS-basedv2001MPU
300mm/”32nmNode”
59-54nm M1
2008-0951-52Masks
ORTC Table 4: Design TWG Model for On-Chip Frequency – Lower model starting point 2010/3.6Ghz– 4% growth rate through 2026– *Unchanged 2011 ITRS 13% PIDS target
model Intrinsic Transistor Frequency Growth;– *However, proposal for 2012 ITRS 8% PIDS
target model Intrinsic Transistor Growth (work preparation in 2011)
27
Table ORTC-4 Performance and Packaged Chips Trends
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026Chip Frequency (MHz)
WAS On-chip local clock [2] 5.454 5.875 6.329 6.817 7.344 7.911 8.522 9.180 9.889 10.652 11.475 12.361 13.315 14.343 15.451 16.640 Design /
ISOn-chip local clock [2] 3.462 3.600 3.744 3.894 4.050 4.211 4.380 4.555 4.737 4.927 5.124 5.329 5.542 5.764 5.994 6.234 6.483 6.743
Ghz
Table FreqTopic tbd - 2011 Chip Frequency Model Trend vs.2009/2010 ITRS Frequency
Source: 2011 ITRS - Executive Summary Table tbd
28
Fig 8a - PIDS 2009/11 ITRS CV/I Trends vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
0.10
1.00
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRSC
V/I
(ps)
Year of Production Ramp
PIDS Table 2: CV/I – 2009-2011 ITRS Unchanged
100
1000
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRS
1/(
CV
/I )(
Gh
z)
Year of Production Ramp
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
1/(CV/I) (Ghz) ~ ~ 13%CAGR
PIDS 2012 FDSOI Scenario:‘15/294 – ’26/686 @8.0% CAGR
2011 ITRS2011 - 2026
PIDS 2011 ITRS Table:1/(CV/I) (Ghz) =‘11/156 – ‘26/1000 @ ~ 13% CAGR
‘11/ 313 – ’26/686 @ 5.4% CAGR – MugFET Trend
[2012 Proposal: MugFET 4-year Leading Co. pull-in]
PIDS 2011 ITRS Table:CV/I) (ps) =‘11/0.64 – ‘26/0.10 @ ~ -12% CAGR
‘11/ 0.319 – ’26/0.146 @ - 4.8% CAGR – MugFET Trend
[2012 Proposal: MugFET 4-year Leading Co. pull-in]
CV/I (ps) ~~ -12%CAGR
PIDS 2012 FDSOI Scenario:‘15/0.340 - ’26/0.146-7.4% CAGR
Figure 8a 2012 Update Model Trend versus 2009/2011 ITRS PIDS TWG Transistor Intrinsic Frequency (1/(CV/I)) Performance Trends
Source: 2011 ITRS - Executive Summary Fig. 8a
29
Fig. 8b - ORTC Table 4:On Chip Local Clock Frequency Trend Comparisons to PIDS
vs. 2012 ITRS MUG-FET 4-year Pull-In and Lower Intrinsic Freq. Trend Proposals
Figure 8b Design On-Chip Frequency vs. PIDS Intrinsic Transistor and Ring Oscillator Model Frequency
2011 ITRS2011 - 2026
Source: ITRS Test TWG compilation, ca 4Q 2010; 2011 ITRS PIDS, Design TWGs
2012 Update Scenario:FDSOI
at 8% CAGR
ORTC Table 4:On-Chip Local Clock Frequency:
2011 Design TWG trend:at 4% CAGR
2009/11 PIDS/FEPRing Oscillator Model
101 invertor stagesWith equivalent Fan-out 4
Capacitance load; Results in Frequency of
~ 1/22 x 1/(CV/I)at ~13% CAGR
DesignH’room
~ 1/22
2009/11 ITRS PIDS/FEPIntrinsic Transistor Frequency
1/(CV/I) at 13% CAGR
2007 Des TWG Actual History of Average On-Chip
1999 - 20071Ghz – 4.9Ghz~22% CAGR
On-Chip Clock Frequency:Performance Improvement tradeoffs between dimensional EOT and Gate Lengthwith “Equivalent Scaling,” both process-related(ie Strain, FDSOI, MugFET, III/V Ge, etc);and also Including design-related tradeoffs:
-Multi-Core Architecture-Memory Architecture-Software Power Management-etc.]
1Thz
2012 Update Scenario: MugFET : 4yr Pull-in 1/(CV/I) to 2011; then 5% CAGR
2012 Update Scenario: MugFET
at 5% CAGR
2012 Update Scenario – FDSOI:Beginning 2015 at 8% CAGR
Co.A Actual
Co.B Actual
Co.C Actual
Source: 2011 ITRS - Executive Summary Fig 8b
Work in Progress - Do Not Publish30
MOS Transistor Scaling(1974 to present)
S=0.7[0.5x per 2 nodes]
Pitch Gate
[0.5x per 2 Technology Cycles]
MOS Transistor ScalingMOS Transistor Scaling(1974 to present)
S=0.7[0.5x per 2 nodes]
Pitch Gate
[0.5x per 2 Technology Cycles]
MOS Transistor Scaling(1974 to present)
S=0.7[0.5x per 2 nodes]
Pitch Gate
[0.5x per 2 Technology Cycles]
MOS Transistor Scaling
Figure 10 MOS Transistor Scaling—1974 to present
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
Cycle T ime
Cycle T ime:
(DRAM M1 Example)
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
Cycle T ime
Cycle T ime:
(DRAM M1 Example)
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
Cycle T ime
Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
Cycle T ime
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
Cycle T ime
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
0.5x
0.7x 0.7x
0.5x
0.7x0.7x 0.7x0.7x
N N+1 N+2N N+1 N+2
Node Cycle T ime (T yrs):
*CARR(T) =
[(0.5) (̂1/ 2T yrs)] - 1
CARR(3 yrs) = - 10.9%
CARR(2 yrs) = - 15.9%
* CARR(T) = Compound Annual Reduct ion Rate
(@ cycle t ime per iod, T )
Log
Hal
f-P
itch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrsL
og H
alf-
Pit
ch
Linear Time
1994 NTRS -.7x/3yrs
Actual -.7x/2yrs
Scaling Calculator +Node Cycle T ime:
N-1 N N+1N-1 N N+1
Cycle T ime
Cycle T ime:
(DRAM M1 Example)
Figure 11 Scaling Calculator
Source: 2011 ITRS - Executive Summary ORTC Fig 1, 2
*Note: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of 1Q11. The detailed data are available to the public online at the SIA website, www.sia-online.org, and data is located at http://www.sia-online.org/industry-statistics/semiconductor-capacity-utilization-sicas-reports/
31
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 1Q data for 2011. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.
2.5-Year DRAM Cycle ; 2-year Cycle Flash and MPU
2010 2013
2-Year DRAM
Cycle
3-Year Cycle
Fea
ture
Siz
e (H
alf P
itch)
(m
)
Year
>0.7m
0.7-0.4m
0.4-0.3m
0.3- 0.2m
0.2- 0.16m
0.16-0.12m
0.08-0.06m
0.12-0.08m
0.2- 0.12m
0.4-0.2m
<0.06m
W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS
0.01
0.1
1
10
200620052004
W.P.C.
2000
W.P.C.
2001
W.P.C.
2002
W.P.C.
2003
W.P.C. W.P.C.
2007 2008 2009
W.P.C. W.P.C. W.P.C. W.P.C. W.P.C.
2010 2011
W.P.C.
1998 2015
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09/11 ITRS DRAM Contacted M1 Half-Pitch Target = 2009/11 ITRS Flash Un-contacted Poly Half Pitch Target = 2009/11 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
4-Year Cycle for Flash after2010 Flash pull-in;
MPU 3-yr cycle after 20133-yr cycle for DRAM after pull-in
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
Source: 2011 ITRS - Exec. Summary Fig. 3
Work in Progress – Do Not Publish!32
Flash (NAND) Product Size Generations
2009 ITRS Renewal:
PIDS Flash Size: 2007 2011 2016 2020
2007 ??? ??? ??? ???
4x/4-5yrs WAS'09 16G 64G 256G 1T
Interim Generations: 2009 2014 2018 2022
??? 2007 ??? ??? ??? ???
4x/4-5yrs WAS'09 32G 128G 512G 2T
5yrs 4yrs 4yrs
2011 ITRS Renewal (PIDS 2010 Update Proposal):
PIDS Flash Size: 2007 2010 2011 2014 2016 2019 2020
4x/4-5yrs WAS'09 16G 64G 256G 1T
4x/4-5yrs IS'11 64G 256G 1T
Interim Generations: 2008 2009 2012 2014 2017 2018 2021 2022 2026
4x/4-5yrs WAS'09 32G 128G 512G 2T n/a
4x/4-5yrs IS'11 32G 128G 512G 2T 2T
4yrs 5yrs 4yrs ??yrs
Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/2022-26
Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G
128Gbit chip will be available in 2012.
NAND Cell Array Efficiency unchanged from 56% in ITRS 2010
Work in Progress – Do Not Publish!33
DRAM Product Size Generations
2009/10 ITRS Renewal:
PIDS DRAM Size: 2010 2011 2016 2017 2022 2023
4x/6yrs 2007 4G 16G 64G
WAS'09/10 4G 16G 64G
Interim Generations: 2008 2013 2014 2019 2020
4x/5-6yrs 2007 2G 8G 32G
4x/6yrs WAS'09/10 2G 8G 32G
5yrs 6yrs
2011 ITRS Renewal (PIDS 2010 Update Proposal):
PIDS DRAM Size: 2011 2017 2018 2023 2025
4x/6yrs WAS'09/10 4G 16G 64G n/a
4x/7yrs IS'11 4G 16G 64G
Interim Generations: 2008 2014 2020
4x/6yrs WAS'09/10 2G 8G 32G
4x/6yrs IS'11 2G 8G 32G
6yrs 6yrs 7yrs?
DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026
DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025
DRAM Cell size factor: 4F2 cell will be available in 2013. Delay 2years from ITRS2009/10
DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010
Work in Progress - Do Not Publish 34
2012 ITRS Definition Work – Need Clarification of the M1 Half Pitch To clarify the ORTC Table 1 relationship to Gate Length*
And for consistency with Interconnect TWG Transistor M1 contacted half-pitch [and public - sometimes presented (IEDM, etc) as “Transistor Pitch” or
“Gate Pitch”] ; *vs. Printed Gate Length (GLpr) (sometimes also known as “CD” or Critical Dimension); and finally the publically-measurable Physical Gate Length, (GLph)
[Note: The ITRS does not utilize any single-product “node” designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology trends may be drivers on
individual TWG tables]
Contacted Contacted M1 Half-Pitch vs. M1 Half-Pitch vs.
0.5 x 0.5 x “Transistor or Gate Pitch?”“Transistor or Gate Pitch?”
[>M1 h-p?][>M1 h-p?][GLpr][GLpr]
[GLph][GLph]
ContactContact
Width Width
Metal 1 Pitch [Interconnect TWG Example; Dec’10
= 2x M1 Half-Pitch]
Metal 1 half-pitch = 0.5 x M1 Pitch]
Other ITRS MPU Model Consideration:
[SRAM (6-transistor) Cell Area = 60f2 =
60 x (M1 h-p)^2]
32 nm”/56.25nm h-p, 0.171 um2 [= 62.0 x 0.05625^2]
[IDF 2009]
MPU Cross-Section
Dielectric Capping
LayerCopper
Conductor with
Barrier / Nucleation
Layer
Pre-Metal Dielectric
Tungsten Contact
Plug
Inter-Mediate(=M1x1)
Inter-Mediate(=M1x1)
Metal 1Metal 1
Passivation
DielectricEtch Stop Layer
ASIC Cross-Section
Semi-Global (=M1x2)
Semi-Global (=M1x2)
Metal 1 Pitch
Via
Wire
Via
Wire
Via
Wire
Metal 1 Pitch
Global (=IMx1.5~2µm)Global (=IMx1.5~2µm)
Inter-Mediate(=M1x1)
Inter-Mediate(=M1x1)
Metal 1Metal 1
Global (=IMx1.5~2µm)
Global (=IMx1.5~2µm)
1) MPU: Revised hierarchy2) ASIC: No drastic change, however semi-global should be kept at 2 x
M1 3) Flash: The new technology driver for M1
2011 Interconnect TWG -Hierarchical Cross Sections
Flash Cross-Section
Metal 3
Metal 0Metal 1
Metal 2
Poly Pitch
Metal 1 Pitch
36
2008 Consortium FinFET Design Factor = 42? vs. ITRS = 60 for planar SRAM 2009 60x0.05351u^2 = 171.8u2; also 60 for planar SRAM 2011 60x0.03784u^2 = 85.9u2and vs. actual IDF’09 54 @ 56.25nm/”32nm” 0.171u2 area;and calc. from .092u2 area IDF’09: 58 @ 39.78nm/”22nm” :
Source : http://www.eetasia.com/ART_8800557135_480100_NT_77e3414c.HTM :“…announced Dec. 16 at the 2008 International Electron Devices Meeting [IEDM] in San Francisco, California…”
I. Researchers from the three companies [AMD, IBM, Toshiba] fabricated a highly scaled FinFET SRAM cell using HKMG. 1) It is the smallest non-planar-FET SRAM cell yet achieved: At 0.128µm², a. the integrated cell is more than 50 percent smaller than the 0.274µm² non-planar-FET cell previously reported. b. To achieve this goal, the team optimized the processes, especially for depositing and removing materials, c. including HKMG from vertical surfaces of the non-planar FinFET structure.
II. The researchers also investigated the stochastic variation of FinFET properties within the highly scaled SRAM cells and simulated SRAM cell variations at an even smaller cell size. 2) They verified that FinFETs without channel doping improved transistor characteristic variability by more than 28 percent. a. In simulations of SRAM cells of 0.063µm² area, equivalent to or beyond the cell scaling for the 22nm node, b. the results confirmed that the FinFET SRAM cell is expected to offer a significant advantage in stable operation c. compared with a planar-FET SRAM cell at this generation
2008IEDM:110nmPitch55nmHalf-Pitch
“32 nm”/55nm h-p, 0.128 um2 [= 42.3 x 0.055^2]
[IEDM 2008]
“22 nm”/38.9nm h-p, 0.063 um2 [= 41.6 x 0.028^2]
[Simulation ca. 2008]
ITRS MPU Model :[SRAM (6-transistor) Cell Area
= 60f2 = 60 x (M1 h-p)^2]
vs. actual “32 nm”/56.25nm h-p, 0.171 um2 [= 54.0 x 0.05625^2]
[ca. 2009]
4x20
= 8
0nm
Eq.GLph=
???nm !?
http://www.slideshare.net/finance6/intel-pdf-32nm-technology-update-mark-bohrhttp://download.intel.com/pressroom/kits/events/idffall_2009/pdfs/IDF_MBohr_Briefing.pdf
Work in Progress - Do Not Publish37
http://en.wikipedia.org/wiki/Tri-gate_transistors_(Intel)#Tri-gate_transistors_.28Intel.29 http://arstechnica.com/business/news/2011/05/intel-re-invents-the-microchip.ars/2
^ "Intel Reinvents Transistors Using New 3-D Structure". Intel. http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors-using-new-3-d-structure. Retrieved 5/4/2011.
- http://newsroom.intel.com/docs/DOC-2032 ^ a b "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. http://arstechnica.com/business/news/2011/05/intel-re-invents-the-microchip.ars. Retrieved 7 May 2011