1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant

1

N/P-Channel MOSFET Fabrication

By

Assoc. Prof Dr. Uda Hashim

School of Microelectronic Enginnering

KUKUM

FOX FOX

N-Well N-Well

Arsenic ImplantLDD

As+ S/D ImplantP-Well

NMOSPMOSCapacitor

FOX FOX

BF2 S/D Implant

BPSG

AlSiCu

Planarisation

Metal 2Passivation

P+ Substrate

Spacer

Test InsertandScribe-line

2

Overview

• Integrated Circuit Manufacturing Process

• Mask Design and Layout

• Main Fabrication Process

• Transistor Fabrication Step by Step

• Electrical Characterization and Testing

• Fabrication Documents (Runcard) Preparation

3

The making of transistor

• Circuit design

• Mask/layout design

• Mask making and artwork

• Fabrication process

• Device testing – for parametric and functional test

• Packaging and Reliability Test

4

Step 1: Logic Design

5

Step 2: Circuit Design

6

Step 3: Layout Design

7

Mask Making and Artwork

8

Fabrication Process

9

Step 11: Wafer Probe, Scribe & dice

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Step 12: Die Attach, Wire Bonding, & Encapsulation

11

Step 13: Final Test

12

Mask Design

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MOSFET Masking Step

• Mask 1: Source Drain Mask

• Mask 2: Gate Mask

• Mask 3: Contact mask

• Mask 4: Metallization Mask

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Introduction• Mask design is very important before fabrication

process can be done.• Design rules must be followed to prevent defect in

the process.• In this design, gate length is varied from 30um,

50um, 100um, 150um, 200um and 300um.• Different gate length will have different gate mask

and different distance from source to drain.• The smaller the gate size, the better the transistor in

speed.

15

Circuit, layout and cross section of NMOS transistor

• In NMOS design, NMOS circuit is transferred to layout design.

• Then, mask can be design to fabricate NMOS transistor.

16

MASK 1: Source Drain Mask

• Mask 1 is used to control the heavily phosphorus doped and create the source and drain region of the n_channel device.

Layout 1: Source and Drain

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Mask 2: Gate Mask

• Mask 2 is used to remove the thick oxide layer and grow a very high quality of thin oxide.

Layout 2: Layout 1 and gate

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Mask 3: Contact mask

• Mask 3 is used to pattern the contact holes.

• Etching will open the holes.

Layout 3: Layout 2 and contact

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Mask 4: Metallization Mask• Mask 4 is used to pattern the

connection.• The uncovered Aluminum

film will be removed during etching process.

Layout 4: Layout 3 and metallization

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Mask Design(Step by Step)

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Photo Mask Preparation

• Apply AutoCAD to design the masks

• Transfer the pattern to high resolution printer

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Mask Design Step • Step 1: Set frame and wafer size dimension• Step 2: Design alignment mark • Step 3: Design source and drain mask

(Mask 1) block and duplicate to the whole wafer.

• Step 4: Design gate mask (Mask 2) block and duplicate to the whole wafer. Then, inverse the alignment

mark to change the polarity.

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• Step 5: Design contact mask (Mask 3) block and duplicate to the whole

wafer.

• Step 6: Design Metallization mask (Mask 4) block and duplicate to the whole

mask.

• Step 7: Print on transparency film using high resolution printer.

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Step 1: Set frame and wafer size dimension

• The frame size is set to 20” x 12” (A4 paper size).

• The wafer diameter is set to 4” and the wafer block is set to 6” x 6”.

• Then the design unit is set to millimeter or micron depend on the designer’s convenience.

25

Step 2: Alignment Mark design

• Alignment mark is used to align wafer between layer to layer during the fabrication process.

• First, design the alignment block.

• Then, design the cross an insert it inside the block.

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Step 3: Design source and drain mask• First, design the mask block.

• Then, design the source and drain region which is uncovered and designed with desired dimension.

• At this mask, the polarity of the alignment block is reversed. The cross is open and the block is opaque.

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Step 4: Design gate mask• The red block is the gate

mask, it is drawn before the white area.

• The white area on the red layer is the gate region.

• Maintain the mask design

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Step 5: Design contact mask • The brown block is the gate

mask.

• The white rectangle is the contact region.


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Step 6: Design metallization mask• The Metallization mask is

used for routing purposes.

• The unprotected region will be etched away whereby the exposed Aluminum area will be removed.


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Actual Transparency Masks

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Q & A

32

EQUIPMENTS

AND

CONSUMABLES

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Equipments

FABRICATION EQUIPMENTS PURPOSES 1. Dry/Wet Oxidation Furnace For wet and dry oxidation process2. N/P Dope Diffusion Furnace For n&p -type diffusion process3. Plasma Enhanced chemical Vapor Thin film Deposition (PECVD) Deposition4. Mask Aligner and Exposure System For mask and wafer alignment and

exposure5. Aluminium Evaporator Aluminium deposition 6. Hot Plate For dehydrate wafer7. Electrical Probe Station To conduct electrical test on wafer

level8. Micrometer For measuring wafer thickness9. Photoresist Spinner Photoresist deposition by spin-on10.Step Height Measurement System To measure the step height of

metal surface11.Low Power Optical Microscope To observe wafer during process

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EquipmentsFABRICATION EQUIPMENTS PURPOSES

12.Conduction Gauge To determine wafer carrier type13.CV Test Station To conduct capacitance and

voltage test14.Four Point Probe For measuring sheet resistance15. IV Test Station To measure the current and

voltage characteristics16.Diamond Scriber Marking lot number on wafer17.Spectrophotometer To measure thin film thickness18.Wet etch bench To perform wet chemical etching

– Buffered Etch Oxide (BOE) Tank– Aluminium Etchant Tank – Developer Tank – Spin Rinse Dryer

19.Wet process bench To perform wet cleaning process– Wet Bench Tank– Spin Rinse Dryer

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Consumables

CONSUMABLES PURPOSES 1. Hydrofluoric Acid Solution To remove native oxide

on silicon wafer2. Deionized Water For rinsing and cleaning

wafers3. Positive/Negative Photoresist Positive/Negative masking coating

layer4. Photoresist Developer To remove resist after exposure5. Buffered Etch Oxide For etching exposed and unwanted

oxide 6. Aluminium Etchant For etching aluminium 7. 100 mm, p-type, boron-doped As the starting material8. <100> silicon wafer9. Liquid/solid Phosphorus n-type diffusion source10.Liquid/solid Boron p-type diffusion source11.Transparencies As wafer mask

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MICRO FABRICATION CLEANROOM

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• Teaching fab

• Completed in December 2003

• The size of the cleanroom built is approximately 115m2

• Cleanliness class from ISO Class 5 to ISO Class 8.

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YELLOW ROOM (ISO CLASS 5)

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WHITE ROOM (ISO CLASS 6)

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CHARACTERIZATION ROOM (ISO CLASS 6)

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Oxidation Furnace ( WET / DRY)

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Diffusion Furnace ( n-type / p- type)

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Physical Vapor Deposition system

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Photolithography Module

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Wet Etching Module

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Wet Cleaning Module

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Wafer Test Module

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Wafer Characterization Module

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Scanning Electron Microscope Module

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E-beam Lithography Module

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Cleanroom Facilities

Gas Corridor

DI Water System

Scrubber System

Electrical Main Switch Board

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Main Fabrication Process

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Fabrication Process

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Pre-Oxidation Clean Cycle

• The SC-1 (RCA) clean is used to remove particles and organic materials by oxidizing the particle

• NH4OH : H2O2 : H2O with the ratio 1 : 4 : 50

• Temperature ~75 with 10 minutes ℃duration and rinse by DI water ~3 minutes

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SC-1 Clean Cycle System

SC-1 Clean Cycle System DI Water System

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Diffusion

• Junction Depth – Spreading Resistance

Measurement1100C 60min N2:O2=1:1 (100)

1

10

100

1000

10000

100000

1000000

-2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13

Distance (5um)

Sp

read

ing

res

ista

nce

(oh

m)

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Diffusion (cont.)• The relation among temperature, duration and

Junction Depth

00.5

11.5

22.5

33.5

1080 1100 1120 1140 1160 1180 1200 1220

temperature (C)

Juncti

on D

epth

(um

)

0

1

2

3

4

5

0 10 20 30 40 50 60 70

Time (minute)

Junc

tion

Dept

h (u

m)

60 minutes N2:O2 = 4:1 1200 N℃ 2:O2 = 4:1

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Diffusion (cont.)• Different structures have different junction

depth in the same condition 1100 60minutes N℃ 2:O2 = 1:1

0

0.5

1

1.5

2

2.5

111 100Structure

Junction D

epth

(um

)

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Diffusion (cont.)• Sheet Resistance

Vertical 4 point probe test

1

10

100

0 2 4 6 8 10 12

distance (cm)

Sh

ee

t R

esi

sta

nce

111

100

Horizontal 4 point probe

1

10

100

0 5 10

distance (cm)

Sheet

Resi

stance

111

100

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Diffusion impurities

• The material employed in a diffusion process is termed the diffusion source. Many types of materials can be applied as diffusion sources because the diffusion processes for the Si-base device have many distinct requirements. The impurities can be classified into two types for semiconductor manufacturing: "acceptor" and "donor". Acceptors can be adopted to form a "p-type" semiconductor, and donors can be applied to create an "n-type" semiconductor.

NMOS PMOS

http://www.ndl.org.tw/english/icfab/Process/07-Diffusion/m3-7-2.htm

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1.PR Coating

2.Wafer Spin

3.Soft Bake

4.Mask Align

8.Etching

7.Inspection

6.Develop

5.Exposure

Photolithography Flow

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Photolithographic

• Alignment – Contrast of Alignment Mark

• Exposure Bias – Inaccurate Critical

Dimension on Photo Masks

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Transistor Fabrication(Step by Step Process)

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n-channel MOSFET Fabrication

The device fabrication steps are shown for n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET). All photolithography processes are shown by means of animation. The steps shown here are the most detailed and serve as basis for the next few applets showing the device fabrication. A lightly doped p-type Si wafer

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For NMOS process, the starting material is a P-type lightly doped, <100>-oriented, polished silicon wafer. The first step is to form the SiO2 layer(0.5 - 1um thick) by thermal oxidation. The oxidation temperature is generally in the range of 900 - 1200 degree C, and the typical gas flow rate is about 1cm/s.

Oxide Grown

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Photoresist Applied

Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer is spun at about 3000rpm to be uniformly spread out.After the spinning step, the wafer is given a pre-exposure baking (80 - 100 degree C) to remove the solvent from the PR film and improve adhesion to the substrate.

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PR Developed

Third step is to define the active area (Drain and Source regions) by photolithography.The PR layer not covered by the mask undergoes a chemical change by UV light and is removed by the spraying the wafer with the developing solution(e.g. Shipley MF319). The final remaining PR is a copy of the pattern on the mask. Finally,the wafer is rinsed and spin-dried, and then baked again so that the PR can resist the strong acid used to etch the exposed oxide layer.

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Oxdie Etched

For SiO2 etching, HydroFluoric(HF) acid is usually used because it attacks oxide, but not silicon or PR. Therefore, the HydroFluoric(HF) acid etches away the oxide in the openings in the PR, and stops at the silicon surface.

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PR Removed

After SiO2 etching, PR is stripped by using either a solvent (Aceton) or a plasma oxidation, leaving behind an insulator pattern that is the same as the opaque image on the mask.

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Phosphorus Diffused

After stripping the PR,a two-step diffusion process is used to form drain and source regions, in which Phosphorus predeposition is first formed under a Constant-Surface-Concentration Condition(CSCC) and then is followed by a drive-in diffusion under a Constant-Total-Dopant Condition(CTDC). Finally, a thin layer of Phosphosilicate Glass on the wafer is removed by HF

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Field Oxide Grown

After the forming the drain and source regions, additional oxide layer is grown from thermal oxidation as before. The Phosphorus spreads out by diffusion during this furnace operation, but the concentration are still much higher than that of the substrate doping.

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PR Applied

The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

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PR Developed


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Oxide Etched


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PR Stripped


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Gate Oxide Grown

After the second photolithography, a very thin gate oxide layer(a few hundred angstroms) is grown by thermal oxidation.

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PR Applied

The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

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PR Developed


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Oxide Etched


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PR Removed


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Aluminium Film Deposited

A metal such as Aluminum is then evaporated on the whole substrate surface(a few thousand angstrom thick) under high-vacuum condition.This method is attractive because it is simple and inexpensive and produces no ionizing radiation.The Al layer will form electrical contacts later.

82

PR Applied

The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

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PR Developed


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Aluminium Interconnect Etched


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Completion of NMOS Fabrication

After the final PR stripping, all the NMOS fabrication steps are completed.

86

Expected Product – Fabricated MOSFET

87

Electrical Characterizationand Testing

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The Profile of MOS Transistor

The profile of the finished wafer The curves of drain current versus drain voltage

89

The Characteristics of PMOS

Saturated Threshold Voltage

-3.00E-05

-2.50E-05

-2.00E-05

-1.50E-05

-1.00E-05

-5.00E-06

0.00E+00

-6.00E+00 -5.00E+00 -4.00E+00 -3.00E+00 -2.00E+00 -1.00E+00 0.00E+00

Vg (V)

Dra

in c

urre

nt (

A)

I-V characteristics of the resistor

-1.50E-03

-1.00E-03

-5.00E-04

0.00E+00

5.00E-04

1.00E-03

1.50E-03

-6.00E+00

-4.00E+00

-2.00E+00

0.00E+00 2.00E+00 4.00E+00 6.00E+00

Voltage (V)

Curr

ent

(A)

Threshold voltage of the PMOS is about –3V

The resistance of the resistor is about 5 kΩ

90

The Characteristics of PMOS (cont.)

Drain Current

-4.00E-04

-3.50E-04

-3.00E-04

-2.50E-04

-2.00E-04

-1.50E-04

-1.00E-04

-5.00E-05

0.00E+00

5.00E-05

-2.00E+01 -1.50E+01 -1.00E+01 -5.00E+00 0.00E+00

Drain voltage (V)

Dra

in c

urre

nt (

A)

Vgs=-5

Vgs=-1

Vgs=-2

Vgs=-3

Vgs=-4

Vgs=-5

Vgs=-6

Vgs=-7

Vgs=-8

Vgs=-9

Vgs=-10

91

MOSFET IV Characteristics

PMOS NMOS

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Fabrication Documents (Runcard) Preparation

93

Process Flow Development Diagram

94

Runcard Checklist

• Process runcard

• Measurement sheet

• Rework sheet

• Equipments list

• Consumables list

• Design specification

• Complete Mask Design

95

Process Runcard

• No. of process steps = 71• No of process module = 11• Shall include the following information;

– Step number– Equipment ID– Wafer out– Time in/out– Date out– Remarks

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Measurement sheet

• Total Number of measurement = 35

• Sheet Resistance Measurement = 6

• Oxide Thickness Measurement = 9

• Resist Thickness Measurement = 4

• CD Measurement = 7

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• Only for lithography process

Rework sheet

98

Actual Transparency Masks

99

Thanks