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Microprocessor-based systems

Course 6 Memory design

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Memory circuits Memory cell:

A digital circuit that memorize one bit (e.g.: flip-flop) Memory location (memory word)

Set of elementary memory cells accessed (read or written) simultaneously

The basic addressing element (1, 4, 8,16, 32 bits) Every location has an address

Memory circuit = Set of memory locations Memory capacity – total number of locations (addresses)

bk . . . b1 b0

. . .

. . .

. . .

. . .

0

1

2

n-1

Linear structure

addresses locations

bk . . . b1 b0

locationLines

columns0 1 2 . . c-1

0

1

2

.

.

l-1

Matrix structure

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Characteristics of a memory circuit Geometry of internal organization:

The length of the memory word, organization and addressing.

Memory capacity, Expressed in number of memory locations or in bytes For example:32 kbytes, 64 kB, 256MB, 1GB.

Volatility: loss of data ROM memory (Read Only Memories) – keeps/stores the

data even when the power supply is switched off ROM, PROM, EPROM, EEPROM, Flash

RAM memory (Random Access Memories): it looses its content if the power supply is switched off

Static RAM (SRAM) High speed, low capacity

Dynamic RAM (DRAM): it looses its memory in time Medium speed, very high capacity

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Characteristics of a memory circuit

Memory technologies: bipolar (TTL, TTL Shottky, ECL) – fast but low

integration ratio, high power consumption MOS, CMOS – high integration ratio, high capacity,

average speed, small power consumption Time features:

Access time: the time needed to read or write a memory location; expressed in nanoseconds [ns].

The duration of a read or write cycle The memory’s speed determined by its access time

or transfer cycle Power consumption, expressed in w/bit.

Bipolar memories have higher power consumption; it depends on the capacity

MOS memories have very low power consumption; it depends on the access frequency

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Non-volatile memories: ROM, PROM EPROM, EEPROM, Flash

ADDR DEC

Data Amplifiers for read and programming

A0

A1

An

Control logic

CSPROG

OE

Dk Dk-1 D1 D0

ADDR

DATA

Valid Address

Valid Data

tACC

TCYCLE

tOE

tCS

tOH

CS

OE

a. b.

The internal structure of a ROM memory

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Non-volatile memories: ROM, PROM EPROM, EEPROM, Flash

ROM – Cannot be written, only read operations are allowed Written by the producer (through masks)

PROM – Programmable ROM - One write (programming) operation is allowed for the used

EPROM (UV) – Erasable PROM – a limited number of erase and re-write operations are allowed (aprox. 100 cycles)

EEPROM – Electrically EPROM – electrical erase and re-write (aprox. 100.000 cycles)

Flash – type of EEPROM with a block organization and higher capacity

WL

DL

T

ROM

WL

DL

T

PROM

Vcc

F

WL

DL

T1

EPROM

PL

T2

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Static RAM memories

ADDR DEC

Input/output circuit

A0

A1

An-1

Control logic

CS

Dk-1 Dk-2 D1 D0

Input amplifier

Output amplifier

k k

Memory matrix

ADDR

DATA

Valid address

Valid Data

tACC

TCITIRE

CS

R/W “1”

tCD

Internal structure

b1.

ADDR

DATA

Valid address

Valid Data

TSCRIERE

tDM

CS

R/W

Time diagrams for read and write operations

WR

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Structure of RAM memoryID k-1

CS

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

ID 1 ID 0

OD k-1 OD 1 OD 0

R/W

ADDR DEC

A0A1

An-1

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Dynamic RAM memory The elementary memory cell is a condenser

It is charged (logical 1) or not (logical 0) at write operation; The charge is lost in time (in aprox. 2 ms)

High capacity Requires refresh operations

Raw addr. dec

MUX / DMUX2n/2-1:1 / 1: 2n/2-1

A0

A1

An/2-1

ID

Raw address

reg

Column address

regn/2

0 1 2 . . 2n/2-1

0

1

2

.

.

2n/2-1

n/2

n/2

RAS

CAS OD

WE

WL/R

DL

T3

WL/W

C

T1 T2

DRAM

Memory cell

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Read, write and refresh cycles for DRAM memory

Column addr.

CAS

ADDR

DATA

Raw addr

Valid data

TREAD

RAS

WE

Read cycle

Column addr.

CAS

ADDR

DATA

Raw addr

Valod data

TWRITE

RAS

WE

Write cycle

CAS

ADDR Raw addr

Trefresh

RAS

WE

Refresh cycle

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Design of a static RAM memory module

The structure of a memory module

AddressesData

Selection

Addre

ss

Am

p.

Data

Am

p. Metrix of

memory circuites

Control circuit

Dec Module

selection

Commands

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Design parameters

• Memory capacity (KB, MB)• Internal organization (ex: 8, 16, 32 bits)• The bus:

• Address lines, data lines and commands• Time restrictions

• Start address (the module’s place in the addressing space of the processor)

• Type of available memory circuits• Other functional requirements

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Design steps

1. Building of a memory sub-module with the required data width

2. Build the memory matrix with the required capacity, using the previously built sub-modules

3. Design the decoder module4. Design of address amplifiers5. Design of data amplifiers6. Design of the control circuit (if needed)

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Design example

Capacity: 1Mbytes Organization: 16 bits with access on 8 bits

too The bus:

ISA (24 address lines, 16 data lines, MRDC, MWTC)

Start address: C0000H Available circuits: 64Kbytes

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Building a sub-module with the required data width

64K*8

64K*8

A1

A2

A16

WR\

CSHi\

CSLi\

D0

D1

D8

D7

D15

D9

Submodule 64K*16= 128K*8

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Building the memory matrix with the required capacity

A1-A16 64K*16

64K*16

64K*16

…

D0-D15WR\CSL0\

CSH0\

CSH1\

CSH7\

CSL1\

CSL7\

512K*16=1M*8

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Design of the decoder unit

CS0\

CS1\

CS7\

A17-A23

MRDC\, MWTC\

DEC DEC

SelMod\

74LS138

A17A18

A19

A23

A22

A21

A20

MRDC\

MWTC\

BHE\ A0

CSL0\

CSH0\

CSL7\

CSH7\SelMod\

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Design of address and data amplifiers

74LS244

74LS244

74LS244

74LS245

74LS245

SelMod\RD\

SA0SA1

SA7

SA8SA9

SA15

SA16

SA23

A0A1

A7

A8A9

A15

A16

A23

SD0SD1

SD7

SD8SD9

SD15

D0D1

D7

D8D9

D15

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Design of a DRAM memory moduleAddress bus Data bus

MUX 2:1 MUX Amp A 2:1 date B DRAM Refresh RAS\ W\ Counter AdrSel CAS\ WR\ CAS0\,CAS1\,….CASn\ MRD\ Command RAS\ MWR\ device CAS\ CSM\ Oscilator RefReq DEC. ... CS0\, CS1\, ..CSn\