1 Material on Embedded Systems

8/20/2019 1 Material on Embedded Systems

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“An Embedded System is a computer basedsystem for an application(s) or product withdedicated software embedded in it. It may bean independent system or part of large system”

Definitions

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“It is any device that includes aprogrammable computer but is not itselfintended to be a general purposecomputer.” – Wayne Wolf

Definitions


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“Embedded Systems are the electronic systemsthat contain a microprocessor or amicrocontroller, but we do not think of them ascomputers- the computer is hidden orembedded in the system.” – Todd D. Morton

Definitions

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Introduction

• Embedded System:

• A digital system with at least one processor thatimplements a hardware function that is a part or all of thedigital system

• Facilitates designer to use a C or C++ program fordescription and design of complex hardware functions

• HLL programs replaces the writing of synthesizable HDLcode for detailed design of hardware

• Embedded Processors: Processor(s) of an embeddedsystem


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Introduction

• Embedded Systems vs Micro-controllers:

• Offer more flexibility and design customization

• Offer the methodologies that include the use of hardware

and software in the same integrated design environment

• Offer higher level design methods for integrating hardware

components with embedded processor

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Evolution of digital devices

1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000

FPGAs

ASICs

CPLDs

SPLDs

Microprocessors

SRAMs & DRAMs

ICs (General)

Transistors

Source : “The Design Warrior’s guide to FPGAs” by Clive Maxfield,

Elsevier 2004


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Classes of the Embedded Systems

1. Small scale system – Single 8 or 16 bit microcontroller, littlehardware and software complexities Usually C/Assembly isused for development of the system eg. C is compiled toassembly then to executable codes to place in memory

2. Medium Scale System - Single or few 16 or 32 bitmicrocontrollers or DSPs or RISCs, may also employ thereadily available ASSPs and IPs in the hardware, usecomplex software design tools. Source code engineeringtool, RTOS, IDE (Integrated Development Environment) asthe development platform, …

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Classes of the Embedded Systems

3. Sophisticated system – enormous hardware andsoftware complexities, may also employconfigurable processors with PLDs, hardware andsoftware co-design is used for the cutting edgeapplications, for example, an iPod or Smart mobilephone


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Look at thissunflower, anature’s gift –How does thenature embed itssoftware? Theflower rotates itsface continuouslytowards the Sun.

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Processing Element in Embedded Systems

Example of Embedded System Hardware Elements


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Processor in the Embedded Systems

1. GPPs –

1. Micro Processors

2. Micro Controllers

3. Embedded Processors

4. DSPs

5. Media Processors

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General purpose microprocessor

Example-

Motorola - 68HCxxx CISC

Intel - 80x86 CISC

- i860 CISC & RISC

Sun -SPARC RISC

IBM -Power PC 601, 604 RISC ARM - Nios RISC


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Commonly used Microcontrollers

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Commonly used Embedded Processors

Example-

AMD - 29050 RISC

Intel - i960 RISC

ARM - ARM 7, ARM 9 RISC


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Selection of a Processor

• Final application requirements

• Capabilities of the processor

• Limitations of the processor

• Knowledge and prior experience of the designer

• Availability of tools for designing and debugging

software applications for the processor

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Main Processor Vendors


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Main PLD Vendors

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PLD design tool by Vendors


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Typical PLD Design Flow

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Design of Digital systems:Abstraction Levels

• Transistors to Programs• Transistor level : putting transistors to implement a given

hardware function

• Gate level: less details; tools were developed for utilizationof gates and verification of design;

• RT level (RTL): focus on transfer of data happensbetween registers, logic units, and buses

• Electronic System level (ESL):• concerned with functionality of the system is to be designed and

the algorithms to be implemented;

• System level tools: design entry tools, simulators, hardwaregeneration programs


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Logic Circuit Design ConceptsDesigning Combinational Circuits

• Primitive gates and elementary structures (Muxs,LUTs, etc.) form a set of structures with which anydigital circuit can be designed

• Design is thought in terms of functionality

• Boolean Algebra is used to make a correspondencebetween logic gates and design functions

• Boolean algebra postulates and theorems are used

for transformation of functions into gates

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Designing Combinational Circuits

eg. Consider a three variable function f(a,b,c)

Reduced function uses fewer gates, have less delay andconsumes less power

.caa.b

b).c.(1ac)a.b.(1

a.. b.c.a.caa.b

)a b.c(a.caa.b

b.c.caa.bf

+=

+++=

+++=

+++=

++=

cb


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• Visual Method to apply Boolean algebra rulesis Karnaugh Map

• Iterative Hardware• Minimization of functions using Boolean rules or

by k-maps is only practical for small functions.

• Partitioning based on regularity of a structure, orbased on independent functionalities, help in

breaking a circuit into smaller manageablecircuits.

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Designing Combinational CircuitsIterative Hardware

• e.g. Consider a 4-bit comparator that generates a 1when its 4-bit A input is greater than its 4-bit B input

The G output becomes 1 if is greater than Logically, this meansthat the product term forms an AND


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Designing Combinational CircuitsIterative Hardware

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• Many high level designs include multiplexers and decoders.

Single bit Mux 8-bit- 4-to-1 Mux

A multiplexer is like an n -position switch that selects one of its ninputs to appear on the output. A multiplexer with n inputs iscalled an n-to-1 Mux. A multiplexer with n data inputs requires


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• Decoder: A combinational circuitthat takes a certain code as inputand generates a different code.eg. BCD to SSD decoder

• A decoder has as many outputsas it has combinations of inputseg. See fig, 2-to-4 decoder withactive low output

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Designing Combinational CircuitsEnable/Disable inputs

• Circuits with three-stateoutputs require an OEinput.

• if OE is active, the outputsof the circuit are asdefined by the function ofthe circuit.

• However when OE isinactive, all circuit outputs

become high-impedanceor float (Z value).

• Fig. shows two 2-to-1multiplexers with three-state outputs that arewired to form a 4-to-1multiplexer.


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Designing Combinational CircuitsHigh-Level Design

• First , the transistors were wired form upper-levelstructures (primitive gates) with easier functionalitiesthat digital designers can relate to.

• Then, gates are used in still higher level structures suchas adders, comparators, decoders and multiplexers.

• These higher-level structures are useful to design at ahigher functional level, called as RT (Register Transfer)

level.• In today's designs, most design libraries include

configurable RTL components for designers to use

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Designing Combinational CircuitsHigh-Level Design

•eg. An Absolute Value Circuit:

Circuit uses an array of eight NOT gates, to complementthe input, an adder to add a 1 to this complement togenerate the two's complement of the input. Themultiplexer on the output for selection of output using thesign-bit of the input.


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Logic Design ConceptsStorage Elements/Memory circuits

• To be able to design circuits that can make decisions

not only on present inputs but also based on past

history, we need to have circuits with memory.

• This history enters the logic structure of a memory

circuit by way of feedbacks

• Basic Latch:

Setting and Resetting the Basic Latch

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Storage Elements/Memory Circuits

• Clocked D Latch:

• when clock is 1 a 1 on D causes s to become 1 which causes Q to set to 1,and a 0 on D causes r to become 1 to reset Q.

• when clock becomes 1, the value of D will be stored until the next time

that clock becomes 1.


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Storage Elements/Memory Circuits

Clocked D-latch is used in applications for buffering

the data. For storing multiple bits of data, multiple

latches with a common clock is used.

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Flip-Flops

Latch Feedback Causes Unpredictable Results

Master-Slave D Flip Flop: isolated input and output


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Flip-Flops Control

• The initial value of a flip-flop output depends on itsinternal gate delays, and in most cases isunpredictable. To force an initial state into a flip-flop,set and reset control inputs can be used should beused.

Flip-flops with Synchronous and Asynchronous Control

A Set or Preset control input forces a flip-flop into its 1 state, and a Reset or Clear input forces it to 0.

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Flip-Flops Control / Register

• Another control input for flip-flops is

a clock enabling input.

• The structure formed by a group of flip-

flops with a common clock signal and

common control signals is called a

register .

An 8-bit Register


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Designing Sequential CircuitsFinite State Machine (FSM)

• The circuits that have memory are also called

sequential circuits and make decisions for a given

input depending on what it has memorized.

• The number of states of a sequential circuit is

determined by its memory. A circuit with n memory bits

has 2n possible states.

• Signals or variables representing these states (n of

them) are called state variables.

• All sequential circuits - from a single latch to a networkof high performance computers - can be regarded as

an FSM.

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Finite State Machine (FSM)

• These machines can be modeled as a combinational

circuit with feedback.

• If the feedback path includes an array of flip-flops

with a clock for controlling the timing of data feeding

back, the circuit becomes a synchronous sequential

circuit.

• Huffman model of synchronous sequential circuits

divides such a circuit into a combinational part and a

register part.


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Finite State Machine (FSM)

Huffman Model of a Sequential Circuit

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Designing State Machines

• Problem Description: A sequence detector with oneInput, x and one output, w, is to be designed. The circuitsearches on its x input for a sequence of 1011. If in fourconsecutive clocks the sequence is detected, then itsoutput becomes 1 for exactly one clock period. Thecircuit continuously performs this search and it allows

overlapping sequences.

• For example, a sequence of 1011011 causes two positive pulseson the output.

Searching for 1011


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• State Diagram: A state diagram is like a flowchart

and it completely describes our state machine for

values that occur on its input. Input events are only

considered if they are synchronized with the clock.

State Diagram for the 1011 Detector

• Each state has a name( A through E ) and acorresponding outputvalue (w is 1 in E and

0 in the other states).• There are edges out of

each state for allpossible values ofcircuit inputs.

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• State Table: It enables us to form truth tables and/ork-maps from circuit behavioral description.


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• State Assignment: Hardwareimplementation requires allvariables in a circuit descriptionto be in binary. For this binaryrepresentation, we assign aunique binary pattern (binarynumber) to each of the statesof our state table. This step ofthe work is called "stateassignment".

• State Variables are y2, y1, y0 . State Assignment

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• Transition Table: State names in the state table must

be replaced with their corresponding binary values.

This table is called a transition table.

Transition Table for the 1011 Detector


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• Excitation Table: The combinational and the register

parts of the design are separated. The register part is

simply an array of flip-flops with a common clock

signal. The combinational part is where present

values of flip-flops (their outputs) are used as input to

generate flip-flop input values that will become their

next state values. Flip-flop input tables are called

Excitation Tables.

• Tables for values of D2, D1, D0 and in our 1011

sequence detector are the same as those for y2+,

y1+, y0 + .

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Flip-flop Excitation Table


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• Implementing the Combinational Part The steps of

design of combinational part is completely described by

the excitation table

• This table includes values for D2, D1, D0 in terms of x,

y2, y1,and y0 . K-maps can be extracted from the table

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The four-inputs (x, y2, y1, and

y0) and four-output (w, D2, D1,

D0 combinational circuit is fully

defined by Boolean expressions


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• The design of the 1011

sequence detector will be

completed by wiring the

gate-level realization of

the combinational part

with the flip-flops of the

register part. The

implementation is done

according to the Huffman

model.

Logic Block Diagram of the 1011 Detector

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• Mealy and Moore Machines:

• If in a state machine output only uses state

variables and does not involve input, the state

machine is called a Moore machine.

• In Mealy machine, the output value in each state

are specified on the edge out of the state, alongwith input values i.e. the value of input decides

the value of the output.


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• Implementation of sequence detector with a Mealy

machine usually requires one state less than the Moore

machine that detects the same sequence.

• 1011 detector requires four states, two state variables,

and three 3-variable Karnaugh maps for the two state

variables and the output.

Mealy State Diagram

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• One-Hot Realization / Ring Counter Type:

• This realization uses one flip-flop per state of the

machine. Since in a state diagram only one state is

active at any one time, only one of the

corresponding flip-flops becomes active

• It uses more flip-flops than the binary state

assignment but uses fewer logic gates for activationof the flip-flops.


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Designing State Machines: Implementation

One-hot Implementation of Mealy Machine

• Output of the AND gates on the outputs of the flip-flops

correspond to the edges that come out of the states of the state

diagram.

• AND gates are conditioned by x=0 or x=1.

• Flip-flops use four states (1000, 0100, 0010 and 0001) out of 24

possible states.

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Designing State Machines: One-hot Realization

• Initialization of a one-hot machine should be done

such that it is put into one of its valid states. Starting

the machine in 0000 is wrong because it will never

get out of this state.

• Advantages of one-hot machines : ease of design,

regularity of their structure, and testability.


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Designing Sequential CircuitsSequential Packages

• As there are commonly used combinational

packages, like adders, decoders and multiplexers,

there are commonly used sequential packages like

registers, counters and shifters.

• Counter : A sequential circuit that counts a certainsequence in ascending or descending order. An n-bitbinary up-counter counts n-bit numbers in the

ascending order.

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Sequential Packages: Counters

• With each clock pulse, when UD is 1 it counts up and when UD is 0 itcounts down.

• In the count-up mode the next count after 11 is 00, and in the count-

down mode the next count after 00 is 11.

State Diagram of a 2-bit up/down Counter


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Excitation K-maps for a 2-Bit Up-Down Counter with D flip-flops

Implementation of Two-Bit Up-Down Counter

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• Counters with additional features:

• Resetting :

• Asynchronous resetting forces the counter into its initial state and actsindependent of the clock.

• Synchronous resetting loads the initial state of the counter through the D-inputs of counter flip-flops,

• Parallel loading: To start counting from a given state, the counteris put into parallel-load mode and the designated start state isloaded into the flip-flops of the counter.

• Enabling :An enable input for a counter makes it count onlywhen this input is active.

• Carry in and Carry out : carry-in and carry-out input and outputsignals that are used for cascading


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Sequential Packages: Counters Parallel loading with P1, P0113Counter counts up012

Counter is reset to 0101

Disable the counter000

Operationm0m1Mode

•Counter only counts if carry_in is 1, otherwise it is disabled.

• When carry_in is 1 and counter reaches 11, the carry_out becomes 1.

•Cascading counters can be done by connecting carry_out of one to the carry_in of another.

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Sequential Packages: Shifters

• Shifters: The registers with the property to shift dataright or left with the edge of the clock. These areused for serial data collection, serial to parallel, andparallel to serial converters.

A 4-bit Shift Register


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Memories:

• Memories are two-

dimensional arrays of

flip-flops, or one-

dimensional arrays of

registers.

A 2n m -bit Memory

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RTL Design with HDLsCombinational Circuits

• GATE-LEVEL COMBINATIONAL CIRCUIT• Behavioral Description:

Eg. 1-bit comparator: Use basic logic gates, which include not, and, or,and xor cells, to implement the circuit with logic expression

eq = i0 . i1 + i0’ . i1’ (SOP form)l i b r a r y ieee;

use ieee.std-logic-ll64.all;

e n t i t y eq1 i s

p o r t ( i 0 , il: in std-logic;

eq: out std-logic) ;

end eql;a r c h i t e c t u r e sop-arch of eql i s

s i g n a l p0, p 1 : std-logic;

begin

eq


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Eg. Gate-level implementation of a 2-bit comparatorl i b r a r y i e e e ;

use ieee . std-logic-1164.all;

entity eq2 is

port ( a , b : in std -logic - vector ( 1 downto 0 ) ;

a e q b : out s t d - l o g i c ) ;

end e q 2 ;

architecture sop-arch of eq2 is

signal p0, pl, p2, p3 : s t d - l o g i c ;

begin

a eq b b(1), eq=>e1);

aeqb


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Combinational Circuits : Verification

• Simulation is performed to verify the correctness of the circuit

operation and can be synthesized to a physical device. Simulation is

usually performed within the same HDL framework by creating a

special program, known as a test-bench, to mimic a physical lab

bench.

Test bench for a 2-bit comparator.

The uut block is the unit under test, the test vector generator block generates

testing input patterns, and the monitor block examines the output responses.

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Combinational Circuits : Verification

• Test-bench for a 2-bit comparator


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• RT-LEVEL COMBINATIONAL CIRCUIT

• HDL description of module-level circuits, which are composed

of intermediate-sized components, such as adders,

comparators, and multiplexers; uses these components as the

basic building blocks in register transfer methodology, referred

to as RT-level design.

• RT-LEVEL COMPONENTS: In addition to the logical

operators, relational operators and several arithmetic operators

can also be synthesized automatically. These operators

correspond to intermediate-sized module-level components,such as comparators and adders.

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Combinational Circuits: RTL

• Operators and data types of VHDL-93 and IEEE std-logic-I164 package


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• Overloaded operators and data types in the IEEE numeric.std package

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• Type conversions between std-logic-vector and numeric data types

Concatenation operator : The concatenation operator, &, combines segments of

elements and small arrays to form a large array.


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• CONCURRENT ASSIGNMENT STATEMENTS

• Conditional signal assignment Statements

• Selected signal assignment Statements

Syntax and conceptual implementation: The simplified syntax of a

conditional signal assignment statement is

signal-name


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Combinational Circuits: RTLconcurrent ASSIGNMENT STATEMENTS

Selected signal assignment Statements

Syntax and conceptual implementation: The simplified syntax of a selected

signal assignment statement is

with sel select

sig


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Sequential Statements: Process

• Process: VHDL contains a number of sequential statements, to execute thesestatements, they are encapsulated inside a process.

• A process itself is a concurrent statement. It can be thought of as a black boxwhose behavior is described by sequential statements. Generally process is usedfor two purposes:

• Describe routing structures with i f and case statements.

• Construct templates for memory elements

The simplified syntax of a process with a sensitivity list is

process (sensitivity-list)

begin

sequential statement;

sequential statement;

. . .end process ;

Sensitivity-list: List of signals to which the process responds (i.e., is "sensitive to"). For acombinational circuit, all the input signals should be included in this list. The body of a process iscomposed of any number of sequential statements.

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Sequential Statements: Process

process (a, b)

begin

c


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Sequential Statements:

• IF AND CASE STATEMENTS: If and case statements are two othercommonly used sequential statements. Conceptually, they can be used todescribe routing structures.

If statement: Syntax

if boolean-expr_1 then

sequential_statements;

elsif boolean_expr-2 then

sequential_statements;

elsif boolean_expr-3 then

sequential_statements ;

. . .e l s e

sequential_statements ;

end i f ;

The Boolean expressions are evaluated sequentially

until an expression is evaluated as true or the else

branch is reached, and the statements in the

corresponding branch will be executed.

Note: The if statement must be encapsulated inside a process.

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• Case statement: Case statement uses the “sel” signal to select aset of sequential statements for execution. Conceptually, casestatement infers a similar multiplexing structure during synthesis.

Syntax :

case sel is

when choice_1 =>

sequential statements;

when choice_2 =>

sequential statements ;

when others =>

sequential statements;

end case ;


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•Comparison to concurrent statements

The simple if and case statements are equivalent to the

conditional and selected signal assignment statements.

However, an if or case statement allows any number and any

type of sequential statements in their branches and thus is

more flexible and versatile.

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•CONSTANTS AND GENERICS

Constants: HDL code frequently uses constant values inexpressions and array boundaries. One good design practice is to

replace the “hard literals” with symbolic constants. It makes code

clear and helps future maintenance and revision.

Syntax:

constant const-name : data_type := value_expression;

For example, we can declare two constants as

constant DATA_BIT: integer := 8;

constant DATA-RANGE: integer : = 2**DATA_BIT - 1;


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• Constant:

Adder using a hard literal Adder using a constant

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Generics: Construct generic, is to pass information into an entityand component.

Syntax:entity entity-name is

generic (

generic-name : data-type : = default-values ;

generic-name : data-type : = default-values ;

generic-name : data-type : = default-values

);port (

port-name : mode data-type ;

…

);

end entity-name;


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Adder using a generic

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1 Material on Embedded Systems