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Lecture 22: Multiprocessor

Parallel programming, cache coherency, memory consistency, bus snooping, directory-based CC, SMP using ILP processors

Adapted from UCB CS252 S01, Revised by Zhao Zhang

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Three Types of Parallel ApplicationsCommercial Workload

TPC-C, TPC-D, Altavista (Web search engine)

Multiprogramming and OS Workload

Scientific/Technical ApplicationsExamples:

FFT Kernel: 1D complex number FFT LU Kernel: dense matrix factorization Barnes App: Barnes-Hut n-body algorithm,

galaxy evolution Ocean App: Gauss-Seidel multigrid technique

to solve a set of elliptical partial differential eq.s’

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Amdahl’s Law and Parallel Computers

Amdahl’s Law: speedup is limited by the fraction of the portions that can be parallelized

Speedup ≤ 1 / (1-f), where f is the fraction of sequential computation

How large can be f if we want 80X speedup from 100 processors?

1 / (f+(1-f)/100) = 80f = 0.25% !

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Why Multiprocessors?Uniprocessors cannot keep going!

Building multiprocessors: Use conventional microprocessors to build parallel computers

Long term goal: scale number processors to size of budget, desired performanceMachines example: Sun Enterprise 10000 (8/00) 64 400 MHz UltraSPARC® II CPUs,64 GB SDRAM memory, 868 18GB

disk,tape $4,720,800 total 64 CPUs 15%, 64 GB DRAM 11%, disks 55%, cabinet 16%

($10,800 per processor or ~0.2% per processor)Machines example: Dell Workstation 220 (2/01) 866 MHz Intel Pentium® III (in Minitower) 0.125 GB RDRAM memory, 1 10GB disk, 12X CD, 17” monitor,

nVIDIA GeForce 2 GTS,32MB DDR Graphics card, 1yr service $1,600; for extra processor, add $350 (~20%)

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Where is Supercomputing heading?Three major forms: Massively parallel processor,

multiprocessor, cluster

1997, 500 fastest machines in the world: 319 MPPs, 73 bus-based shared memory (SMP), 106 parallel vector processors (PVP)

2000, 381 of 500 fastest: 144 IBM SP (~cluster), 121 Sun (bus SMP), 62 SGI (NUMA SMP), 54 Cray (NUMA SMP)

Parallel computer architecture : a hardware/ software approach, David E. Culler, Jaswinder Pal Singh, with Anoop Gupta. San Francisco : Morgan Kaufmann, c1999.

http://www.top500.org/

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Shared Address/Memory Processor Model

Each processor can name every physical location in the machineEach process can name all data it shares with other processesData transfer via load and storeData size: byte, word, ... or cache blocksUses virtual memory to map virtual to local or remote physicalMemory hierarchy model applies: now communication moves data to local processor cache (as load moves data from memory to cache)

Latency, BW, scalability when communicate?

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Shared Address/Memory Multiprocessor Model

Communicate via Load and StoreBased on timesharing: processes on multiple processors vs. sharing single processorProcess: a virtual address space and > 1 thread of control

ALL threads of a process share a process address space Pthread example: calculate X[i] = X[i] – X[i-1];pthread_t pit[K];double X[N];for (i=1; i<K; i++)pthread_create(&pit[i],…,do_calc, i);

do_calc(0);for (i=1; i<K; i++)pthread_join(pid[i], …);

Writes to shared address space by one thread are visible to reads of other threads

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Advantages of Shared-memory Model

Ease of programming when communication patterns are complex or vary dynamically during execution

Lower communication overhead, good utilization of communication bandwidth for small data items, no expensive I/O operations

Hardware-controlled caching to reduce remote commutations when remote data is cached

Another favor: Message passing (e.g. MPI)

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SMP InterconnectProcessors to Memory AND to I/OBus based: all memory locations equal access time so SMP = “Symmetric MP”

Sharing limited BW as add processors, I/O

P P P P

Cache Cache Cache Cache

Main memory I/O system

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Coherency CoherenceOn P1: On P2Write X; Read X;

Informally: “Any read must return the most recent write” Too strict and too difficult to implement

Better: “Any write must eventually be seen by a read” All writes are seen in proper order (“serialization”)

Two rules to ensure this: “If P writes x and P1 reads it, P’s write will be seen by P1 if the read

and write are sufficiently far apart” Writes to a single location are serialized: seen in one order

Latest write will be seen Otherwise could see writes in illogical order

(could see older value after a newer value)

Cache coherency in multiprocessors: How does a processor know changes in the caches of other processors? How do other processors know changes in this cache?

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Memory Consistency ModelDeal with the order of how a sequence of writes appear to readers

What would happen if P2 see “flag=1” first? On P1: On P2:A = 1; while (flag==0);flag = 1; print A;

Sequential consistency: read and writes are “globally” serialized from every processor’s viewpoint

Performance penalty may be significantRelaxed memory consistency model: redefine correctness for performance!

Commonly used: relax write-to-read program order E.g. Processor Consistency (PC), Total store ordering (TSO)

On P1: On P2: | On P1: On P2:A = 1; print B; | A = 1; B = 1;B = 1; print A; | print B; print A;

Very abstract, complex and theoretical; being an important issue for multiprocessor performance

Read text and Culler’s book if you have to be concerned with MC

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Potential HW Coherency Solutions

Snooping Solution (Snoopy Bus): Send all requests for data to all processors Processors snoop to see if they have a copy and respond

accordingly Requires broadcast, since caching information is at

processors Works well with bus (natural broadcast medium) Dominates for small scale machines (most of the

market)Directory-Based Schemes

Keep track of what is being shared in 1 centralized place (logically)

Distributed memory => distributed directory for scalability(avoids bottlenecks)

Send point-to-point requests to processors via network Scales better than Snooping Actually existed BEFORE Snooping-based schemes

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Basic Snoopy ProtocolsWrite Invalidate Protocol:

Multiple readers, single writer Write to shared data: an invalidate is sent to all caches

which snoop and invalidate any copies Read Miss:

Write-through: memory is always up-to-date Write-back: snoop in caches to find most recent copy

Write Broadcast Protocol (typically with write through):

Write to shared data: broadcast on bus, processors snoop, and update any copies

Read miss: memory is always up-to-date

Write serialization: bus serializes requests! Bus is single point of arbitration

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An Example Snoopy ProtocolInvalidation protocol, write-back cacheEach block of memory is in one state:

Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches

Each cache block is in one state (track these): Shared : block can be read OR Exclusive : cache has only copy, its writeable, and

dirty OR Invalid : block contains no data

Read misses: cause all caches to snoop busWrites to clean line are treated as misses

Extended MESI (Modified, Exclusive, Shared, and Invalid) is more commonly used

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Place read misson bus

Snoopy-Cache State MachineState machinefor CPU requestsfor each cache block and for bus requests for each cache block

InvalidShared

(read/only)

Exclusive(read/write)

CPU Read

CPU Write

CPU Read hit

Place Write Miss on bus

CPU read missWrite back block,Place read misson bus CPU Write

Place Write Miss on Bus

CPU Read missPlace read miss on bus

CPU Write MissWrite back cache blockPlace write miss on bus

CPU read hitCPU write hit

Cache BlockState

Write miss for this block

Write BackBlock; (abortmemory access)

Write miss for this block

Read miss for this block

Write BackBlock; (abortmemory access)

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Larger MPsSeparate Memory per ProcessorLocal or Remote access via memory controller1 Cache Coherency solution: non-cached pages Alternative: directory per cache that tracks state of every block in every cache

Which caches have a copies of block, dirty vs. clean, ...Info per memory block vs. per cache block?

PLUS: In memory => simpler protocol (centralized/one location)

MINUS: In memory => directory is ƒ(memory size) vs. ƒ(cache size)

Prevent directory as bottleneck? distribute directory entries with memory, each keeping track of which Procs have copies of their blocks

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Distributed Directory MPs

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Directory ProtocolSimilar to Snoopy Protocol: Three states

Shared: ≥ 1 processors have data, memory up-to-date Uncached (no processor hasit; not valid in any cache) Exclusive: 1 processor (owner) has data;

memory out-of-date

In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy)Keep it simple(r):

Writes to non-exclusive data => write miss

Processor blocks until access completes Assume messages received

and acted upon in order sent

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Directory ProtocolNo bus and don’t want to broadcast:

interconnect no longer single arbitration point all messages have explicit responses

Terms: typically 3 processors involved Local node where a request originates Home node where the memory location

of an address resides Remote node has a copy of a cache

block, whether exclusive or shared

Example messages on next slide: P = processor number, A = address

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Memory Consistency and ILP

Speculate loads, recovered on violation With ILP and SC what will happen on this?

P1 code P2 code P1 exec P2 execA = 1 B = 1 spec. load B spec. load Aprint B print A store A store B

retire load B flush at load A

SC can be maintained, but expensive, so use TSO or PC Speculative execution and rollback can still

improve performance

Performance: ILP + Strong MC Weak MC

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Multiprocessor ConclusionSome optimism about future

Parallel processing beginning to be understood in some domains

More performance than that achieved with a single-chip microprocessor

MPs are highly effective for multiprogrammed workloads MPs proved effective for intensive commercial workloads,

such as OLTP (assuming enough I/O to be CPU-limited), DSS applications (where query optimization is critical), and large-scale, web searching applications

On-chip MPs appears to be growing, e.g., IBM Power4 1) embedded market where natural parallelism often exists an obvious alternative to faster less silicon efficient, CPU. 2) diminishing returns in high-end microprocessor encourage designers to pursue on-chip multiprocessing

Future: CMP + SMT?