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2
Finite state machines
FSM: A system that visits a finite number of logically distinct states
Counters are simple FSMs Outputs and states are identical Visit states in a fixed sequence without
inputs
3
More than counters
FSMs are typically more complex than counters Outputs can depend on current state and
on inputs State sequencing depends on current
state and on inputs
4
FSM design
Counter design procedure1. State diagram
2. State-transition table
3. Next-state logic minimization
4. Implement the design
FSM design procedure1. State diagram
2. State-transition table
3. State minimization
4. State encoding
5. Next-state logic minimization
6. Implement the design
5
Example: Vending machine
15 cents for a cup of coffee Doesn’t take pennies or quarters Doesn’t provide any change
VendingMachine
FSM
N
D
Reset
Clock
OpenCoinSensor
ReleaseMechanism
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1. State diagram
S0
Reset
S2
D
S6[open]
D
S4[open]
D
S1
N
S3
N
S5[open]
N
S8[open]
D
S7[open]
N
(from all states)
Draw self-loops for N’ D’ for S0 to S3
Also draw self-loops for 1 for S4 to S8
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2. State transition tablepresent inputs next outputstate D N state open
S0 0 0 0 1 1 01 1
S2 0 0 S2 00 1 S5 01 0 S6 01 1 X X
S3 0 0 S3 00 1 S7 01 0 S8 01 1 X X
S4 X X S4 1 S5 X X S5 1 S6 X X S6 1 S7 X X S7 1 S8 X X S8 1
S0 0S1 0S2 0X X
S1 0 0 S1 00 1 S3 01 0 S4 01 1 X X
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3. State minimization
0¢
Reset
5¢
N
N
N + D
10¢
D
15¢[open]
D
N’D’
N’D’
Resetsymbolic state table
present inputs next outputstate D N state open 0¢ 0 0 0¢ 0
0 1 5¢ 01 0 10¢ 01 1 – –
5¢ 0 0 5¢ 00 1 10¢ 01 0 15¢ 01 1 – –
10¢ 0 0 10¢0 1 15¢ 01 0 15¢ 01 1 – –
15¢ – – 15¢ 1
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4. State encoding
present stateinputs next state outputQ1 Q0 D N D1 D0 open
0 0 0 0 0 0 00 1 0 1 01 0 1 0 01 1 – – –
0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 – – –
1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 – – –
1 1 – – 1 1 1
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5. Next-state logic minimization
0 1 1 0
1 0 1 1
X X X X
0 1 1 1
D0
Q0
N
D
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
0 0 1 1
0 1 1 1
X X X X
1 1 1 1
Q1D1
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1Open
Q0
N
D
Q1D0
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Generalized FSM model
Combinational logic computes next state and outputs Next state is a function of current state and
inputs Outputs are functions of
Current state (Moore machine) Current state and inputs (Mealy machine)
InputsOutputs
Next State
Current State
outputlogic
Next-statelogic
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Moore vs. Mealy machines
outputs
state feedback
inputs
reg
combinational logic for
next state logic foroutputs
Moore machineOutputs are a function
of current state
Outputs changesynchronously with
state changes
Mealy machineOutputs depend on state
and on inputs
Input changes can cause immediate output changes
(asynchronous)
inputs outputs
state feedback
regcombinational
logic fornext state
logic foroutputs
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State diagrams
Moore machine Each state is labeled by a
state-name/output pair.
Mealy machine
Each transition arc is labeled by a input-condition/output pair.
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D QQ
D QQ
A
B
clock
out
Example: 10 01
Circuits recognize AB=10 followed by AB=01 What kinds of machines are they?
D QQ
D QQ
D QQ
D QQ
A
B
clock
out
Moore
Mealy
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Example: "01" or "10" detector
Moore: Output is a function of state only Specify output in the state bubble
D/1
E/1
B/0
A/0
C/0
1
0
0
00
1
1
1
1
0
reset
current next currentreset input state state output
1 – – A 00 0 A B 00 1 A C 00 0 B B 00 1 B D 00 0 C E 00 1 C C 00 0 D E 10 1 D C 10 0 E B 10 1 E D 1
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Example: "01" or "10" detector
Mealy: Output is a function of state and inputs Specify outputs on transition arcs
B
A
C
0/1
0/0
0/0
1/1
1/0
1/0
reset/0
current next currentreset input state state output
1 – – A 00 0 A B 00 1 A C 00 0 B B 00 1 B C 10 0 C B 10 1 C C 0
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Moore vs. Mealy
Moore machines + Safer to use because outputs change at clock
edge
– May take additional logic to decode state into
outputs Mealy machines
+ Typically have fewer states
+ React faster to inputs — don't wait for clock
– Asynchronous outputs can be dangerous
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Synchronous Mealy machines
We often design synchronous Mealy machines Design a Mealy machine Then register the outputs
20
Synchronous Mealy machines
Registered state and registered outputs No glitches on outputs No race conditions between communicating
machines
inputs outputs
state feedback
regcombinational
logic fornext state
logic foroutputs
reg