1. INTRODUCTION · 2017. 3. 29. · 3 1. INTRODUCTION 17MB25 mainboard is based on MSTAR concept IC. This IC is capable of handling audio processing, video processing, scaling-display

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1. INTRODUCTION.................................................................................................................. 32. TUNER................................................................................................................................... 3

1.1 General description of TDTC-G101D: .................................................................. 31.2 Features of TDTC-G101D: .................................................................................... 31.3 Pin Configuration ................................................................................................... 4

3. AUDIO AMPLIFIER STAGE WITH TPA3101 ................................................................... 43.1 General Description of TPA3101................................................................................. 43.2 Features of TPA3101 .................................................................................................. 43.3 Pin Configuration of TPA3101 .............................................................................. 5

4. MICROCONTROLLER (MSTAR)....................................................................................... 64.1 Genaral Description..................................................................................................... 64.2 Features .................................................................................................................. 6

5. INTEGRATED DVB-T RECEIVER (CHEERTEK) ............................................................ 75.1 General Description...................................................................................................... 75.2 Features .................................................................................................................. 8

6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM) ............................................................ 106.1 General Description.................................................................................................... 106.2 Features ...................................................................................................................... 106.3 Pin Configuration ...................................................................................................... 11

7. 512K CMOS SERIAL FLASH – MX25L512 ..................................................................... 127.1 General Description.................................................................................................... 127.2 Features ...................................................................................................................... 12

8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM) .......................................................... 148.1 General Description.................................................................................................... 148.2 Features ...................................................................................................................... 14

9. SAW FILTER ...................................................................................................................... 149.1 IF Filter for Audio Applications – Epcos K9656M ................................................... 149.1.1 Standarts .................................................................................................................. 149.1.2 Features ................................................................................................................... 15 9.1.3 Pin Configuration .................................................................................................. 159.1.4 Frequency Response................................................................................................ 159.2 IF Filter for Video Applications – Epcos K3958M.................................................... 169.2.1 Standarts .................................................................................................................. 169.2.2 Features ................................................................................................................... 169.2.3 Pin Configuration .................................................................................................... 169.2.4 Frequency Response................................................................................................ 17

10. POWER STAGE ................................................................................................................ 1711. IC SPECIFICATIONS ....................................................................................................... 18

11.1 32K Smart Serial EEPROM – 24C32 ..................................................................... 1811.2 TL062 ...................................................................................................................... 1911.3 PI5V330 ................................................................................................................... 2011.4 74HCT4053............................................................................................................. 2111.5 FMS6145................................................................................................................. 2211.6 LM1117................................................................................................................ 2311.7 ST24LC21 ............................................................................................................... 2411.8 24LC02.................................................................................................................... 2511.9 MAX810............................................................................................................... 2611.10 TDA1308............................................................................................................... 2711.11 MP1583 .................................................................................................................. 2711.12 MP2112 ............................................................................................................ 29

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11.13 IRF7314............................................................................................................ 2912. BLOCK DIAGRAMS ........................................................................................................ 30

12.1 General Block Diagram............................................................................................ 3012.2 Integrated DVB-T Receiver Block Diagram............................................................ 3212.3 MSTAR Block Diagram....................................................................................... 33

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1. INTRODUCTION17MB25 mainboard is based on MSTAR concept IC. This IC is capable of handling audio processing, video processing, scaling-display processing, 3D comb filter, OSD and text processing, 8 bit dual LVDS transmitter.

TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.

Sound system is able to supply 2x10W (10%THD) audio output power for stereo speakers. Supported peripherals are:

The analog part of the moard can support DVD module which is connected to mainboard through a cable. The USB feature is supported through digital part of the mainboard.

1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)1 SCART socket(Common)1 YPbPr (Common)1 PC input(Optional)2 HDMI (Common)1 Stereo audio input for PC(Common)1 Line out(Common)1 S/PDIF output(Common)1 Side S-Video(Optional)1 Headphone(Common)1 Common interface(Optional)1 Digital USB(Opional)1 RS232(Optional)

2. TUNERA horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3 Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on the Tuner in use.

1.1 General description of TDTC-G101D:The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C bus.

1.2 Features of TDTC-G101D: Digital Half-NIM tuner for COFDM Covers 3 Bands(From 48MHz to 862MHz for COFDM, From 45.25MHz to 863.25MHz for CCIR CH)

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Including IF AGC with SAW Filter Bandwidth Switching (7/8 MHz) possible DC/DC Converter built in for Tuning Voltage Internal(or External) RF AGC, Antenna Power Optional

1.3 Pin Configuration

3. AUDIO AMPLIFIER STAGE WITH TPA3101

3.1 General Description of TPA3101The TPA3101D2 Rev.A evaluation module consists of a single 10-W, class-D, stereo audio power amplifier complete with a small number of external components mounted on a circuit board that can be used to directly drive a speaker with an external analog audio source as the input.

The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, 36dB. The outputs are fully protected against shorts to GND, Vcc and output to output shorts with an auto recovery feature and monitor output.

3.2 Features of TPA3101 10-W/ch into an 8-Ω Load From a 13-V Supply 9.2-W/ch into an 8-Ω Load From a 12-V Supply Operates from 10 V to 26 V 87% Efficient Class-D Operation Eliminates Need for Heat Sinks Four Selectable, Fixed Gain Settings

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Differential Inputs Thermal and Short-Circuit Protection With Auto Recovery Feature Clock Output for Synchronization With Multiple Class-D Devices Surface Mount 7 mm ´ 7 mm, 48-pin QFN Package Surface Mount 7 mm ´ 7 mm, 48-pin HTQFP Package

3.3 Pin Configuration of TPA3101

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4. MICROCONTROLLER (MSTAR)

4.1 Genaral DescriptionThe MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function LCD monitor/TV with resolutions up to full HD (1920x1080). It is configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two scaling engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit MCU and a built-in output panel interface. By use of external frame buffer, PIP/POP is provided for multimedia applications. Furthermore, 3-D video decoding and processing are fulfilled for high-quality TV applications. To further reduce system costs, the MST6WB7GQ-3 also integrates intelligent power management control capability for green-mode requirements and spread-spectrum support for EMI management.

4.2 Features

LCD TV controller with PIP/POP display functions Input supports up to UXGA & 1080P Panel supports up to full HD (1920x1080) TV decoder with 3-D comb filter Multi-standard TV sound demodulator and decoder 10-bit triple-ADC for TV and RGB/YPbPr 10-bit video data processing Integrated DVI/HDCP/HDMI compliant receiver High-quality dual scaling engines & dual 3-D video de-interlacers 3-D video noise reduction Full function PIP/PBP/POP MStarACE-3 picture/color processing engine Embedded On-Screen Display (OSD) controler engine Built-in MCU supports PWM & GPIO Built-in dual-link 8/10-bit LVDS transmitter 5-volt tolerant inputs Low EMI and power saving features 296-pin LQFP

NTSC/PAL/SECAM Video Decoder Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM Automatic TV standard detection Motion adaptive 3-D comb filter for NTSC/PAL 8 configurable CVBS & Y/C S-video inputs Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip Macrovision detection CVBS video output

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Video IF for Multi-Standard Analog TV Digital low IF architecture Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution Maximum IF analog gain of 37dB in addition to digital gain Programmable TOP to accommodate different tuner gain to optimize noise and

linearity performance

Multi-Standard TV Sound Decoder Supports BTSC/NICAM/A2/EIA-J demodulation and decoding FM stereo & SAP demodulation L/Rx4, mono, and SIF audio inputs L/Rx3 loudspeaker and line outputs Supports sub-woofer output Built-in audio output DAC’s Audio processing for loudspeaker channel, including volume, balance, mute, tone, EQ,

and virtual stereo/surround Optional advanced surround available (Dolby1, SRS2, BBE3… etc)

Digital Audio Interface I2S digital audio input & output S/PDIF digital audio input & output HDMI audio channel processing capability Programmable delay for audio/video synchronization

Analog RGB Compliant Input Ports Three analog ports support up to UXGA Supports HDTV RGB/YPbPr/YCbCr Supports Composite Sync and SOG (Sync-on-Green) separator Automatic color calibration

DVI/HDCP/HDMI Compliant Input Port Two HDMI input ports with built-in switch Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color

resolution Single link on-chip DVI 1.0 compliant receiver High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver

5. INTEGRATED DVB-T RECEIVER (CHEERTEK)

5.1 General DescriptionCT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared with Cheertek's previous generations of STB receiver devices. CT216T further interates COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-flickering,

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HW JPEG decoding, flesh tone and black-white extensions, and improvement of small video quality.

CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder, audio DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI controller and other peripherals.

Cli216T is designed in focus on the market of single tuner input product which makes, it a cost effective solution. Supports include free to air, conditional access for SC (Smart card) and CI portable devices, PVR, LCD TV, and other DVB-T applications.

5.2 FeaturesCOFDM Demodulator ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant Automatic spectral inversion, detection Integrated ADC Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported Single IF AGC or dual RF/lF AGC controls with ΔΣ modulabon Impulsive noise cancellation Carrier acquisition range: ±400 kHz (extensible to ±600 kHz in 8MHz BW) Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels

with one 8MHz analog filter Co-channel interterence (CCl) supression RF signal strength monitor

MPU Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS 8KB I-Cache and 8KB D-Cache Two general purpose timers Watchdog timer DSU for source level debug

Memory 6-bit SDRAM controller supports up to 32MB (16MB for l28-pin) Unified memory architecture Parallel flash (216-pin only) 1/2-bit SPI flash

Transport De-multiplexing TS, PES, and ES demultiplexing OneTS path CI CAM interface (216-pin only) 32 general purpose PID filters 32 Section filters CRC-32 accelerator DVB-CSA de-scramblers

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Video Decoding and Processing MPEG-2 MP@ML MPEG-4 SP&ASP PAL/NTSC format conversion 3:2 pull down Zoom in/out from 1/16X to 16X HW JPEG decode 4/8/16-bit OSD with anti-flickering On chip NTSC/PAL TV encoder CVBS, S-VHS, and component video VBI insertion for Teletext, CC and WSS ITU-R BT.601 and ITU-R BT.656 outputs Flesh tone extension Black/white extension,

Audio Decoding and Processing MPEG-1: layer 1/2/3 MPEG-2: layer 1/2 Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,

32K, 44.1K, and 48KHz Decode CU-DA at sampling frequency of 44.1 KHz SPDIF out for AC-3 by-pass Embedded 2 channels audio DAC for L/R outputs Digital mute control and volume adjustment

OSD(On Screen Display) There are total 9 display planes: border; background. video. RS1 (Rectangle Strip 1),

RS2, OSD, RS3, RS4, and cursor. 4/8l16-bit OSD with anti-flickering and anti-flutter Support alpha-blending per color Adjustable brightness control in window Bitmap OSD Support horizontal pixel duplication to enlarge bitmap automatically Support sub-region redraw to facilitate bitmap display.

Digitnal TV Encoder NTSC-M, PAL-B, D, G, H, I, Nc, M encoding Four video DACs to provide 6 configuration output: modes Support CVBS, S-VHS. and component video outs VBI insertion for Teletext, CC and WSS Color burst amplitude control Programmable sync. level On chip, color-bar generator

High Speed I/O USB 2.0 HS host controller

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Memory card reader with SD, MMC, and MS interfaces Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes. Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format spec

1.43 with 1-bit and 4-bit modes.

Peripherals Up to 3 full duplex UART with 16-byte FIFO 2-wire serial (2WS) in master mode .. . Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART) 5 digits 7-Segrnent LED control 5x3 two-dimension key scan 2 SAR-ADC input 4 PWM input/output 1 HW IR command decode GPIO

Electrical and Physical Characteristics Capable of using single 27MHz clock input crystal 1.8V and 3.3V dual power supply Power standby mode PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package

6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM)

6.1 General DescriptionThe EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

6.2 Features Fast access time from clock: 4.5/5/5.4 ns Fast clock rate: 200/166/143 MHz Fully synchronous operation Internal pipelined architecture 1M word x 16-bit x 4-bank Programmable Mode registers

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CAS Latency: 2, or 3 Burst Length: 1, 2, 4, 8, or full page Burst Type: interleaved or linear burst Burst stop function Auto Refresh and Self Refresh 4096 refresh cycles/64ms CKE power down mode Single +3.3V ± 0.3V power supply Interface: LVTTL 54-pin 400 mil plastic TSOP II package Pb free and Halogen free 60-ball 6.4mm x 10.1mm VFBGA package Pb free

6.3 Pin Configuration

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7. 512K CMOS SERIAL FLASH – MX25L512

7.1 General DescriptionThe MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L512 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status readcommand can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

7.2 FeaturesGeneral Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 524,288 x 1 bit structure 16 Equal Sectors with 4K byte each Any Sector can be erased individually Single Power Supply Operation 2.7 to 3.6 volt for read, erase, and program operations Latch-up protected to 100mA from -1V to Vcc +1V Low Vcc write inhibit is from 1.5V to 2.5V

Performance

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High Performance Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock

(30pF + 1TTL Load) Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and

2s(max.)/chip(512Kb) Low Power Consumption Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and

4mA(max.) at 33MHz Low active programming current: 15mA (max.) Low active erase current: 15mA (max.) Low standby current: 10uA (max.) Deep power-down mode 1uA (typical) Minimum 100,000 erase/program cycles

Software Features Input Data Format 1-byte Command code Block Lock protection The BP0~BP1 status bit defines the size of the area to be software protected against

Program and Erase instructions. Auto Erase and Auto Program Algorithm Automatically erases and verifies data at selected sector Automatically programs and verifies data at selected page by an internal algorithm

that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)

Status Register Feature Electronic Identification JEDEC 2-byte Device ID RES command, 1-byte Device ID

Hardware Features SCLK Input Serial clock input SI Input Serial Data Input SO Output Serial Data Output WP# pin Hardware write protection HOLD# pin pause the chip without diselecting the chip PACKAGE 8-pin SOP (150mil) All Pb-free devices are RoHS Compliant

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8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM)

8.1 General DescriptionThe EM63A165 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM63A165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

8.2 FeaturesFast access time from clock: 5/5.4 ns• Fast clock rate: 166/143 MHz• Fully synchronous operation• Internal pipelined architecture• 4M word x 16-bit x 4-bank• Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function• Auto Refresh and Self Refresh• 8192 refresh cycles/64ms• CKE power down mode• Single +3.3V power supply• Interface: LVTTL• 54-pin 400 mil plastic TSOP II package - Pb free and Halogen free

9. SAW FILTER

9.1 IF Filter for Audio Applications – Epcos K9656M

9.1.1 Standarts B/G D/K I L/L’

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9.1.2 Features TV IF audio filter with two channels Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75

MHz (L’- NICAM) Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz

and 33,40 MHz

9.1.3 Pin Configuration

1 Input2 Switching input3 Chip carrier - ground4 Output

5 Output

9.1.4 Frequency Response Frequency Response of Channel 1:

Frequency Response of Channel 2:

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9.2 IF Filter for Video Applications – Epcos K3958M

9.2.1 Standarts B/G D/K I L/L’

9.2.2 Features TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz Constant group delay

9.2.3 Pin Configuration1 Input2 Input - ground3 Chip - carrier ground4 Output

5 Output

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9.2.4 Frequency Response

10. POWER STAGEThe DC voltages required at various parts of the chassis and inverters are provided by an external power supply unit or produced on the chassis if an adapter is used for the supply. The 12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical switch to produce the required standby voltage. Also regulators and mosfets generate 1.8V, 3.3V and 5V and 1.26V voltages for other different parts of the chassis.

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11. IC SPECIFICATIONS

11.1 32K Smart Serial EEPROM – 24C32General DescriptionThe Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This device has been developed for advanced, low power applications such as personal communications or data acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code and data applications. The 24C32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package.

Features Voltage operating range: 4.5V to 5.5V Peak write current 3 mA at 5.5V Maximum read current 150 µA at 5.5V Standby current 1 µA typical Industry standard two-wire bus protocol, I2C compatible Including 100 kHz and 400 kHz modes Self-timed write cycle (including auto-erase) Power on/off data protection circuitry Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance

Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block 8 byte page, or byte modes available 1 page x 8 line input cache (64 bytes) for fast write loads Schmitt trigger, filtered inputs for noise suppression Output slope control to eliminate ground bounce 2 ms typical write cycle time, byte or page Up to 8 chips may be connected to the same bus for up to 256K bits total

memory Electrostatic discharge protection > 4000V Data retention > 200 years 8-pin PDIP/SOIC packages Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to

+85°C

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Pin Configuration

11.2 TL062General DescriptionLow-power JFET-input operational amplifier

Features Very Low Power Consumption Typical Supply Current . . . 200 µA (Per Amplifier) Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Common-Mode Input Voltage Range Includes VCC+ Output Short-Circuit Protection High Input Impedance . . . JFET-Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate . . . 3.5 V/µs Typ

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Pin Configuration

11.3 PI5V330

General DescriptionPericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the Company.s advanced CMOS low-power technology, achieving industry leading performance. The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is recommended for both RGB and composite video switching applications. The VideoSwitch. can be driven from a current output RAMDAC or voltage output composite video source. Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also this device has exceptionally high current capability which is far greater than most analog switches offered today. A single 5V supply is all that is required for operation. The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.

Features High-performance, low-cost solution to switch between video sources Wide bandwidth: 200 MHz Low ON-resistance: 3Ω Low crosstalk at 10 MHz: .58 dB Ultra-low quiescent power (0.1 µA typical) Single supply operation: +5.0V Fast switching: 10 ns High-current output: 100 mA Packages available: 16-pin 300-mil wide plastic SOIC (S) 16-pin 150-mil wide plastic SOIC (W) 16-pin 150-mil wide plastic QSOP (Q)

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Pin Configuration

11.4 74HCT4053

General DescriptionThe 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typicallyground).

Features Low ON resistance: 80 W (typical) at VCC - VEE = 4.5 V 70 W (typical) at VCC - VEE = 6.0 V 60 W (typical) at VCC - VEE = 9.0 V Logic level translation: To enable 5 V logic to communicate with ±5 V analog signals Typical ‘break before make’ built in Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-

A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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Pin Configuration

11.5 FMS6145General DescriptionThe FMS6145 Low-Cost Video Filter (LCVF) is intended to replace passive LC fi lters and drivers with a low-cost integrated device. Five 4th-order fi lters provide improved image quality compared to typical 2nd or 3rd-order passive solutions. The FMS6145 may be directly driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias circuitry may be used if AC-coupled inputs are required. The outputs can drive AC- or DC-coupled single (150Ω) or dual (75Ω) loads. DC coupling the outputs removes the need for output coupling capacitors. The input DC levels are offset approximately +280mV at the output.

Features Five 4th-order 8MHz (SD) fi lters Drives single,AC- or DC-coupled, video loads (2Vpp, 150Ω) Drives dual, AC- or DC-coupled, video loads (2Vpp, 75Ω) Transparent input clamping AC- or DC-coupled inputs AC- or DC-coupled outputs DC-coupled outputs eliminate AC-coupling capacitors 5V only Robust 8kV ESD protection Lead-free TSSOP-14 package

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Pin Configuration

11.6 LM1117General DescriptionThe LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve the transient response and stability.

Features Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions Space Saving SOT-223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0.2% (Max) Load Regulation 0.4% (Max) Temperature Range LM1117 0°C to 125°C LM1117I -40°C to 125°C

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Pin Configuration

11.7 ST24LC21DescriptionThe ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),

organized by 8 Bits.This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

Features 1 Mıllıon Erase/Wrıte Cycles 40 Years Data Retentıon 2.5v To 5.5v Sıngle Supply Voltage 400k Hz Compatıbılıty Over The Full Range Of Supply Voltage Two Wıre Serıal Interface I2c Bus Compatıble Page Wrıte (Up To 8 Bytes) Byte, Random And Sequentıal Read Modes Self Tımed Programmıng Cycle Automatıc Address Incrementıng Enhanced Esd/Latch Up Performances

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Pin Configuration

11.8 24LC02DescriptionThe Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically

Erasable PROM. The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.8V, with standby and active currents of only 1 A and 1 mA, respectively. The 24XX02 also has a page write capabilityfor up to 8 bytes of data. The 24XX02 is available in the standard 8-pin PDIP, surface mount OIC, TSSOP and MSOP packages and is also available in the 5-lead SOT-23 package.

Features• Single supply with operation down to 1.8V• Low-power CMOS technology- 1 mA active current typical- 1µA standby current typical (I-temp)• Organized as 1 block of 256 bytes (1 x 256 x 8)• 2-wire serial interface bus, I2C™ compatible• Schmitt Trigger inputs for noise suppression• Output slope control to eliminate ground bounce• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility• Self-timed write cycle (including auto-erase)• Page write buffer for up to 8 bytes• 2 ms typical write cycle time for page write• Hardware write-protect for entire memory• Can be operated as a serial ROM• Factory programming (QTP) available• ESD protection > 4,000V• 1,000,000 erase/write cycles• Data retention > 200 years• 8-lead PDIP, SOIC, TSSOP and MSOP packages• 5-lead SOT-23 package• Pb-free finish available• Available for extended temperature ranges:

26

- Industrial (I): -40°C to +85°C- Automotive (E): -40°C to +125°C

Pin Configuration

11.9 MAX810General DescriptionThe MAX809 and MAX810 are cost-effective system supervisor circuits designed to monitor VCC in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within 10 _sec of VCC falling through the reset voltage threshold. Reset is maintained active for a timeout period which is trimmed by the factory after VCC rises above the reset threshold. The MAX810 has an active-high RESET output while the MAX809 has an active-low RESET output. Both devices are available in SOT-23 and SC-70 packages. The MAX809/810 are optimized to reject fast transient glitches on the VCC line. Low supply current of 0.5 _A (VCC = 3.2 V) makes these devices suitable for battery powered applications.

Features Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms, 100

ms, and 140 ms) RESET Output Guaranteed to VCC = 1.0 V. Low Supply Current Compatible with Hot Plug Applications VCC Transient Immunity No External Components Wide Operating Temperature: -40°C to 105°C Pb-Free Packages are Available

27

Pin Configuration

11.10 TDA1308DescriptionThe TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a

DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

Features Operating temperature range: -40 to +85 C No switch ON/OFF clicks Short-circuit resistant signal-to-noise ratio: 110 dB total harmonic distortion: 0.001 %

Pin Configuration

11.11 MP1583General Description

The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal

28

shutdown. Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown mode the regulator draws 20µA of supply current.The MP1583 requires a minimum number of readily available external components tocomplete a 3A step down DC to DC converter solution.

Features 3A Output Current Programmable Soft-Start 100mΩ Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95% Efficiency 20µA Shutdown Mode Fixed 385KHz frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75 to 23V operating Input Range Output Adjustable From 1.22 to 21V Under Voltage Lockout Available in 8 pin SOIC Package 3A Evaluation Board Available

Pin Configuration

29

11.12 MP2112General DescriptionThe MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency without an external Schottky diode. It is ideal for powering portable equipment that powered by a single cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load current from a 2.5V to 6V input voltage. The output voltage can be regulated as low as 0.6V. The MP2112 can also run at 100% duty cycle for low dropout applications.The MP2112 is available in a space-saving 6-pin QFN package.

Features High Efficiency: Up to 95% 1MHz Constant Switching Frequency 1A Available Load Current 2.5V to 6V Input Voltage Range Output Voltage as Low as 0.6V 100% Duty Cycle in Dropout Current Mode Control Short Circuit Protection Thermal Fault Protection <0.1µA Shutdown Current Space Saving 3mm x 3mm QFN6 Package

Pin Configuration

11.13 IRF7314General Description

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.

30

Pin Configuration

12. SERVICE MENU SETTINGSIn order to reach service menu, First Press “MENU” Then press the remote control code, which is “4725”. In DTV mode, first press “MENU” and select “TV SETUP”. Then, press “4725”.

12.1. Video Setup

Panel Info <..................................> 32_LC_SAC1

Blue Background <.....>If “Menu” selected, “Blue Background” item is seen in “Feature”menu.If “Yes” selected, “Blue Background” is on and not seen in

“Feature” menuFilm Mode <.....>

If “Yes” selected, “Film Mode” feature is active.Dynamic Contrast <.....>

If “Yes” selected, “Dynamic Contrast” feature is active.Game Mode <...........>

If “Yes” selected, “Game Mode” feature is activeSRGB For PC <...........>

If “Yes” selected, PCs can use SRGB option.Dynamic Noise Reduction<...........>

If “Yes” selected, “Dynamic Noise Reduction” feature is activeWSS Option<...........>

If “Yes” selected, WSS Option can be used

12.2. AudioSetup

BG<.....>Europe

New ZellandAustraliaNo

DK<.....>I<.....>L<.....>Equalizer <.....>

If “Yes” selected, “Equalizer” item is seen in “Sound” menu.Headphone <.....>

If “Yes” selected, “Headphone” item is seen in “Sound” menu.Power On/Off Melody <.....>

If “Yes” selected, when power on/off conditions, the power on/off melody can be heard.

Dynamic Bass <.....>Value between 0 to 12Effect<.....> Value between 0 to 7Audio Delay ,offset <.....> Value between 0 to 190Audio Setup Cont...2

Carrier mute<.......> Value between 0 to 28Headphone Sound Select <.......>

Always Active SelectAlways Inactive SelectMenuAlways Main MenuAlways PIP/PAP Window

Sound Mode Detect Time <.......> Value between 0 to 255Noise Reduction Threshold <.......> Value between 0 to 255Noise Reduction Time <.......> Value between 0 to 15AVL Attack Time <.......> Value between 0 to 255AVL Release Time <.......> Value between 0 to 255

Prescales ( AVL On)FM Prescale<.......> Value between 0 to 255AM Prescale <.......> Value between 0 to 255NICAM Prescale <.......> Value between 0 to 255SCART Prescale <.......> Value between 0 to 255FAV Prescale <.......> Value between 0 to 255DTV Prescale <.......> Value between 0 to 255HDMI Prescale <.......> Value between 0 to 255YPbPr/PC Prescale <.......> Value between 0 to 255An. USB Prescale <.......> Value between 0 to 255Dig. USB Prescale <.......> Value between 0 to 255

Prescales ( AVL Off)FM Prescale<.......> Value between 0 to 255AM Prescale <.......> Value between 0 to 255NICAM Prescale <.......> Value between 0 to 255SCART Prescale <.......> Value between 0 to 255FAV Prescale <.......> Value between 0 to 255DTV Prescale <.......> Value between 0 to 255HDMI Prescale <.......> Value between 0 to 255YPbPr/PC Prescale <.......> Value between 0 to 255

An. USB Prescale <.......> Value between 0 to 255Dig. USB Prescale <.......> Value between 0 to 255

Clipping Levels ( AVL On)FM Clipping <.......> Value between 0 to 255AM Clipping <.......> Value between 0 to 255NICAM Clipping <.......> Value between 0 to 255SCART Clipping <.......> Value between 0 to 255FAV Clipping <.......> Value between 0 to 255DTV Clipping <.......> Value between 0 to 255HDMI Clipping <.......> Value between 0 to 255YPbPr/PC Clipping <.......> Value between 0 to 255An. USB Clipping <.......> Value between 0 to 255Dig. USB Clipping <.......> Value between 0 to 255

Clipping Levels ( AVL Off)FM Clipping <.......> Value between 0 to 255AM Clipping <.......> Value between 0 to 255NICAM Clipping <.......> Value between 0 to 255SCART Clipping <.......> Value between 0 to 255FAV Clipping <.......> Value between 0 to 255DTV Clipping <.......> Value between 0 to 255HDMI Clipping <.......> Value between 0 to 255YPbPr/PC Clipping <.......> Value between 0 to 255An. USB Clipping <.......> Value between 0 to 255Dig. USB Clipping <.......> Value between 0 to 255

12.3. Service Scan/Tuning Setup

First Search for L/L’ <.......>ATS Delay Time (ms) <.......> Value between 0 to +200Main Tuner Setup

Tuner TypeLC_TDTC_GXX1DThomson DTT7543XPhilips TD1318AF-3Samsung DTOs403LH172AGeneric ( Analog Only)

Control Byte <.......> Value between 0 to +255BSW1 <.......> Value between 0 to +255BSW2 <.......> Value between 0 to +255BSW3 <.......> Value between 0 to +255Low-Mid – Low Byte <.......>Low-Mid – High Byte <.......>Mid-High – Low Byte <.......>Mid-High – High Byte <.......>

S Band TOP <.......>VIF TOP <.......> Value between 0 to +15VIF TOP SECAM <.......> Value between 0 to +15VIF TOP DK<.......> Value between 0 to +15Synch Threshold<.......> Value between 0 to +40

16.4. OptionsOptions-1

Power UpStandbyLast state

TV Open ModeSource1st TVLast Tv

First APS <.......> If “Yes” selected, first time TV opens by asking APS.

APS Volume <.......> Value between 0 to +63Burn In Mode <.......>

If “Yes” selected, TV opens with Burn-In mode. This mode is used in manufacturing.

APS TestAutostore <.......>

If “Yes” selected, Channel is automatically stored.Unicode Enabled <.......>

If “Yes” selected,Unicode characters can be read in the USB Files.

Options-2Source List menu <.......>

If “Yes” selected, Sorce List Menu appears on the screen when press “source” button.

RS232 for B2B <.......> If “Yes” selected, Remote Control commandsthe TV via

RS232 and vice versa.RC Select <.......>

RC Group 1RC Group 2RC Group 3RC Group 4RC Group 5RC Group 6

Double Digit Key <.......>If “Yes” selected, Double Digit Button on RC activates.

Protection <.......> If “Yes” selected,short circuit protection activates.

Led Type <.......>1 Led 1 Color1 Led 2 Color2 Led 2 Color1 Led 3 Color2 Led 3 Color

200 Programme <.......> If “Yes” selected, totaly 200 programmes can be used.

TouchPad <.......> If “Yes” selected, TouchPad can be used.

Teletext OptionsTXT Darkness <.......> Value between 0 to +63TXT Type <.......>

Fasttext&ToptextNoDefaultFastextToptext

TXT Language <.......>MenuWest East CyrillicTurk/GreArabicPersianAuto

No Txt Warning <.......>If “Yes” selected, “No Txt Transmission” warning appears on

the screen when pressing txt button from RC.Txt Subtitle <.......>

If “Yes” selected, Teletext subtitles can be seen.Optional Features

Default Zoom <.......>Menu16:94:3Panaromic14:9 Zoom

Menu Timeout <.......>Menu15 Sec30 Sec60 SecNo Time

Backlight <.......>If “Yes” selected, “Backlight” feature is active.

100 Step Slider <.......>If “Yes” selected, 64 step sliders will become 100 step sliders.

Analog USB Enabled <.......>If “Yes” selected, “Analog USB” option is active.

Menu Double Size <.......>If “Yes” selected, menu sizes increases.

CEC Enable <.......>If “Yes” selected, “CEC” feature is active.

Digital USB Hotplug <.......>If “Yes” selected, “Digital USB Hotplug” feature is active.

PIP OptionsPip <......>

AV PIPNo PIPPC PIP

Hotel Options <......>Hotel TV <......>

If “Yes” selected, “Hotel TV” feature is active.IR Smartloader <......>

If “Yes” selected, “IR Smartloader” feature is active.

16.5. External Source SettingsTV <.......>DTV <.......>Ext 2 <.......>Ext 2 S <.......>FAV <.......>BAV <.......>S-Video <.......>HDMI 1 <.......>HDMI 2 <.......>HDMI 3 <.......>HDMI 4 <.......>YPbPr <.......>PC <.......>

16.6. PresetUser Ad.jADC Adj.Service Adj.All Adj.Init Factory Channels.

16.7. NVM EditNVM-edit addr. (hex)NVM-edit data (hex)NVM-data dec

16.8. ProgrammingHDMI DDC Update Mode <.......>HDCP Key Update Mode <.......>Software Bypass <.......>

If “On” selected, speaker effects are bypassed.

LVDS Clock Step <.......> Value between 0 to +255Memory Clock Step <.......> Value between 0 to +255DTV Download <.......>

If “On” selected, DTV software can be updated from SCART.

DSUB9 Download <.......> If “On” selected, DTV software can be updated from DSUB9.

16.9. DiagnosticEeprom I2CTuner I2CIF I2CHDMI I2CDTV RS232

16.10. Product Info

13. SOFTWARE UPDATE DESCRIPTION

13.1 17MB25 Analog Part Software Update With Bootloader Procedure

1.1 The File Types Used By The Bootloader

All file types that used by the bootloader software are listed below:

1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920 Kb.

2. The Config Binary File : It has “.cin extension and it is the config of the tv application. Its size may be 64 Kb or a few times 64 Kb.

3. The Test Script File : It has “.txt” extension and it is the test script that is parsed and executed by the bootloader. It don’t have to be any times of 64 Kb.

4. The Test Binary File : It has “.tin” extension and it is used and written by the test groups. It is run to understand the problem part of the hardware.

Alltough a file that is used by the bootloader can be had any one of these extensions, its name has to be “VESTEL_S” and it has to be located in the root directory of the usb device.

1.2 Usage of The Bootloader1. The starting to pass through : The chassis is only powered up.2. The starting to download something : When chassis is powered up the menu key has to be pushed.Before the chassis is powered up and if any usb device is plugged to the usb port, the programme is downloaded from usb firstly.Any usb device is plugged to usb port , user must open hyperterminal in the pc and connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c connectors. Serial connection settings are listed below:

- Bit per second: 115200 - Data bits: 8

- Parity: None- Stop bits: 1- Flow control: None

In this case the bootloader sofware puts “C” character to uart. After repeating “C” characters are seen in the hyperterminal user can send any file to chassis by selecting Transfer -> Send File menu item and choosing “1K Xmodem” from protocol section.

Figure 1. The Sample Output Before Sending The File

2. EEProm update To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.Serial connection settings are listed below:

- Bit per second: 9600 - Data bits: 8 - Parity: None- Stop bits: 1- Flow control: None

Programming menu item is choosed in the service menu and switch “HDCP Key Update Mode” from off to on.

Figure 2. The Programming Service Menu

After then you must see Xmodem menu in the hyperterminal.To download hdcp key press k or to download eeprom content press w.

Figure 3. Xmodem Menu

If the repeated “C” characters are seen you can transfer file content via select Transfer->Send File and choose “Xmodem” protocol and click the “Send” button.

Figure 4. The Starting To Send

16.2 17MB25 HDCP key upload procedure.

1) Turn on TV set.2) Open a COM connection using fallowing parameters and select ISP COM Port

NoBaud Rate: 9600 bpsData Bits: 8Stop Bits: 1Parity: NoneFlow Control: None

3) Enter service menu by pressing “4” “7” “2” 5” consecutively while main menu is open

4) Select “9. Programming”5) Select “HDMI HDCP Update Mode” yes.6) On Hyper Terminal Window press “k”7) Click on send file under Transfer Tab.8) Select Xmodem and choose the HDCP key to be uploaded.9) Press send button10)Restart TV set

13.3 17MB25 Digital Software Update From SCART

Adjusting DTV Download Mode: 1. Power on the TV. 2. Exit the Stby Mode.3. Enter the “Tv Menu”. 4. Enter “4725” for jumping to “Service Settings”. 5. Select “8. Programming” step. 6. Change “6. DTV Download” to “On”. 7. Switch to the Stby mode.

Adjusting HyperTerminal: 1. Connect the “MB25 SCART Interface” to SCART1 (bottom SCART plug). 2. Also connect the “MB25 SCART Interface” to PC.3. Open “HyperTerminal”.4. Determine the “COM” settings listed and showed below.

Bit per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None

COM Properties Window

6. Click “OK”.

Software Updating Procedure1. In the HyperTerminal Menu, click the “Connect” button. 2. Exit the Stby Mode.3. The “Space” button on the keyboard must be pressed, when the following window can be seen.

Selection Window

4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with Xmodem”.5. Repeating “C” characters are seen in the “HyperTerminal” menu.

The Sample Output Before Sending The File

6. Click the “Send” button on the HyperTerminal7. Select the “Filename xxxx_slot1.img” using “Browse”.8. Choose the “1K Xmodem” from “Protocol” option.

Selection of File

File and Protocol Selection Window

Note: In the Software updating Procedure section, when the first “C” character is seen, the filename selection process must be finished before 10 seconds. If the process can not be finished, the file sending operation will be cancelled. The following figure shows this situation.

Capture of Receving Data Failing

9. When sending the file the following window must be seen.

Capture of Sending Process

10. After the sending process the following HyperTerminal window must be seen.

Capture of End of The Sending Process

11. For sending second program file, the Software Updating Procedure must be repeated from the step X. Select the “Filename xxxx_slot2.img” using “Browse”. 12. After sending the second program file, the Software Updating Procedure will be succesful.

Note: After the File Sending Process, 1. Upgrade Application with FUM2. Upgrade Application with Xmodem, options must be seen.

End of The Sending Process

Checking Of The New Software 1. Turn off and on the TV.2. Enter the “Setup” submenu in the “DTV Menu”.3. Choose the “Configuration” option.4. For controlling new software, check the “Receiver Upgrade” option.

13.4 17MB25 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.

1. Copy the bin file, including higher version than the software loaded in flash, into the USB flash memory root directory. This file should be named up.bin.

2. Insert the USB disk.3. Digital module performs version and CRC check. If version and CRC check is

successful, then a message prompt appears to notify user about new version. If the user confirms loading of new version, upgrade.bin file is written into flash unused slot.

4. Digital module disables the previous software in the flash and then a system reset is performed.

5. After the reset, digital module starts with new software.

Revert operation:

With revert operation, it is possible to downgrade the software.Revert operation is very similar to upgrade process. In the revert operation, file name should be f_up.bin. Also user confirmation is not asked.

1. Copy the bin file into the USB flash memory root directory. This file should be named force_upgrade.bin.

2. Insert the USB disk.3. A lower version than the software in flash can be loaded with revert operation.

Digital module performs only CRC check. If CRC check is successful, then force_upgrade.bin file is written into flash unused slot.

4. Digital module disables the previous software in the flash.5. A message prompt is displayed to notify user about end of revert process. 6. Power off/on is required to start digital module with the new software.

For controlling new software, check the “Receiver Upgrade” option.

New ZellandAustraliaNo

DK<.....>I<.....>L<.....>Equalizer <.....>

If “Yes” selected, “Equalizer” item is seen in “Sound” menu.Headphone <.....>

If “Yes” selected, “Headphone” item is seen in “Sound” menu.Power On/Off Melody <.....>

If “Yes” selected, when power on/off conditions, the power on/off melody can be heard.

Dynamic Bass <.....>Value between 0 to 12Effect<.....> Value between 0 to 7Audio Delay ,offset <.....> Value between 0 to 190Audio Setup Cont...2

Carrier mute<.......> Value between 0 to 28Headphone Sound Select <.......>

Always Active SelectAlways Inactive SelectMenuAlways Main MenuAlways PIP/PAP Window

Sound Mode Detect Time <.......> Value between 0 to 255Noise Reduction Threshold <.......> Value between 0 to 255Noise Reduction Time <.......> Value between 0 to 15AVL Attack Time <.......> Value between 0 to 255AVL Release Time <.......> Value between 0 to 255

Prescales ( AVL On)FM Prescale<.......> Value between 0 to 255AM Prescale <.......> Value between 0 to 255NICAM Prescale <.......> Value between 0 to 255SCART Prescale <.......> Value between 0 to 255FAV Prescale <.......> Value between 0 to 255DTV Prescale <.......> Value between 0 to 255HDMI Prescale <.......> Value between 0 to 255YPbPr/PC Prescale <.......> Value between 0 to 255An. USB Prescale <.......> Value between 0 to 255Dig. USB Prescale <.......> Value between 0 to 255

Prescales ( AVL Off)FM Prescale<.......> Value between 0 to 255AM Prescale <.......> Value between 0 to 255NICAM Prescale <.......> Value between 0 to 255SCART Prescale <.......> Value between 0 to 255FAV Prescale <.......> Value between 0 to 255DTV Prescale <.......> Value between 0 to 255HDMI Prescale <.......> Value between 0 to 255YPbPr/PC Prescale <.......> Value between 0 to 255

An. USB Prescale <.......> Value between 0 to 255Dig. USB Prescale <.......> Value between 0 to 255

Clipping Levels ( AVL On)FM Clipping <.......> Value between 0 to 255AM Clipping <.......> Value between 0 to 255NICAM Clipping <.......> Value between 0 to 255SCART Clipping <.......> Value between 0 to 255FAV Clipping <.......> Value between 0 to 255DTV Clipping <.......> Value between 0 to 255HDMI Clipping <.......> Value between 0 to 255YPbPr/PC Clipping <.......> Value between 0 to 255An. USB Clipping <.......> Value between 0 to 255Dig. USB Clipping <.......> Value between 0 to 255

Clipping Levels ( AVL Off)FM Clipping <.......> Value between 0 to 255AM Clipping <.......> Value between 0 to 255NICAM Clipping <.......> Value between 0 to 255SCART Clipping <.......> Value between 0 to 255FAV Clipping <.......> Value between 0 to 255DTV Clipping <.......> Value between 0 to 255HDMI Clipping <.......> Value between 0 to 255YPbPr/PC Clipping <.......> Value between 0 to 255An. USB Clipping <.......> Value between 0 to 255Dig. USB Clipping <.......> Value between 0 to 255

16.3. Service Scan/Tuning SetupFirst Search for L/L’ <.......>ATS Delay Time (ms) <.......> Value between 0 to +200Main Tuner Setup

Tuner TypeLC_TDTC_GXX1DThomson DTT7543XPhilips TD1318AF-3Samsung DTOs403LH172AGeneric ( Analog Only)

Control Byte <.......> Value between 0 to +255BSW1 <.......> Value between 0 to +255BSW2 <.......> Value between 0 to +255BSW3 <.......> Value between 0 to +255Low-Mid – Low Byte <.......>Low-Mid – High Byte <.......>Mid-High – Low Byte <.......>Mid-High – High Byte <.......>

S Band TOP <.......>VIF TOP <.......> Value between 0 to +15VIF TOP SECAM <.......> Value between 0 to +15VIF TOP DK<.......> Value between 0 to +15Synch Threshold<.......> Value between 0 to +40

16.4. OptionsOptions-1

Power UpStandbyLast state

TV Open ModeSource1st TVLast Tv

First APS <.......> If “Yes” selected, first time TV opens by asking APS.

APS Volume <.......> Value between 0 to +63Burn In Mode <.......>

If “Yes” selected, TV opens with Burn-In mode. This mode is used in manufacturing.

APS TestAutostore <.......>

If “Yes” selected, Channel is automatically stored.Unicode Enabled <.......>

If “Yes” selected,Unicode characters can be read in the USB Files.

Options-2Source List menu <.......>

If “Yes” selected, Sorce List Menu appears on the screen when press “source” button.

RS232 for B2B <.......> If “Yes” selected, Remote Control commandsthe TV via

RS232 and vice versa.RC Select <.......>

RC Group 1RC Group 2RC Group 3RC Group 4RC Group 5RC Group 6

Double Digit Key <.......>If “Yes” selected, Double Digit Button on RC activates.

Protection <.......> If “Yes” selected,short circuit protection activates.

Led Type <.......>1 Led 1 Color1 Led 2 Color2 Led 2 Color1 Led 3 Color2 Led 3 Color

200 Programme <.......> If “Yes” selected, totaly 200 programmes can be used.

TouchPad <.......> If “Yes” selected, TouchPad can be used.

Teletext OptionsTXT Darkness <.......> Value between 0 to +63TXT Type <.......>

Fasttext&ToptextNoDefaultFastextToptext

TXT Language <.......>MenuWest East CyrillicTurk/GreArabicPersianAuto

No Txt Warning <.......>If “Yes” selected, “No Txt Transmission” warning appears on

the screen when pressing txt button from RC.Txt Subtitle <.......>

If “Yes” selected, Teletext subtitles can be seen.Optional Features

Default Zoom <.......>Menu16:94:3Panaromic14:9 Zoom

Menu Timeout <.......>Menu15 Sec30 Sec60 SecNo Time

Backlight <.......>If “Yes” selected, “Backlight” feature is active.

100 Step Slider <.......>If “Yes” selected, 64 step sliders will become 100 step sliders.

Analog USB Enabled <.......>If “Yes” selected, “Analog USB” option is active.

Menu Double Size <.......>If “Yes” selected, menu sizes increases.

CEC Enable <.......>If “Yes” selected, “CEC” feature is active.

Digital USB Hotplug <.......>If “Yes” selected, “Digital USB Hotplug” feature is active.

PIP OptionsPip <......>

AV PIPNo PIPPC PIP

Hotel Options <......>Hotel TV <......>

If “Yes” selected, “Hotel TV” feature is active.IR Smartloader <......>

If “Yes” selected, “IR Smartloader” feature is active.

16.5. External Source SettingsTV <.......>DTV <.......>Ext 2 <.......>Ext 2 S <.......>FAV <.......>BAV <.......>S-Video <.......>HDMI 1 <.......>HDMI 2 <.......>HDMI 3 <.......>HDMI 4 <.......>YPbPr <.......>PC <.......>

16.6. PresetUser Ad.jADC Adj.Service Adj.All Adj.Init Factory Channels.

16.7. NVM EditNVM-edit addr. (hex)NVM-edit data (hex)NVM-data dec

16.8. ProgrammingHDMI DDC Update Mode <.......>HDCP Key Update Mode <.......>Software Bypass <.......>

If “On” selected, speaker effects are bypassed.

LVDS Clock Step <.......> Value between 0 to +255Memory Clock Step <.......> Value between 0 to +255DTV Download <.......>

If “On” selected, DTV software can be updated from SCART.

DSUB9 Download <.......> If “On” selected, DTV software can be updated from DSUB9.

16.9. DiagnosticEeprom I2CTuner I2CIF I2CHDMI I2CDTV RS232

16.10. Product Info

17. SOFTWARE UPDATE DESCRIPTION

16.1 17MB25 Analog Part Software Update With Bootloader Procedure

1.1 The File Types Used By The Bootloader

All file types that used by the bootloader software are listed below:

1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920 Kb.

2. The Config Binary File : It has “.cin extension and it is the config of the tv application. Its size may be 64 Kb or a few times 64 Kb.

3. The Test Script File : It has “.txt” extension and it is the test script that is parsed and executed by the bootloader. It don’t have to be any times of 64 Kb.

4. The Test Binary File : It has “.tin” extension and it is used and written by the test groups. It is run to understand the problem part of the hardware.

Alltough a file that is used by the bootloader can be had any one of these extensions, its name has to be “VESTEL_S” and it has to be located in the root directory of the usb device.

1.2 Usage of The Bootloader1. The starting to pass through : The chassis is only powered up.2. The starting to download something : When chassis is powered up the menu key has to be pushed.Before the chassis is powered up and if any usb device is plugged to the usb port, the programme is downloaded from usb firstly.Any usb device is plugged to usb port , user must open hyperterminal in the pc and connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c connectors. Serial connection settings are listed below:

- Bit per second: 115200 - Data bits: 8

- Parity: None- Stop bits: 1- Flow control: None

In this case the bootloader sofware puts “C” character to uart. After repeating “C” characters are seen in the hyperterminal user can send any file to chassis by selecting Transfer -> Send File menu item and choosing “1K Xmodem” from protocol section.

Figure 1. The Sample Output Before Sending The File

2. EEProm update To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.Serial connection settings are listed below:

- Bit per second: 9600 - Data bits: 8 - Parity: None- Stop bits: 1- Flow control: None

Programming menu item is choosed in the service menu and switch “HDCP Key Update Mode” from off to on.

Figure 2. The Programming Service Menu

After then you must see Xmodem menu in the hyperterminal.To download hdcp key press k or to download eeprom content press w.

Figure 3. Xmodem Menu

If the repeated “C” characters are seen you can transfer file content via select Transfer->Send File and choose “Xmodem” protocol and click the “Send” button.

Figure 4. The Starting To Send

16.2 17MB25 HDCP key upload procedure.

1) Turn on TV set.2) Open a COM connection using fallowing parameters and select ISP COM Port

NoBaud Rate: 9600 bpsData Bits: 8Stop Bits: 1Parity: NoneFlow Control: None

3) Enter service menu by pressing “4” “7” “2” 5” consecutively while main menu is open

4) Select “9. Programming”5) Select “HDMI HDCP Update Mode” yes.6) On Hyper Terminal Window press “k”7) Click on send file under Transfer Tab.8) Select Xmodem and choose the HDCP key to be uploaded.9) Press send button10)Restart TV set

16.3 17MB25 Digital Software Update From SCART

Adjusting DTV Download Mode: 1. Power on the TV. 2. Exit the Stby Mode.3. Enter the “Tv Menu”. 4. Enter “4725” for jumping to “Service Settings”. 5. Select “8. Programming” step. 6. Change “6. DTV Download” to “On”. 7. Switch to the Stby mode.

Adjusting HyperTerminal: 1. Connect the “MB25 SCART Interface” to SCART1 (bottom SCART plug). 2. Also connect the “MB25 SCART Interface” to PC.3. Open “HyperTerminal”.4. Determine the “COM” settings listed and showed below.

Bit per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None

COM Properties Window

6. Click “OK”.

Software Updating Procedure1. In the HyperTerminal Menu, click the “Connect” button. 2. Exit the Stby Mode.3. The “Space” button on the keyboard must be pressed, when the following window can be seen.

Selection Window

4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with Xmodem”.5. Repeating “C” characters are seen in the “HyperTerminal” menu.

The Sample Output Before Sending The File

6. Click the “Send” button on the HyperTerminal7. Select the “Filename xxxx_slot1.img” using “Browse”.8. Choose the “1K Xmodem” from “Protocol” option.

Selection of File

File and Protocol Selection Window

Note: In the Software updating Procedure section, when the first “C” character is seen, the filename selection process must be finished before 10 seconds. If the process can not be finished, the file sending operation will be cancelled. The following figure shows this situation.

Capture of Receving Data Failing

9. When sending the file the following window must be seen.

Capture of Sending Process

10. After the sending process the following HyperTerminal window must be seen.

Capture of End of The Sending Process

11. For sending second program file, the Software Updating Procedure must be repeated from the step X. Select the “Filename xxxx_slot2.img” using “Browse”. 12. After sending the second program file, the Software Updating Procedure will be succesful.

Note: After the File Sending Process, 1. Upgrade Application with FUM2. Upgrade Application with Xmodem, options must be seen.

End of The Sending Process

Checking Of The New Software 1. Turn off and on the TV.2. Enter the “Setup” submenu in the “DTV Menu”.3. Choose the “Configuration” option.4. For controlling new software, check the “Receiver Upgrade” option.

16.4 17MB25 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.

1. Copy the bin file, including higher version than the software loaded in flash, into the USB flash memory root directory. This file should be named up.bin.

2. Insert the USB disk.3. Digital module performs version and CRC check. If version and CRC check is

successful, then a message prompt appears to notify user about new version. If the user confirms loading of new version, upgrade.bin file is written into flash unused slot.

4. Digital module disables the previous software in the flash and then a system reset is performed.

5. After the reset, digital module starts with new software.

Revert operation:

With revert operation, it is possible to downgrade the software.Revert operation is very similar to upgrade process. In the revert operation, file name should be f_up.bin. Also user confirmation is not asked.

1. Copy the bin file into the USB flash memory root directory. This file should be named force_upgrade.bin.

2. Insert the USB disk.3. A lower version than the software in flash can be loaded with revert operation.

Digital module performs only CRC check. If CRC check is successful, then force_upgrade.bin file is written into flash unused slot.

4. Digital module disables the previous software in the flash.5. A message prompt is displayed to notify user about end of revert process. 6. Power off/on is required to start digital module with the new software.

For controlling new software, check the “Receiver Upgrade” option.

31

12. BLOCK DIAGRAMS

12.1 General Block Diagram

32

12.2 Integrated DVB-T Receiver Block Diagram

33

12.3 MSTAR Block Diagram

VIFM

10V10u

C363

21

10V10u

C361

21

10V10uC3602

1

10V100nC137

2

1

10kR505

21 IF_AGC_DVB

2u2

L104

21

16V10n

C546

21

R12747R

21

47RR126

21

C134100n10V

2

1

10V100n

C132

21

10V100n

C131

21

10V100n

C129

21

1kR624

21

50V47pC5872

1

50V47pC5862

1

RF_AGC

1N4148

D12121

12kR111

21

BC848BQ116

3

2

1

74HCT4053U115

1615141312111098

7654321 2Y1

2Y03Y13Z3Y0EVEEGND S3

S2S1

1Y01Y11Z2Z

VCC

47RR125

21

56RR680

21

5V_TUN

ADDRESS_SEL_TUNER

5V_TUN

ANALOG_IF

5V_TUN

ADDRESS_SEL_TUNER

33V_TUNER

5V_TUN

FDN336P

Q102

3

2

1

BC848BQ115

3

2

1

4R7R482

21

50V1u

C532 2

1

ANT_CTRL

ANALOG_IF

4k7

R252

21

1k

R623

21

MST6WB7GQ-3U138

73

72

62

63

64

65

66

67

68

69

70

71 GND_RXV

VIFP

VIFM

SIFM

SIFP

GND_RXS

AVDD_RXS

VR12

VR27

AVDD_MPLL

AVDD_RXV

TAGC

4

17MB25

ÖNDER GENÇ

ANALOG IF 1114-28-2008_16:47

87654321

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A3PROJECT NAME :VESTELSCH NAME :

DRAWN BY :

SHEET:

K9656M

Z101

41

53

2 IN2GND

OUT2

IN1 OUT1

SIF_CTL

K3958M

Z102

41

5

3

2 IN2GND

OUT2

IN1 OUT1

SIFP

SIFM

SIFP

SIFM

SCL_TUNER

SDA_TUNER

SCL_TUNER

33V_TUNER

SDA_TUNER

S102 21

T_AGC

T_AGC

SCL_TUN

SCL_TUN

SDA_TUN

SCL_TUNER

SDA_TUNER

S101 21

SDA_TUN

5V_VCC

10V100n

C128

21

22kR595

21

DIGITAL_IF_P

DIGITAL_IF_N

2R1

TH101

21

16V47uC520

2

1

33V_TUNER

3V3_VCC

BF799Q144

3

2

1

10R

R384

21

1k2R483

21

16V10n

C545

21

100n

10V

2 1

C135

5V_TUN

S1052 1

330R

F11621

5V_TUN

3V3_VCC

SCL_TUN_DVB

SDASDA_TUN_DVB

5V_TUN

BSN20

Q140

3

2

1

22k

R594

21

5V_TUN

16V10n

C547

21

SCL

1kR622

21

R504

10k

21

VIFM

VIFPANALOG_IF

680R

R735

21

IF_AGC_DVB_IN

IF_AGC_DVB_IN

IF_AGC_DVB_IN

C136100n10V

2

1

5V_TUN

8V_VCC

8V_VCC

R501

10k

21

5V_TUN

5V_VCC

10V

10u

C364 2

1

4k7R253

21

RF_AGC_A

RF_AGC_A

S103 21

6k8

R473

21

6k8

R474

21

3k3

R231

21

BA782

D1452 1

16V47uC448

2

1

10V10u

C467

21

10V100nC5102

1

16V47uC600

2

1

330R

F18421

330R

F18521

330R

F18621

100kR209

21

100k

R210

21

RF_AGC

L114

1u

21

1u

L11121

10kR503

21

TP151

1

LM1117U123

4

3 2

1

GND

OUTIN

VOUT

VIFP

TU101

DTOS403LH172A

11

10

9

8

7

6

5

4

3

2

1BA

RF_AGC

SAS

SCL

SDA

AIF_OUT

+5V

IF_AGC

VT

IFOUT+

IFOUT-

TU102

TDTC-G101D

12

11

10

9

8

7

6

5

4

3

2

1ANT_PWR

B1

RF_AGC

SCL

SDA

B2

NC

AS

IF_AGC

DIF2

DIF1

AIF

4k7R254

21

10V

100n

C130 2

1

S10421 IDTV_SW

6V3220uC6542

1

3V3_STBY330R

F18721

10kR502

21

OVER_CUR_DETECT

10V10uC3592

1

F234

330R

21

1u

L117

21

DIGITAL_IF_N

DIGITAL_IF_P

50V

47p

C675 2

1

RF_AGCRF_AGC_DVB

50V220pC5972

1 50V

100p

C676 2

1

10V220nC1332

1

R408

330R

21

1kR460

21

75RR380

ACT_ANT

N.C.

ACT_ANT

ACTIVE ANTENNA

ACT_ANT

N.C.

WARNING!!! This part must be close to chip

Connect if "33V Integrated Tuner" is used!AGC AND I2C SWITCH PART

Near Tunersupply pin

WARNING!!! This part must be close to chip

WARNING!!! Saw filter outputs must be close the chip

This part must be placed near the tuner

TUNER SUPPLY OPSION

!!!En az 1.8 cm2 altta ve üstte soðutma alaný býrakýlmalý.

NEAR THE TUNER

N.C.

Samsung/Thomson

LG

25V220nC658

C652

27p50V

21

C649

27p50V

21

F246

600R

21

600R

F24521

R584100R

8

7

6

5 4

3

2

1

R2

R3

R1

R4

YPBPR_AUD_L_IN

R349100R

21

D117

C5V6

2 1

R682

33k

21

50V

220p

C1142

1

R64075R 21

C112

220p

50V

21

D114

C5V6

21

C480

1n50V

21

C479

1n50V

21

C478

1n50V

21

C103

220p50V

2 1

75RR638

21

JK102

5

4 3

21

10k

R506

21

VGA_G

VGA_R

50V

27p

C438 2

1

VGA_B

2k2

R712

21

50V

27p

C439 2

1

10V100nC1382

1

LINE_R_OUT

17MB25

ONDER GENC

A/V INTERFACE 1124-28-2008_15:57

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DRAWN BY :

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D172

C5V6

2 1

C5V6

D1152 1

10kR120

21

SC1_AUD_R_OUT

75RR644

2 1

NUP4004M5

D103

543

2

1

NUP4004M5

D106

543

2

1

50V1n

C489

21

VGA_DDC_5V

TP102

1

TP104

1

TP103

1

10k

R507

21

10k

R511

21

NUP4004M5

D102

543

2

1

2k2

R711

21

BAV70

D146

3

21

VGA_DDC_5V

CN118

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

C5V6

D169

21

NUP4004M5

D101

543

2

1

50V1n

C473

2 1

TP105

1

ST24LC21

U1128

7

6

5 4

3

2

1A0

A1

A2

GNDSDA

SCL

WP

VCC

R64175R2 1

SC1_AUD_L_OUT

50V220p

C106

21

SC1_CVBS_OUT

C107

220p50V

2 1

4k7R255

21

SC1_PIN8

50V1n

C475

21

D112

C5V6

2 1

C5V6

D113

21

50V

220p

C1112

1

SPDIF_OUT_COAXIAL

50V

220p

C105 2

1

47RR128

2 1

600R

F20421

F205

600R

21

F208

600R

21

600R

F21021

600R

F21121

SC101

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

SCART LT1

F196

600R

21

BC848BQ117

3

2

1

600R

F20921

600R

F19821

S_VIDEO_C_IN S_VIDEO_Y_IN

SC1_CVBS_IN

SC1_G

50V

27p

C437 2

1

50V

27p

C441

21

C440

27p50V

2 1

RCA_Y

SC1_R50V220p

C104

2 1

SC1_B

SC1_AUD_L_INC477

1n50V

21

SC1_AUD_R_IN600R

F19421

SC1_FB

C115

220p50V

21

F207

600R

2 1

5V_TUN

600R

F215

21

D105

NUP4004M55 4 3

2

1

50V1n

C474

2 1

F212

600R

21

50V

220p

C113

21

F216

600R

2 1

SAV_CVBS

5V_VCC

33k

R683

21

C442

27p50V

2 1

RCA_PR

RCA_PBR63775R 21

R63975R

21

C5V6

D1162 1

TX/SDA_SC

RX/SCL_SC

10V10u

C365

21

F197

600R

21

LINE_L_OUT

SAV_AUD_L_IN

SAV_AUD_R_IN

75RR643

2 1

50V220p

C108

2 1

10V100n

C140

2 1

TP101 1

5V_SPDIF

10V

10u

C366 2

1

C116

220p

50V

21

VGA_HSNC

VGA_VSNC

JK106

65

43

21YLW

WHT

RED

YPBPR_AUD_R_IN

JK104

2

4

65

3

1

BLK

RED

WHT

JK101

2

4

65

3

1

RED

BLU

GRN

SPDIF_OUT100RR464

21

100RR213

21

100RR216

21

100RR217

21

50V1n

C488

21

100RR219

21

C484

1n50V

21

47RR129

21

SPDIF_OUT_COAXIAL

4k7

R804

21

4k7

R242

21

5V_SPDIF

330R

F118215V_VCC

10V100n

C627

21

10V100n

C229

21

1kR400

21

S21621

PROG_END111

C5V6

2 1

D159

C5V6

21

C5V6

D158

21

C15V

D1402 1

22kR596

21

600R

F19521

C628

100n10V

2 1

R87222k

21

600R

F24321

F244

600R

21

25V

10u

C640 2

1

D163

C15V

21

10kR861

21

3V3_VCC

12V_VCC4A/24VDC

FS10121

DVD_AUD_R_IN

DVD_AUD_L_IN

50V27p

C648

21

50V27p

C650

21

DVD_SPDIF

R642

75R

21

C651

27p50V

21

DVD_C_IN

DVD_Y_IN

DVD_IR

DVD_SENSE

R8054k7

21

F242

600R

21

JK105

43

21WHT

RED

D168

C5V6

21

C5V6

D1732 1

CN111

12

11

10

9

8

7

6

5

4

3

2

1

C5V6

D1702 1

C5V6

D171

21

TP240

1

C18V

D176

VGA CONNECTOR

SCART1 INPUT

VGA INPUT

YPBPR INPUT

SUBWOOFER OUTPUT

LINE OUTPUT

S-VIDEO INPUT

COAXIAL SPDIF OUTPUT

YPBPR/PC LINE INPUT

SPDIF OUTPUT INTERFACE

SIDE AV INPUT

DVD CONNECTION

!

16V1u

C342

16V1uC327

GAIN_SW1

75RR879

2 1

4k7R806

21 2N7002Q154

3

2

1

3k3R802

21 3k3R801

2 1

SOGIN0

SOGIN0

DSP_CH2_L

DSP_CH2_R

C494

1n50V

21

16V1u

C340

8V_VCC

F219

600R

21

SC_1_R 20kR739

21

16V1u

C335

SC1_AUD_R_OUT

SC1_AUD_L_OUT

R73820k

21

SC1_L

10V10u

C374

2 1

V+

V+

V+

R73720k

21

R52210k

21

POP_MUTEBC848BQ121

3

2

1

LINE_R_OUT

16V1u

C330

10kR521

2 1

POP_MUTE

47RR153

21 LINE_L_OUT

20kR736

21

LINE_OUT_LV+

10V10u

C369

2 1

R66775R

2 1

R60722k

21

10kR520

21

10kR519

21

R51810k

21

R51710k

21

R51610k

21

10kR515

21

R51410k

21

R51310k

21

R66375R

2 1

C445

27p50V

21

10V

100n

C145

2 1

330R

F120

21

VGA_G

VGA_B

C429

47n16V

21

C430

47n16V

21

75RR658

2 1

75RR659

2 1

50V1n

C491

21

16V47n

C431

21

75RR660

2 1

SW_PR RIN2P

R65575R

2 1

C426

47n16V

21

C490

1n50V

21

R65675R

2 1

R65775R

2 1

R403470R

21

47RR147

21

16V47n

C427

21

R14847R

21

47RR149

21

16V47n

C428

21

R14647R 21

75RR654

21

C1

R65375R

21

47RR145

21S_VIDEO_C_IN

R14447R

21

75RR650

21

ONDER GENC

17MB25

A/V INTERFACE 1134-28-2008_15:57

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B

C

D

E

F

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A

B

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D

E

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DRAWN BY :

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S106 21

R41922k 21

22kR420

21

16V

10n

C554

21

C555

10n

16V

21

C553

10n

16V

21

16V10n

C550

2 1

33k

R684

21

75RR646

21

100R

R221

21

470R

R402

21

SC1_CVBS_OUT

16V1u

C344

C498

1n50V

21

C499

1n50V

21

50V1n

C492

21

50V1n

C493

21

50V1n

C495

21

50V1n

C496

21

50V1n

C497

21

16V1u

C337

16V1u

C343

16V1u

C339

16V1u

C336

16V1u

C341

16V1u

C338

SC1_AUD_R_IN

10V100n

C148

2 1

10V100n

C149

21

100RR351

21CVBS0_OUT

10V100n

C147

2 1

5V_VCC

C548

10n

16V

21

16V

10n

C549

21

16V

10n

C552

21

R41622k 21

R41822k 21

22kR417

21

22kR414

21

R41322k 21

22kR415

21

SC1_AUD_L_IN

YPBPR_AUD_L_IN

YPBPR_AUD_R_IN

33kR685

21V+

AVDD_AU

BC848BQ119

3

2

1

C551

10n16V

2 1

47RR134

21

R674

39k

21

R467

15k

21

C421

47n16V

21

R13347R

21

R13747R

21

47RR138

21

C417

47n16V

21

R13947R

21

R14047R

21

AVDD_AU

LINE_IN_0R

LINE_IN_0L

LINE_IN_0R

LINE_IN_0L

LINE_IN_1L

LINE_IN_1R

LINE_IN_1L

LINE_IN_1RLINE_IN_2L

LINE_IN_3R LINE_IN_2L

LINE_IN_3L

LINE_IN_2R

LINE_IN_3R

LINE_IN_3L

R65175R 21

R14247R

21 Y0

C0DVD_C_IN 47RR143

21

Y1S_VIDEO_Y_IN

16V47n

C434

21

16V47n

C432

21

16V47n

C423

21

SC1_CVBS_IN

16V47n

C435

21

16V47n

C433

2147RR141

21

C425

47n16V

21

75RR664

2 1

DVB_CVBS

CVBS2

CVBS3

75RR652

21 C422

47n16V

21

C424

47n16V

21

R64975R

2 1

R51210k

21

R13247R

21

CVBS1

CVBS2

CVBS3

RIN0P

BIN0P

GIN0P

SC1_B

SC1_G

16V47n

C418

21

75RR666

2 1

SC1_R

C419

47n16V

21

RIN0P

GIN0P

BIN2P

GIN2P

SOGIN2

SW_PB

SW_YS111 21

RCA_PB

S107 21

S112 21

RCA_YS108 21

SW_Y

1kR627

21

DVB/YPBPR_SW

RCA_PR

S110 21

S109 21

SW_PR

C416

47n

16V

21

Y0

C0

Y1

C1

RIN2P

GIN2P

SOGIN2

BIN2P

BIN0P

SOGIN1

GIN1P

RIN1P

BIN1P 10V100n

C150

2110V100n

C151

21

VGA_VSNC

VGA_HSNC

VGA_R

BIN1P

GIN1P

SOGIN1

RIN1P

PI5V330U129

12345678

161514131211109DC

S2CS1CDDS2DS1DENVCC

GNDDBS2BS1BDAS2AS1AIN

16V47n

C420

21

47RR131

21

AVDD_AU

10V100n

C152

21

C143

100n10V

21

AVDD_33

MST6WB7GQ-3U138

84

83

81

80

79

85

86

78

77

76

87

88

89

75

74

90

91

92

93

94

95

96

97

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

82LINE_IN_1L

GND4

CVBSOUT0

CVBSOUT1

AVDD_33_4

VCOM0

CVBS0

VCOM1

CVBS1

CVBS2

CVBS3

Y0

C0

Y1

C1

RIN2P

GIN2P

SOGIN2

BIN2P

VSYNC2

VSYNC0

HSYNC0

GND3

AVDD_33_3

RIN0P

SOGIN0

GIN0P

GIN0M

BIN0P

BIN0M

RIN1P

GIN1P

SOGIN1

BIN1P

REFM

REFP

VCLAMP

VSYNC1

HSYNC1

LINE_OUT_0R

LINE_OUT_0L

LINE_OUT_1R

LINE_OUT_1L

LINE_OUT_2R

LINE_OUT_2L

LINE_OUT_3R

LINE_OUT_3L

AVDD_AU_1

GND5

LINE_IN_MONO

LINE_IN_3R

LINE_IN_3L

AUVRM

AUVRP

AUVAG

LINE_IN_2R

LINE_IN_2L

AVDD_AU_2

LINE_IN_0L

LINE_IN_0R

LINE_IN_1R

AUCOM

2

3V3_VCC

R68633k

21

SAV_CVBS

SAV_AUD_L_IN

SAV_AUD_R_IN

DVB_Y

C443

27p50V

2 1

75RR662

2150V27p

C444

2 1

R66175R

21

SW_PB

DVB_PB

DVB_PR

22kR598

21

R59922k

21

22kR600

21

R60122k

21

R60322k

21

R60522k

21

22kR606

21

DSP_CH1_L

DSP_CH1_R

DSP_CH1_R

DSP_CH1_L

DSP_CH4_L

DSP_CH4_R

MAIN_L

MAIN_RHP_R

HP_LDSP_CH2_L

DSP_CH2_R

DSP_CH4_L

DSP_CH4_R

DSP_CH3_L

DSP_CH3_R

SC1_L

75RR665

2 1

33kR687

21

SC1_FB

10V100n

C144

2 1

16V1uC326

C368

10u10V

2 1

SC_1_R

DVD_Y_IN

C118

220p50V

21

82kR675

21

Q120BC848B

3

2

1

R68933k2 1

82kR676

21

C119

220p50V

21

33kR690

2 1

R15547R

21

TL062

U1178

7

6

54

3

2

1 OUT1

IN1-

IN1+

VSS IN2+

IN2-

OUT2

VDD

33kR691

21

50V220p

C120

21

82kR677

21

33kR692

2 1

50V220p

C121

21

82kR678

21

U118

TL062

8

7

6

54

3

2

1 OUT1

IN1-

IN1+

VSS IN2+

IN2-

OUT2

VDD

8V_VCC

F217

600R

2 1

8V_VCC

16V1u

C332

C142

100n

10V

2 1

CVBS0_OUT

10V

10u

C367

21

10V10u

C378

2 1

C375

10u10V

2 1

10V10u

C372

2 1

C371

10u10V

2 1

330R

F15121

100RR228

21

100RR229

21

100RR224

21

100RR225

21

100RR222

21

100RR223

21

100RR226

21

100RR227

21

LINE_IN_2R

DSP_CH3_L

DSP_CH3_R

CVBS1

AVDD_33R773470R

21

C612

1n

50V

21

DVD_AUD_L_IN

DVD_AUD_R_IN

5V_TUN330R

F11921

16V1u

C331

LINE_OUT_L

LINE_OUT_R

LINE_OUT_R

BC858BQ146

3

2

1

300RR620

21470RR404

21

47RR150

21

47RR152

21

R15147R

21

16V100n

C511

21

16V100n

C512

21

AUDIO INPUT VOLTAGE DIVISION AND DC BLOCK

Place close to PauloAUDIO OUTPUT FILTERS

DVB/YPBPR SWITCH

Place close to PauloVIDEO TERMINATIONS AND DIFFERENTIAL TRACINGPlace 75R termination resistorsclose to Paulo reference GNDs

Pin79

Pin74AVDD_AU DECOUPLING CAPACITORS

SCART VIDEO OUTPUT AMPLIFIERS

S218 21

S217 21

R875

1k

21

BC848BQ162

3

2

1

HDMIA_HPD

HDMIA_5V

R8761k

21

5V_VCC

TP203 1

TP204

1

HDMI_WP224LC02

U1478

5

6

7

4

3

2

1 A0

A1

A2

VSS

WP

SCL

SDA

VCC

10V100nC6292

1

4k7

R807

21

D165BAV70

3

2 15V_VCC HDMIA_5V

HDMIA_SDA

HDMIA_SCL

TP205

1

TP206

1

R84010R

21

10RR839

21

10RR837

21

10RR835

21

R83410R

21

HDMIA_C+

HDMIA_SDA

HDMIA_2-

HDMIA_HPD

TP134 1

TP133

1

HDMIB_5V

R629

1k

21

R39610R 21

C173100n10V

2

1

AVDD_USB3V3_VCC

10V100nC1602

1

C159100n10V

2

1

C157100n10V

2

1

HDMI_WP1

390RR412

21

AVDD_33

R39110R

21

R38810R

21

17MB25

S.SEBNEM TAS & ULAS DERELI

HDMI&USB 1144-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

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24LC02

U1108

5

6

7

4

3

2

1 A0

A1

A2

VSS

WP

SCL

SDA

VCC

R38610R

21

HDMIB_1+

HDMIB_1-HDMIB_0+10R

R3942 1

27k

R621

21

10RR387

21

HDMIB_0-HDMIB_C+

R38910R

21

10RR390

21

CN1212120

19181716151413121110987654321

VDDC

VDDP

VDDP

VDDP

10V100nC1562

1

10V100n

C154

21

AVDD_33

AVDD_33

10V100nC1582

1

C155100n10V

2

1

10RR392

21

HDMIB_SCL

HDMIB_C-

R39310R 21

10V100nC1532

1

4k7

R257

21

BC848BQ123

3

2

1

HDMIB_SDA

2N7002

Q101

32

1

F124

330R

21

910RR119

21

47k

R491

21

47k

R492

21

R493

47k

21

R494

47k

21

AVDD_USB

HDMIA_1+

HDMIA_1-

AVDD_33

HDMIA_0-

HDMIA_C-

HDMIB_HPD

HDMIB_5V

R6301k

21

5V_VCC

HDMIA_SDA

HDMIA_SCL

HDMIB_SDA

HDMIB_SCL

HDMIB_2+

HDMIB_2-

HDMIB_HPD

D147BAV70

3

2 15V_VCC HDMIB_5V

HDMIB_SDA

HDMIB_SCL

TP106

1

TP132

1

TP135

1

TP136

1

MST6WB7GQ-3U138

288

191

192

220

232

219

233

218

234

217

235

216

236

197

237

196

238

195

239

194

240

193

241

242

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

282

283

284

285

286

287

289

290

291

292

293

294

295

296

231ICLK

DDCDB_SCL

DDCDB_SDA

HPLUGB

RXB2P

RXB2N

GND18

RXB1P

RXB1N

RXB0P

RXB0N

AVDD_33_5

RXBCKP

RXBCKN

VDDC5

DDCDA_SCL

DDCDA_SDA

REXT

AVDD_33_2

HPLUGA

RXA2P

RXA2N

GND2

RXA1P

RXA1N

AVDD_33_1

RXA0P

RXA0N

GND1

RXACKP

RXACKN

DI[9]

DI[8]

USB20_DM

DI[7]

USB20_DP

DI[6]

GND11

DI[5]

VDDP2

DI[4]

GND12

VDDP5

VDDP3

DI[3]

USB_VBUS

DI[2]

USB_DM

DI[1]

USB_DP

DI[0]

USB_CID

AVDD_USB

USB20_REXT

GND

1

200RR829

21

4k7

R258

21

10RR385

21

R83210R

21

R83610R

21

R83810R

21

10RR841

21

10RR843

21

HDMIA_2+

10RR833

21

HDMIA_1+

HDMIA_1-

HDMIA_0+

HDMIA_0-

HDMIA_C-

HDMIA_SCL

CN1222120

19181716151413121110987654321

HDMIA_C+

HDMIA_0+

4k7

R808

21

HDMIA_2-

HDMIA_2+

HDMIB_C-

HDMIB_C+

HDMIB_0-

HDMIB_0+

HDMIB_1-

HDMIB_1+

HDMIB_2-

HDMIB_2+

S116 21

5V_STBY

HDMI_CEC

HDMIA_5V

CEC

CEC

CEC

100RR159

21

3V3_STBY

VDDP

HDMI1

Pin6 Pin13 Pin285

Pin236Pin216Pin196

HDMI2

HDMI1

HDMI Receiver In_B

HDMI2

CEC CIRCUIT

OPTION2

CN133

43

21

CN119

54321

R8771k

21

100RR827

21

5V_VCC

GAIN_SW13V3_VCC 4k7

R75721

MECH_SWITCH3V3_STBY

C5V6

D16021

50V220p

C626

21

600R

F24921

600R

F25021

CN130

4321

R16147R

21

R16247R

21

C180

100n10V

21 S122 21

S120 21

CN110

4

3

2

1

5V_STBYR2844k7 21

3V3_STBYR2834k7

2 1

4k7R282

2 1

4k7R277

2 1

R2764k7

2 1

R2754k7 21

3V3_STBY

C178100n10V

2

1

C176100n10V

2

1

C177100n10V

2

1

10V100nC1752

1

4k7

R265

21

MAX809LTRU130

3

21

GND RSTVCC

TP1081

TP1091

10V100n

C181

2 1

TP1101

TP1121

24C32U103

78

654

321 E0

E1E2VSS SDA

SCL

VCCWC

10k

R528

21

BC848BQ130

3

2

1

S12521

S117213V3_STBY

SCL_NVM

IR_IN

47k

R498

21

3V3_VCC

R60822k

2 1

BC848BQ125

3

2

1

SDA_NVM

NVM_WP

TP1111

100k

R724

21

10V100nC182

2

1

10V100n

C183

21

3V3_STBY

14.31818MHz

X104 2

1

1M

R110

21

50V27p

C447

21

270R

R397

21

470R

R405

21

1k2

R484

21

2k7

R118

21

3k9

R243

21

VDDP

VDDP

VDDP

VDDP VDDC

VDDC

LED1

3V3_STBY

3V3_STBY

R2674k7

2 1

3V3_STBY

DVB/YPBPR_SW3V3_VCC

DVB_IRQ

R2684k7

2 13V3_VCC

IDTV_SW

PROTECT

NVM_WP

ANT_CTRL

BC848BQ126

3

2

1

BC858BQ147

3

2

1

Q127BC848B

3

2

1

100RR354

21

R355100R

21

DIMMINGBACKLIGHT_DIM

MST6WB7GQ-3U138

213

212

281

279

278

277

276

275

274

273

272

243

230

229

228

227

225

224

223

222

221

215

214

209

208

207

206

205

20455

56

57

58

59

60

61

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

149

150

151

152

153

154

155

156

157

158

159

226

280

210

211DDCR_SCL

DDCR_SDA

GPIOM[2]

VDDP4

GPIOR[10]

GPIOR[9]

GPIOR[8]

GPIOR[7]

GPIOR[6]

GPIOR[5]

GPIOR[4]

GPIOR[3]

GPIOR[2]

GPIOR[1]

GPIOR[0]

GPIOD[17]

GPIOD[16]

GPIOD[15]

GPIOD[14]

GPIOD[13]

GPIOD[12]

GPIOD[11]

GPIOD[10]

VDDC1

GND6

VDDP1

GPIOD[9]

GPIOD[8]

GPIOD[7]

GPIOD[6]

GPIOD[5]

GPIOD[4]

GPIOD[3]

GPIOD[2]

GPIOD[1]

GPIOD[0]

XIN

XOUT

GPIOL[4]

GPIOL[3]

GPIOL[2]

GPIOL[1]

GPIOL[0] SAR0

SAR1

SAR2

SAR3

PWM0

PWM1

INT

IRIN

GPIOB[0]

GPIOB[1]

PWM2

PWM3

GND14

GPIOT[0]

GPIOT[1]

GPIOT[2]

GPIOT[3]

HWRESET

VDDP7

GND17

GPIOE[3]

GPIOE[2]

GPIOE[1]

GPIOE[0]

GPIOM[0]

GPIOM[1]

GPIOM[3]

DDCA_SDA

DDCA_SCL

3

3V3_VCC

5V_VCC

10kR524

2 1

KEYBOARD_STBY

SCL

SDA3V3_STBY

3V3_STBY

TX/SDA

4k7R289

2 1

RX/SCL

3V3_VCCR2914k7

2 1

4k7R292

2 1

3V3_VCC

SDA_NVMR2624k7

2 1

SCL_NVM

LED2

BACKLIGHT_DIM

DVB_TXD

DVB_RXD

4k7R294

2 1

3V3_VCC

HDMI_CEC

HDMIB_5V

HDMIA_5V

STBY_ON/OFF_NOT

4k7R286

2 1

3V3_STBY

3V3_STBY4k7R287

2 1

R2904k72 1 3V3_STBY

R2884k7

2 1

5V_STBY

BC848B

Q128

3

2

1

R280

4k7

21

17MB25

ÖNDER GENÇ

CONTROLLER 1154-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

U127M74HC4052

1615141312111098

7654321 2Y0

2Y22Z2Y32Y1EVEEGND S1

S01Y31Y01Z1Y11Y2VCC

PROG_EN 5V_STBY

R281

4k7

21

R2614k7

2 1 3V3_STBY

SW_UPDATE_SELECT

SW103 43

21 SW105 43

21 SW106 43

21 SW107 43

21

5V_STBY

5V_STBY

TX/SDAR16347R

21

RX/SCL 47RR164

21

AMP_MUTE

3V3_STBY

RX/SCL_SC

RX/SCL

TX/SDA

S121 21

S123 21

STBY_ON/OFF

3V3_STBY

3V3_STBY

10V

10u

C383 2

1

R2934k72 1 3V3_STBY

3V3_VCCR2644k7

2 1

3V3_STBY 4k7R271

2 1

4k7R269

2 1

R2704k7

2 1

3V3_STBY

5V_VCC

PROTECT_PANEL

R16547R

21

IR_IN

HP_DETECT

100RR352

21

R353100R

21

BC848BQ124

3

2

1

S124

21

DVD_IR

DVD_IR_ON/OFF

50V220p

C530

21

50V220p

C529

21

4k7R232

21

21

4k7R233

10kR421

21

1k

R745

21

4k7R234

21

50V220p

C531

21

10k

R531

21

BC848BQ131

3

2

1

10kR422

21

LED1

R2794k72 1 3V3_STBY

20kR742

2 1

OVER_CUR_DETECT

S11821

3V3_STBY

5V_STBY

3V3_VCC 4k7R274

21

TX/SDA_SCUART0_TXD0

UART0_RXD0

SW_UPDATE_SELECT

USB_DIG_OCD

DVB_RESET

C446

27p50V

21

C653

27p50V

21

600R

F24721

R2784k72 1

STBY_ON/OFF_NOT

S11921

DVD_SENSE

SC1_PIN8

LED2

SW104 43

21

SIF_CTL

R74847R

21

HDMI_WP1

HDMI_WP2

IR_IN

USB_ENABLE

4k7R760

2 1

3V3_STBY

100RR356

2 1

R263

4k7

21

R6944k7

2 1

DVD_IR_ON/OFF

1kR395

21

R382

220R

21

BC858B

Q148

3

2

1 BC858B

Q149

3

2

1

220R

R381

21

R831

220R

21

220R

R830

21

KEYBOARD_STBY

10V100nC6302

1

F248

600R

21

C5V6

D162

21

R79347R

21

D161

C5V6

21

KEYBOARD_ONBOARD

MECH_SWITCH_ONBOARD

TK_SUPPLY

KEYBOARD_ONBOARD

MECH_SWITCH_ONBOARD

SW101

6

5

4

3

2

1

S238MEGA_DCR_IN

S237

MEGA_DCR_OUT

S242

MECH_SWITCH_ONBOARD KEYBOARD_ONBOARD

TK_SUPPLY

TP2411

TP2391

1N4148

D167

R90547R

21

5V_TOLERANT

N.C.

5V_TOLERANT

5V_TOLERANT

1

SW_UPDATE_SELECT

LED

P+ P- VOL+ TV/AV VOL-

PIN272 PIN226PIN108 PIN110

HC4052 DISABLEHC4052 ENABLE1

ANALOG_SW_UPDATE

N.C.

DEBUG SOCKET

For Internal CPU SelectionFor Internal CPU Selection

MAX810

0

N.C.

PROGRAMMING PART

PROG_EN

DVB_SW_UPDATE0

5V_TOLERANT

5V_TOLERANT

PUSH V+ AND V- AT THE SAME TIME FOR MENU

BADR[0]R9084k7

213V3_VCC

BC848BQ168

C712100n10V

2

1

R9104k7

2 1 3V3_VCC

3V3_VCC4k7R909

2 1

DVB_SPDIF

MX25L512U132

87654

321 CS#

SOWP#GND SI

SCLKHOLD#VCC

R367100R

21

R368100R

21

R366100R

21

330R

F126213V3_VCC

10V100nC1962

1

C197100n10V

2

1

10V100nC1982

1

C199100n10V

2

1

10V100nC2002

1

10V100nC2012

1

C202100n10V

2

1

MDATA[4]

10V100nC1932

1

C189100n10V

2

1

100RR357

21

VDDM

MADR[0]

MCLKE

WEZ

MADR[7]

6V3220uC461

2

1

6V3220uC462

2

1

10V100nC2042

1

10V100nC2102

1

60R

F16321

10V100nC2122

1

100R

R365

21

100RR369

2 1 SDI

100RR370

21

17MB25

ÖNDER GENÇ

MEMORY INTERFACE 1164-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

SCZ

SDO

MDATA[0]

MDATA[1]

MDATA[2]

MDATA[3]

MDATA[5]

MDATA[6]

MDATA[7]

MDATA[8]

MDATA[9]

MDATA[12]

MDATA[13]

MDATA[14]

MDATA[15]

MADR[2]

MADR[3]

MADR[4]

MADR[5]

MADR[6]

MADR[9]

MADR[8]

RASZ

SDO

SCZ

SDI

SCK

MDATA[10]

SCK

10k

R535

21

R536

10k

21

50V1nC5012

1

MADR[1]

MADR[10]

VDDM

VDDM

MDATA[11]

MST6WB7GQ-3U138

203

202

201

200

199

190

189

188

187

186

185

184

183

182

181

180

178

177

176

175

174

173

172

171

169

168

167

165

164

163

161

160119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

198

179

170

166

162AVDD_MI_3

MDATA[2]

MDATA[5]

AVDD_MI_6

SPI_SCK

AVDD_MIPLL

AVDD_MI_2

GND8

WADR[0]

WADR[1]

WADR[2]

WADR[3]

WADR[4]

WADR[5]

WADR[6]

WADR[7]

WADR[8]

WADR[9]

WADR[10]

WADR[11]

WEZ

CASZ

AVDD_MI_1

GND7

VDDC2

RASZ

BADR[0]

BADR[1]

ALE

RDZ

WRZ

AD[3]

AD[2]

AD[1]

AD[0] DQM0

DQS0

MDATA[0]

MDATA[1]

GND9

MDATA[3]

AVDD_MI_4

MDATA[4]

MDATA[6]

MDATA[7]

AVDD_MI_5

MDATA[8]

MDATA[9]

GND10

MDATA[10]

MDATA[11]

MDATA[12]

MDATA[13]

MDATA[14]

MDATA[15]

AVDD_MI_7

DQS1

DQM1

MCLKZ

MCLK

MCLKE

MVREF

SPI_SDI

SPI_SCZ

SPI_SDO

GND13

VDDC3

5

VDDC

LDM

UDM

10V100nC2132

1

3V3_VCC

DVD_SPDIF

VDDC

VDDC

CASZ

VDDM

C194100n10V

2

1

VDDM

VDDM

VDDM

10V100nC1952

1

VDDM

3V3_STBY

330R

F15721

10V100nC203 2

1

VDDM

60R

F16221

VDDM

TP118

1

TP113

1

TP115

1

TP114

1

TP119

1

10V100nC2082

1

C186100n10V

2

1

VDDM

MCLK100RR499

21

BACKLIGHT_ON/OFF

4k7R295

213V3_VCC

PANEL_VCC_ON/OFF

SPDIF_OUT

R296

4k7

21

3V3_VCC

10V10uC4692

1

TP117

1

TP116

1

3V3_STBY

10V100nC1842

1

10V10uC6432

1

330R

F15021

VDD_DMC

VDD_DMQ

4k7R907

21

4k7

R906

21

3V3_VCC

S244

4k7

R912

MT48LC4M16A2TG8EU131

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28VSS1

A4

A5

A6

A7

A8

A9

A11

NC1

CKE

CLK

DQMH

NC2

VSS2

DQ8

VDDQ3

DQ9

DQ10

VSSQ3

DQ11

DQ12

VDDQ4

DQ13

DQ14

VSSQ4

DQ15

VSS3

VDD3

A3

A2

A1

A0

A10

BA1

BA0

CS#

RAS#

CAS#

WE#

DQML

VDD2

DQ7

VSSQ2

DQ6

DQ5

VDDQ2

DQ4

DQ3

VSSQ1

DQ2

DQ1

VDDQ1

DQ0

VDD1VDD_DMC

VDD_DMQ

100RR586

87654

321

R4R3R2R1MDATA[3]

MDATA[2]MDATA[1]MDATA[0]

R587100R

87654

321

R4R3R2R1

VDD_DMQ

MDATA[6]MDATA[7]

MDATA[4]MDATA[5]

VDD_DMC

R828100R

21LDM

R10422R

21WEZ

R10522R

21CASZ

R10322R

21RASZ

22RR900

21

BADR[0]R92722R

21

BADR[1]

BADR[1]

3V3_VCC 4k7R911

21

100RR916

87654

321

R4R3R2R1

MADR[8]

MADR[10]

MADR[9]

100RR917

87654

321

R4R3R2R1

MADR[1]MADR[0]

MADR[3]MADR[2]

VDD_DMC

MADR[4]

MADR[6]MADR[5]

MADR[7]

R915100R

87654

321

R4R3R2R1

MADR[11]

MADR[11]

MCLK

MCLKER361100R

21

UDM100RR360

21

VDD_DMQ R589100R

87654

321

R4R3R2R1

MDATA[11]

MDATA[9]MDATA[10]

MDATA[8]

R588100R

87654

321

R4R3R2R1

MDATA[14]MDATA[15]

MDATA[13]MDATA[12]

VDD_DMQ

PIN27

PIN129 PIN203

PIN131 PIN147 PIN162 PIN168 PIN173 PIN179 PIN184

FLASH

PIN1 PIN14

PIN3 PIN49PIN43PIN9

8MB SDRAM

WARNING!!!DON'T USE VIA FOR MCLK AND DATA SIGNALS

MEMORY

35V220uC711

Q166BC848B

3

2

1

C7071n50V

R88810k

21

16V1u

C695

TPA3101U150

12

11

10987654321

24

23

22

21

20

19

18

17

16

15

14

13

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48 AVCC_2

AVCC_1

FAULT

MUTE

SHUTDOWN

BSRP

ROUTP_2

ROUTP_1

ROUTN_2

ROUTN_1

BSRN

GND_7

GND_6

PVCCR_2

PVCCR_1

PGNDR_2

PGNDR_1

VCLAMPR

VCLAMPL

PGNDL_2

PGNDL_1

PVCCL_2

PVCCL_1

GND_5

GND_3

ROSC

VREG

VBYP

AGND_2

BSLP

LOUTP_1

LOUTP_2

LOUTN_1

LOUTN_2

BSLN

GND_4

GND_1

RINN

RINP

AGND_1

LINP

LINN

GAIN0_1

GAIN0_2

GAIN1

MSTR/SLV

SYNC

GND_2

16V1u

C696

R896

100R8 7 6 5

4321

R2

R3

R1

R4

50V100n

C703

MAIN_R

MAIN_L

16V1u

C694

100k

R890

50V470pC700

16V1u

C350

SS33

D166

CN115

4

3

2

1

S230

VREG

10V10u

C385

21

S229

R891

100k

VREG

100k

R893

VREG

C688

220n25VVDD_AUDIO

R892100k

F254

50R

100kR898

S126 21

S127 21

17MB25

S.SEBNEM TAS

AUDIO 1174-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

HP_DETECT

8V_VCC

50V1nC704

VREG

16V1u

C693

25V220n

C689

50R

F253

50V1n

C705

L118

10u

21

C6801u25V

F252

50R

3V3_VCC

50V1nC706

10u

L11921

25V1uC681C690

220n25V

10u

L1202 1

S23612V_AUDIO

24V_VCCS235

VDD_AUDIO

VDD_AUDIO

25V1uC682

50V

1uC685

35V22u

C708

16V

1u

C692

Q133BC848B

3

2

1

AMP_MUTE

MUTE_HP_L

R54510k

2 1BC848BQ135

3

2

1

16V1u

C702

10k

R546

21

BC858BQ150

3

2

1

AMP_EN

AMP_EN

R88710k

2

1

10kR542

2 1BC848BQ132

3

2

1

1N4148

D124

21

50V470pC698

5V_VCC

16V1uC701

MUTE_HP_R

Q134BC848B

3

2

1

10kR544

2 1

5V_VCC

POP_MUTE

C684

1u50V

C710

22u35V

VDD_AUDIO

25V220n

C691

50R

F251

HP_L

HP_R

25V1uC683

L121

10u

2 1

C699470p50V

100R

R894

8 7 6 54321

R2

R3

R1

R4

50V470pC697

R897

100R8 7 6 5

4321

R2

R3

R1

R4

16V100nC595

100R

R895

8 7 6 54321

R2

R3

R1

R4

VDD_AUDIOVREG

FAULT

R541

10k

21

100k

R729

21

S128 21

C709

22u

35V

C6871u50V

VDD_AUDIO

BC848BQ167

3

2

1

D127

1N4148

21

12V_VCC

R90410k

21FAULT

16V100u

C453

2 1

R_AUDIO_N

R_AUDIO_P

L_AUDIO_P

16V100u

C5412 1

50V1n

C503

21

50V

220p

C122 2

1

50V2n2

C537 2

1

50V2n2C5382

1

600R

F19021

15k

R123

21

100kR211

21

3k9

R236

21

20k

R237

21

4k7R423

21

4k7R424

21

L_AUDIO_N

L_AUDIO_N

10kR722

21

L_AUDIO_P

TDA1308T

U1288

7

6

54

3

2

1 OUTA

INAN

INAP

VSS INBP

INBN

OUTB

VDD10V10uC3862

1

1N4148

D1262 1

D125

1N4148

2 1

C5021n50V

2

1

16V100u

C540

21

C123

220p

50V2

120k

R238

21

600R

F19221

JK107

987

654

321

R_AUDIO_N

R_AUDIO_P

MUTE_HP_L

600R

F191

21

50V

2n2

C625

2 1

50V2n2C6242

1

MUTE_HP_R

100k

R212

21

10V220n

C472

21

10V220n

C471

21

3000028910NF

ANALOG

CONNECT TO C552 GND

ANALOG

CONNECT TO C553 GND

HEADPHONE AMPLIFIER

ANALOG

POP NOISE CIRCUIT

ANALOGPOWER POWER

POWER POWERANALOG

ANALOG

CLOSE TO PIN

POWER

POWER

POWER

POWER

POWERPOWER

ANALOG

ANALOG

ANALOG

POWER POWER

POWERPOWER

PIN 1,12,13,24,25,36 AND 37

MUST BE CONNECT TO TERMAL PAD

ANALOGANALOG

ANALOG

USB_ENABLE

CN128

4

3

2

1

5V_VCC

USB_DIG_OCD

5V_VCC

STMP2161

U149

5

43

2

1 OUT

GND

FAULT EN

IN

4k7

R809

21

47kR855

2 1

100k

R884

21

330R

F2352 1

AZ099-04S

U1456

5

43

2

1 IO1

GND

IO2 IO3

VDD

IO4

10V10uC644 2

1

BC847BQ160

3

2

1

5V_VCC

3V3_VCC

12V_VCC

CI_PWR

BSH103

Q158

32

1

330R

F23621

10V10uC6452

1

10V

100n

C631

2 1

10V100nC6322

1

10k

R862

21

R86310k

21

R85647k

21

R85747k

21

TP207

1

CI_A5

CI_D5

CI_D7

CI_A10

CI_A11

CI_A8

CI_A14

CI_D4

CI_OE

CI_A13

CI_WE

CI_A6

CI_A4

CI_A2

CI_A0

CI_D1

CI_A7

CI_A3

CI_A1

CI_D0

CI_IORD

CI_D2

CI_A9

CI_D6

CI_CE

CI_CD 3V3D_DVB

CI_WAIT

CI_IOWR CI_RST

CI_REG

MPEG_TS_OUT_D7

MPEG_TS_OUT_D6

MPEG_TS_OUT_D5

MPEG_TS_OUT_D4

MPEG_TS_OUT_D2

MPEG_TS_OUT_D0

MPEG_TS_OUT_D1

MPEG_TS_IN_D2

MPEG_TS_IN_D1

MPEG_TS_IN_D0

MPEG_TS_OUT_SYNC

3V3D_DVB

MPEG_TS_OUT_D3

CI_D3

MPEG_TS_IN_SYNC

MPEG_TS_IN_VALID

MPEG_TS_OUT_VALID

CI_A12

3V3D_DVB

MPEG_TS_IN_D3

MPEG_TS_IN_D4

MPEG_TS_IN_D5

MPEG_TS_IN_D6

MPEG_TS_IN_D7

4k7

R810

21

3V3D_DVB

CI_PWR

3V3D_DVB

CI_IREQ

CI_PWR

3V3D_DVB

CN131

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

4k7

R811

21

47R

R794

21

4k7

R812

21

4k7

R813

21

4k7

R814

21

4k7

R815

21

4k7

R816

21 4

7R

R795

21

47R

R850

8 7 6 54321

R2

R3

R1

R4

10k

R864

21

47R

R851

8 7 6 54321

R2

R3

R1

R4

3V3D_DVB

MPEG_TS_IN_CLK

150R

R791

21

5V_VCC

F237

330R

21

CI_PWR_CTRL

17MB25

MB35 HW GROUP

CI 1184-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

50V

15p

C655

21

MPEG_TS_OUT_CLK

C656

15p

50V

2 1

R84410R

2 1

10RR845

2 1

USB_DIG_DP

USB_DIG_DM

N.C.

B1

TS_OUT

TS_IN

CIB4

MPEG_TS_OUT

TS ROUTING

MPEG_TS_IN

CI_CONTROL/ DATA&ADDRESS BUS

CI 5V SWITCH CIRCUITUSB INTERFACE

CI SOCKET

N.C.

USB

C713

22p50V

50V22p

C714

C35222u16V

2

1

50V22p

C716

C717

22p50V

1MR789

2 1

C250100n10V

2

1

R326

1k2

21

5V_VCC

3V3D_DVB

MCAS

MA0

MA2MA1

MA11MA9MA8MA7MA6MA5

CI_D0

CI_D2

CI_D1

CI_D6

CI_D5

CI_D7

CI_D3

CI_D4

CI_A0CI_A1

CI_A3CI_A4

CI_A6

CI_A2

CI_A8CI_A9

CI_A10CI_A11

CI_A13CI_A12

CI_A5

CI_A7

MBS0

MD2MD1

RESET_DVB

MPEG_TS_IN_VALID

MPEG_TS_IN_D1

MPEG_TS_IN_D6

MPEG_TS_OUT_D1

MPEG_TS_OUT_D3

MPEG_TS_OUT_D4

MPEG_TS_OUT_D5

MPEG_TS_OUT_D6

3V3_VCC 3V3A_PLL_DVB

3V3_VCC

3V3_VCC

3V3_VCC

3V3A_ADC_DVB

ENC_PB

ENC_PR

ENC_Y

MPEG_TS_OUT_CLK

MPEG_TS_OUT_VALID

MPEG_TS_OUT_D7

MPEG_TS_OUT_D2

MPEG_TS_IN_D5

MPEG_TS_IN_D4

MPEG_TS_IN_D3

MPEG_TS_IN_D2

MPEG_TS_IN_D0

MPEG_TS_IN_CLK

MPEG_TS_IN_SYNC

DVB_RESET

MPEG_TS_OUT_SYNC

MDQM

MA1MA2

MD0

CI_WAIT

CI_RST

3V3D_DVB

CI_A14

33RR446

87654

321

R4R3R2R1

SF_CS

SF_DO

SF_CLK

SF_DIO

3V3D_DVB

MA3

MWEMDQM

MRAS

MA12

MA4

MBS0MBS1

MD0

MD1MD2

MD4MD3

3V3_SDRAM_DVB

3V3_SDRAM_DVB

MD6MD5

MD7

MD15

MD14MD13

3V3_SDRAM_DVB

MD11MD12

MD10MD9

3V3_SDRAM_DVBMD8

3V3_SDRAM_DVB

3V3_SDRAM_DVB

3V3_SDRAM_DVB

SCL_TUN_DVBSDA_TUN_DVB

1V8D_DVB

3V3A_DVB

3V3A_DVB

MPEG_TS_OUT_D0

3V3D_DVB

UART0_RXD0

MPEG_TS_OUT_VALID

17MB25

ULAS DERELI

DVB MPEG DECODER & SDRAM 1194-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

3V3A_PLL_DVB

MA10

MPEG_TS_IN_D7

DSU_RXD0

1V8_VCC

3V3_VCC

33RR186

21

MCAS

3V3_VCC

3V3D_DVB

3V3_SDRAM_DVB

3V3_SDRAM_DVB

3V3D_DVB

UART0_TXD0

DSU_TXD0

CI_OE

RESET_DVB

CI_PWR_CTRL

ENC_CVBS

ENC_PR

ENC_PB

ENC_Y

DVB_Y

SF_CLK

SF_CSSF_DO

1V8D_DVB

ENC_CVBS

3V3A_DVB

CI_WE

DVB_SPDIF

DVB_TXD

DVB_RXD

USB_DIG_DP

USB_DIG_DM

3V3A_DVB

TP154

1

TP1241

10k

R406

21

4k7R307

2 1

MX25L512U114

87654

321 CS#

SOWP#GND SI

SCLKHOLD#VCC

10k

R376

21

33RR182

21

33RR190

21

TP153

1

10k

R373

21

10V100nC240

2

1

10V10uC2932

1

33RR191

21

330R

F14221

33RR443

87654

321

R4R3R2R1

33RR444

87654

321

R4R3R2R1

33RR437

87654

321

R4R3R2R1

33RR450

87654

321

R4R3R2R1

33R

R449

87654 3 2 1

R4R3R2R1

33R

R448

87654 3 2 1

R4R3R2R1

10k

R372

21

33R

R188

21

50V1n

C301

21

10V

100n

C274

2 1

330R

F14021

10V100nC2552

1

3V3_VCC

10V

100n

C277

2 1

16V

22u

C679

2 1

33R

R440

87654 3 2 1

R4R3R2R1

330R

F13721

100RR316

21

1k2

R328

21

100RR318

21

1k2

R327

21

10V100nC2482

1

TP1201

TP1221

R317100R

21 10V100nC239 2

1

10V

100n

C266

2 1

4k7R308

2 1

330R

F13821

75RR458

2 1

75RR459

2 1

C67822u16V

2

1

50V

27p

C297

21

10k

R375

21

10V

100n

C251

2 1

10V100nC2532

1

10V100nC2732

1

10V100nC2592

1

10V100nC2582

1

330R

F13421

10V10uC2952

1

10V100nC2562

1

10V100nC2572

1

10V100nC2642

1

10V

100n

C254

21

10V

10u

C292

2 1

10V100nC265 2

1

10V10uC2912

1

CT216T-R

U104

216

215

545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321

108

107

106

105

104

103

102

101

100

999897969594939291908988878685848382818079787776757473727170696867666564636261605958575655

109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

GPF23/CIREG

GPA8/CI0INT#

GPA9/CI1INT#

GPF31/CIIOWR#

GPF30/CI0IORD#

GPF25/CI0CE#

GPF27/CI1CE#

GPF24/CI0CD#

GPF26/CI1CD#

HWAIT/GPF22

HRD#/CI0OE#/GPOF21

HWR#/CIWE#

HA15/GPOF15

HA16/CI1IORD#/GPOF16

HA17/CI1OE#/GPOF17

HALE/GPOF20

GPB10/VSYN/KEYDET2

GPB9/HSYN/KEYDET1

GPB8/USB_DRVVBUS

GPB4/USB_DRVVBUS

GPB3/DSPLYCM3

GPB2/DSPLYCM2

GPB1/RX1/DSPLYCM1

GPB0/TX1/DSPLYCM0

VDD33_4

GPB6/DSPLYCLK

GPB5/DSPLYDAT

GPB7/IR

VDD18_3

GPA13/SC1CD

GPC8/SC1RST

GPC9/SC1PWR

GPC7/RX2/SC1DAT

GPC6/TX2/SC1CLK

GPA3/SC0CD

GPC4/SC0RST

GPC5/SC0PWR

GPC3/UART1_RX/SC0DAT

GPC2/UART1_TX/SC0CLK

GPB14/SD/MS_D2

GPB15/SD/MS_D3

GPB11/SD/MMC_CMD

GPC14/SD/MMC_CLK

GPB12/SD/MMC_DAT

GPB13/SD/MS_D1

GPA10/SD/MMC_WP

GPC13/SD/MMC_PWE

GPG6/MS_INS

GPG4/SD_PWE

GPG3

GPG2

GPG1

GPG0AVSS_3AVO3

AVD33_3AVO2

AVSS_2AVO1

AVD33_2AVO0

AVSS_1FSADJVREF

AVD33_1AUDIO_DAC_VMID

AUDIO_DAC_LAUDIO_DAC_RGPC15/SPDIF

GPA0/CLKO/PCMACKHAD8/PD0/GPOE8HAD9/PD1/GPOE9

VDD18_2HAD10/PD2/GPOE10HAD11/PD3/GPOE11HAD12/PD4/GPOE12HAD13/PD5/GPOE13HAD14/PD6/GPOE14HAD15/PD7/GPOE15HA19/VSYN/GPOF19HA18/HSYN/GPOF18

GPA7/PWM3/PCMSD/SCXOGPA6/PWM2/PCMWS/SCXIGPA5/PWM1/PCMCLK/TX2GPA4/PWM0/PCMACK/RX2

UART0_TX/GPOC0UART0_RX

SAR_ADC_IN1SAR_ADC_IN0

VDD33_3VSS_2OSCIOSCO

GPC1/COFDM_ERRGPA12/AGC_RFGPA11/AGC_IF

GPA15/SDAGPA14/SCL

AVSS_PLL_2VLFQ

AVD33_PLLVLFM

AVSS_PLL_1VCCAVSSA

VCCAX

HAD7/GPOE7

HAD6/GPOE6

HAD5/GPOE5

HAD4/GPOE4

HAD3/GPOE3

HAD2/GPOE2

HAD1/GPOE1

HAD0/GPOE0

SF_CS#/FCS#

SF_CLK/HA22/GPOD4

SF_DO/HA21/GPOD3

SF_DIO/HA20/GPOD2

VDD33_2

GPD6/FUM/TSO_SYN

GPD7/FUM/TSO_VLD

GPD5/FUM/TSO_CLK

GPD8/FUM/TSO_D0

GPD9/TSO_D1

GPD10/TSO_D2

GPD11/TSO_D3

GPD12/TSO_D4

GPD13/TSO_D5

GPD14/TSO_D6

GPD15/TSO_D7

TSI_SYN/HSYN

TSI_VLD/VSYN

TSI_CLK/CLKO

TSI_D0/PD0

TSI_D1/PD1

TSI_D2/PD2

TSI_D3/PD3

TSI_D4/PD4

TSI_D5/PD5

TSI_D6/PD6

TSI_D7/PD7

DSU0_RX/UART0_RX/GPD0

DSU0_TX/UART0_TX/GPD1

RESET#

GPA1/CS1#/RX1/HSYN/SD_CD#

GPA2/CS2#/TX1/VSYN/PCMCLK

OSCI1

OSCO1

USB_AVD33

USB_AVSS_1

USB_DN

USB_DP

USB_REF

USB_AVSS_2

USB_AVD18

VINP

VINN

VREFN

VREFP

ADC_VMID

MD0MD1MD2MD3MD4MD5MD6MD7MDQMMD15MD14MD13MD12MD11MD10MD9MD8MCLKVDD33_1VSS_1MA12/GPOC11MA11/GPOC10MA9MA8MA7MA6MA5MA4MWE#VDD18_1CAS#RAS#BS0BS1/GPOC12MA10MA0MA1MA2MA3HA14/GPOF14HA13/GPOF13HA12/GPOF12HA11/GPOF11HA10/GPOF10HA9/GPOF9HA8/GPOF8HA7/PD7/GPOF7HA6/PD6/GPOF6HA5/PD5/GPOF5HA4/PD4/GPOF4HA3/PD3/GPOF3HA2/PD2/GPOF2HA1/PD1/GPOF1HA0/PD0/GPOF0

GPF29

GPF28

10V10uC2942

1

10V100nC2452

1

10V100nC2462

1

10V100nC2472

1

10V100nC2432

1

10V100nC2442

1

10V100nC2722

1

10V100nC2362

1

10V100nC2372

1

330R

F13221

330R

F13321

10V100nC2522

1

330R

F13621

330R

F13521

FUM_EN

R91833R

87654

321

R4R3R2R1

33R

R436

8 7 6 54321

R4R3R2R1

MDQMMCLK_SDRAM

MCLK_SDRAM

U134MT48LC4M16A2TG8E123456789101112131415161718192021222324252627

545352515049484746454443424140393837363534333231302928VSS1

A4A5A6A7A8A9

A11NC1CKECLK

DQMHNC2

VSS2DQ8

VDDQ3DQ9

DQ10VSSQ3DQ11DQ12VDDQ4DQ13DQ14VSSQ4DQ15VSS3

VDD3A3A2A1A0A10BA1BA0CS#RAS#CAS#WE#DQMLVDD2DQ7VSSQ2DQ6DQ5VDDQ2DQ4DQ3VSSQ1DQ2DQ1VDDQ1DQ0VDD1

50V1n

C302

21

50V1n

C303

21

75R

R454

21

75R

R455

21

R456

75R

21

10V100nC278 2

1

330R

F13021

UART0_TXD0

UART0_RXD0

MPEG_TS_OUT_D0

DSU_TXD0

33RR180

8

7

6

54

3

2

1

R2

R3

R1

R4

MPEG_TS_OUT_SYNC

FUM_EN

MPEG_TS_OUT_CLK

DSU_RXD0

DSU_TXD0

3V3D_DVB

1V8_VCC

DVB_IRQ

CN109

10 9

8 7

6 5

4 3

2 1

10kR348

21

10V10uC2892

1

1V8D_DVB

3V3D_DVB

50V1n

C300

21

10V

100n

C275

21

TP163

1

TP164

1

10V100nC2492

1

10kR371

21

4k7R762

21

IDTV_SW

3V3D_DVB

IF_AGC_DVB

4k7

R500

21

33R

R447

87654 3 2 1

R4R3R2R1

33R

R183

87654 3 2 1

R4R3R2R1

CN107

21

DIGITAL_IF_N

DIGITAL_IF_P

33RR185

2 1

330R

F14121

10V100nC267 2

1

33RR926

R92233R

87654

321

R4R3R2R1

3V3A_ADC_DVB

33RR924

87654

321

R4R3R2R1

50V

27p

C2962

1

10V100nC2632

1

10V100nC2602

1

10V100nC2622

1

10V100nC2612

1

10V10uC2882

1

S21521

S21421

10V

100n

C268

2 110V

100n

C276

2 1

R92533R

R92133R

87654

321

R4R3R2R1

33RR919

87654

321

R4R3R2R1

R92033R

87654

321

R4R3R2R1

R92333R

87654

321

R4R3R2R1

BC847B

Q153

3

2

1

100RR320

21

16V22uC287

2

1

50V10p

C715

50V

47p

C619 2

1

1u

L115

21

27MHz

X102

21

3V3D_DVB

TP121

1

100RR319

2 1 RF_AGC_DVB

50V15pC601 2

1

5V_VCC

10V10uC2862

1

10V10uC2852

1

TP155 1

TP141 1

SF_DIO33RR192

21

TP1561

TP1521

3V3_SDRAM_DVB

DVB_PB

FMS6145

U139

1

2

3

4

5

6

7

14

13

12

11

10

9

8NC2

OUT5

OUT4

GND

OUT3

OUT2

OUT1

NC1

IN5

IN4

VCC

IN3

IN2

IN1

75RR457

2 1

75RR461

2 1

DVB_CVBS

DVB_PR

CI_CD

CI_CE

R435

33R8 7 6 5

4321

R4R3R2R1

CI_IORD

CI_IOWR

CI_IREQ

CI_REG

33R

R434

8 7 6 54321

R4R3R2R1

50V390p

C124

21

50V390p

C139

21

50V390p

C102

21

50V390p

C101

21

75R

R462

21

MD3

MD7MD6MD5MD4

MD15MD14MD13MD12MD11MD10MD9MD8

100RR315

21

MA11MA9MA8MA7

MA5MA6

MA4MWE

MBS1

MA0MA10

MA3

3V3D_DVB

MA12

MRAS

1V8D_DVB

10V100nC269 2

1

TP1231

TP2081

470RR198

21

5k6

R325

21

R913100R2 1

100RR914

2 1

RAM ADDRESS BUS

MPEG DEC TS OUTPUT

CI ADDRESS BUS

CI DATA BUS

* Layout Req.

MPEG DEC TS INPUT

DVB VIDEO FILTER&AMP

SERIAL FLASH

CI CONTROL SIGNALS

CHEERTEK

MPEG DECODER

Comm.Port

CVBS/YPbPr Video

Outputs

DVB RESET

<==

<==

SERIAL FLASH

==>

FUM Interface SDRAM

390nH

27MHz VCXO

RAM DATA BUS

12V_VCC12V_AUDIO

25V220nC660

C667

220n

25V2

1

12V_STBYS222 21

D120

C5V6

21

10V100nC637 2

1

R86610k

21

3V3_STBY

U148MP1583

1234

8765FB

COMPENSS

GNDSWINBS

16V22uC671 2

1

TP211

1D164

SS33

21

15u

L11621

C666

100n16V

21

C67010n16V

2

1

C677

5n650V

21

R8033k9

21

C67222u16V

2

1

C67322u16V

2

1

16V22uC6742

1

BC848BQ164

3

2

1

10V100nC634 2

1

R8184k7

2 1

TP210

1

5V_VCC

MOSFET_CONTROLR8174k7

2 1

FDC642P

Q156

2

6543 1

TP209

1

F241

60R

21

7A/32VDC

FS10421

12V_PSUR84710R

21

22k

R874

21

22kR873

21

IRF7314Q155

8

7

6

54

3

2

1

TP2021

TP2011

C5V6

D157

21

10kR571

21

33kR708

2 1

10kR570

21

10kR569

21

D137

BAW56

3

21

R562

10k

21

R56310k

21Q136

BC848B

3

2

1

BC858BQ151

3

2

1

3V3_STBY

4k7R342

21

R3434k7

21 STBY_ON/OFF

5V_VCC

C56722u16V

2

1

16V100uC543

2

1

17MB25

ONDER GENC

MB25 POWER 11104-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

16V22uC5652

1

16V22uC566 2

1

S1342 1

12V_VCC

R3394k7

21

4k7R340

21

R3414k7

21

330R

F14521

PANEL_VCC_ON/OFFBC848BQ139

3

2

1

12V_VCC

5V_VCC

C309100n10V

2

1

5V_VCC

5V_VCC

3V3_VCC

3V3_VCC

5V_STBY

12V_VCC

R56410k

21

5V_STBY

10kR575

2 1

10V100nC310 2

1

R3384k7

2 1

1V26_STBY

3k9R244

21

50V5n6

C599

21

3V3_STBY

R3454k7

21

R3444k7

21 BACKLIGHT_ON/OFF

F170

60R

21

6V3100u

C506

21

C507

100u6V3

2 1

24V_VCC

5V_VCC

3V3_VCC

BAW56

D135

3

21

10kR565

2 1 33k

R699

21

R70533k

2 1 12V_VCC

R56810k 21

33kR706

2 1

5V_TUN

D136

BAW56

3

21

PANEL_VCC

BC848B

Q137

3

2

1

12V_AUDIO

33kR707

2 1

R70933k2 1

24V_VCC

330R

F14721

F146

330R

21

C408

10u

10V

21

10V100nC3072

1

LM1117U122

4

3 2

1

GND

OUTIN

VOUT

8V_VCC

8V_VCC

MECH_SWITCH

VDDP

VDDC

AVDD_33

MP2112

U1446

5

4 3

2

1FB

GND

SWVINB

VINA

EN16V22uC5792

1

16V22uC5752

1

16V22uC5762

1

60R

F17121

60R

F16921

C406

10u

10V

21

16V10nC358 2

1

16V22uC5782

1

16V47uC470

2

1

16V100n

C518

21

10V100n

C519

21

50V1n

C535

21

3V3_VCC

SS33

D14421

R70233k

21

10kR378

21

1kR476

21

4u7

L11021

TP157

1

TP143 1

TP149

1

PROTECT

TP150

1

FDC642P

Q104

2

6543 1

TP145

1

3V3_VCC

25V

10u

C452 2

1

2k

R411

21

STBY_ON/OFF_NOT

3V3_VCC

S210 21

1V26_STBY

C56822u16V

2

1

MP1583U137

1234

8765FB

COMPENSS

GNDSWINBS

12V_STBY

TP147 1

D156

C5V6

21

TP196

1

30V_VCC

24V_VCC

5V_VCC

TP195

1

TP197 1 TP1981

12V_STBY

TP199 1

12V_AUDIO 12V_VCC

TP200 1

5V_STBY

3V3_VCC

1V8_VCC

LM1117U121

4

3 2

1

GND

OUTIN

VOUT

JK103

5

4

3

2

1

7A/32VDC

FS10221 12V_PSU

3V3_STBY

10RR846

21

MECH_SWITCH

FS103

7A/32VDC

21

C410

10u

10V

21

10V100nC3082

1

10V100nC633 2

1

12V_STBY

5V_STBY

S227 21

12V_STBY

15k

R854

21

3V3_VCC

C635

100n10V

21

BC848BQ163

3

2

1

12V_STBY

12V_AUDIO

C409

10u

10V

21 C306

100n10V

2

1

12V_INV

MOSFET_CONTROL

25V10uC6412

1

12V_INV

10V

100n

C636

2 1

DIMMING

FDC642P

Q105

2

6543 1

33k

R566

21

DIMMING

60R

F22221

3V3_STBY

12V_STBY

12V_STBY

R700

33k

21

R336

33k

21

25V

220n

C618 2

1

3V3_STBY

47RR205

21

BC848BQ138

3

2

1

25V10uC6422

1

5V_STBY

47RR796

21

FDC642P

Q157

2

6543 1

S211 21

12V_STBY

10kR865

21

R881

33k

21

C668

220n

25V2

1

25V

220n

C669 2

1

33k

R880

21

R882

33k

21

33kR883

21

R79747R

21

12V_VCC

47RR798

21

30k

R790

21

1k

R878

21

25V220nC665

25V

220n

C436 2

1 33k

R337

21

25V220nC661

L106

15u21

60R

F17221

S245 21

25V220nC663

PANEL_VCC

25V220nC662

PROTECT_PANEL

CN117

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

CN126

20 19

18 17

16 15

14 13

12 11

10 9

8 7

6 5

4 3

2 1

25V220nC664

TP142

1

BACKLIGHT_ON/OFF

100R

R721

21

47RR410

21S228 21

200k

R249

21

160kR124

21

2k

R886

21

CN127

11

10 9 8 7 6 5 4 3 2 1

25V100uC455

25V220nC659

TP236 1

TP237 1

TP2381

STBY_ON/OFF

STBY_ON/OFF_NOT

S241

S243

MOSFET_CONTROL

MOSFET_CONTROL

C5V6

D174

C18V

D175

4A/24VDC

FS105

3V3_STBYS240

S239

180K olacak

NC

NC

NC

CAPACITORSPAULO DECOUPLING

SHORT CCT PROTECTION

PANEL SUPPLY SWITCH

INVERTER SOCKET

A/D DIMMING SELECTION

17IPS17 CONNECTOR

17PW26 OPTIONSADAPTER AND IPS15 OPTIONS

ADAPTER OPTIONS17PW26 CONNECTOR

NC

!

!

TP235 1

TP230 1

TP229 1

TP228 1

TP226 1

TP224 1

TP223 1

TP222 1

TP221 1

TP220 1

TP217 1

TP216 1

TP215 1

TP214 1

S141 21

S1402 1

OPTION3

OPTION2

OPTION1

RX_A_3_N

RX_A_CLK_P

RX_A_2_P

RX_A_2_N

RX_A_1_P

RX_A_1_N

RX_A_0_P

RX_A_0_N

RX_A_CLK_N

RX_A_3_P

RX_B_3_P

RX_B_0_P

RX_B_1_N

RX_B_1_P

RX_B_2_N

RX_B_2_P

RX_B_CLK_N

RX_B_CLK_P

RX_B_3_N

RX_B_3_P

RX_A_0_N

RX_A_0_P

RX_B_0_N

RX_B_0_N

F149

330R

21

3V3_VCC

PANEL_VCC

CN101

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1

CN102

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10 9 8 7 6 5 4 3 2 1

S147

21

R578

10k

21

S148

21

PANEL_VCC

RX_A_0_N

S149

21

S150

21

3V3_VCC

S1522 1

RX_A_3_N

RX_A_CLK_P

RX_A_2_P

RX_A_2_N

RX_A_1_P

RX_A_1_N

RX_A_0_P

CN103

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

RX_A_0_P

RX_A_1_N

RX_A_1_P

RX_A_2_P

RX_A_CLK_P

RX_A_3_N

RX_A_CLK_N

C312

100n

10V

2 1

17MB25

ONDER GENC

LVDS INTERFACE 11114-28-2008_15:57

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:


DRAWN BY :

SHEET:

RX_A_3_P

RX_A_3_N

RX_A_CLK_P

RX_A_CLK_N

RX_A_2_P

RX_A_2_N

RX_A_1_P

RX_A_1_N

RX_A_0_P

RX_A_0_N

RX_B_3_P

RX_B_3_N

RX_B_CLK_P

RX_B_CLK_N

RX_B_2_P

RX_B_2_N

RX_B_1_P

RX_B_1_N

RX_B_0_P

RX_B_0_N

VDDP

VDDC

10k

R582

21

3V3_VCC

S146

21

3V3_VCC

R580

10k

21

PANEL_VCC

PANEL_VCC

S153

21

10V

100n

C311

2 1

10k

R581

21

MST6WB7GQ-3U138

271

270

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269LVB1M

LVB1P

LVB2M

LVB2P

LVBCKM

LVBCKP

LVB3M

LVB3P

LVB4M

LVB4P

GND16

VDDP6

LVA0M

LVA0P

LVA1M

LVA1P

LVA2M

LVA2P

LVACKM

LVACKP

LVA3M

LVA3P

LVA4M

LVA4P

VDDC4

GND15

LVB0P

LVB0M

6

RX_A_0_N

RX_A_CLK_N

RX_A_3_P

RX_B_3_P

RX_B_3_N

RX_B_CLK_P

RX_B_CLK_N

RX_B_2_P

RX_B_1_P

RX_B_1_N

RX_B_0_P

10k

R579

21

R577

10k

21

OPTION2

OPTION1

OPTION3

OPTION1

OPTION2

OPTION3

CN108

3029

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

BACKLIGHT_ON/OFF

S1352 1

CN105

5049

4847

4645

4443

4241

4039

3837

3635

3433

3231

3029

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

330R

F148

21

PANEL_VCC

PANEL_VCC

S1512 1

PANEL_VCC

S132 21

TP212

1

TP213 1

PANEL_VCC

TP225 1

RX_A_1_N

RX_A_1_P

BACKLIGHT_ON/OFF

RX_A_2_N

TP227 1

TP233 1

RX_A_2_P

RX_A_CLK_N

RX_A_CLK_P

RX_A_3_N

RX_A_3_P

TP234 1

RX_A_3_P

RX_A_2_N

S190

21

S191

21

RX_B_2_N

S133 21

MEGA_DCR_IN

3V3_VCCR90110k2 1

10kR902

2 1 3V3_VCC

10k

R903

21

3V3_VCC

MEGA_DCR_OUT

LVDS CABLE

PANEL_VCC = 5V/12V

PANEL_VCC = 5V

PANEL VCC = 5V/12V

26" TO 32" FFC OPTIONS

19" TO 22" FFC OPTIONS

F:\MENTOR_SASELER\17mb25-1\pcb\pcb.pcb - Page 1 of 1 pages.

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Documents

1. INTRODUCTION · 2017. 3. 29. · 3 1. INTRODUCTION 17MB25 mainboard is based on MSTAR concept IC. This IC is capable of handling audio processing, video processing, scaling-display