1, ID 2 ID 1€¦ · The circuit conﬁguration incorporates an input-parallel output-series boost converter with coupled inductors, clamp circuits and a voltage multiplier cell stacking

energies

Article

Interleaved High Step-Up DC-DC Converter Based onVoltage Multiplier Cell and Voltage-StackingTechniques for Renewable Energy Applications †

Shin-Ju Chen 1,* ID , Sung-Pei Yang 2 ID , Chao-Ming Huang 1, Huann-Ming Chou 2 andMeng-Jie Shen 1

1 Department of Electrical Engineering, Kun Shan University, Tainan 710, Taiwan;[email protected] (C.-M.H.); [email protected] (M.-J.S.)

2 Green Energy Technology Research Center, Kun Shan University, Tainan 710, Taiwan;[email protected] (S.-P.Y.); [email protected] (H.-M.C.)

* Correspondence: [email protected]; Tel.: +886-6-205-0323; Fax: +886-6-205-0298† This paper is extended version of paper published in Shin-Ju Chen, Sung-Pei Yang, Chao-Ming Huang,

Huann-Ming Chou, Meng-Jie Shen. Interleaved high step-up DC-DC converter based on voltage multipliercell and voltage-stacking techniques for renewable energy applications. In proceedings of 2018 IEEEInternational Conference on Applied System Innovation (IEEE ICASI 2018), Chiba, Tokyo, Japan, 13–17April 2018.

Received: 30 May 2018; Accepted: 20 June 2018; Published: 22 June 2018��

Abstract: A novel interleaved high step-up DC-DC converter based on voltage multiplier cell andvoltage-stacking techniques is proposed for the power conversion in renewable energy power systems.The circuit configuration incorporates an input-parallel output-series boost converter with coupledinductors, clamp circuits and a voltage multiplier cell stacking on the output side to extend thevoltage gain. The converter achieves high voltage conversion ratio without working at extreme largeduty ratio. The voltage stresses on the power switches are significantly lower than the output voltage.As a result, the low-voltage-rated metal-oxide-semiconductor field-effect transistors (MOSFETs) canbe employed to reduce the conduction losses and higher conversion efficiency can be expected. Theinterleaved operation reduces the input current ripple. The leakage inductances of the coupledinductors act on mitigating the diode reverse recovery problem. The operating principle, steady-stateanalysis and design guidelines of the proposed converter are presented in detail. Finally, a 1-kWprototype with 28-V input and 380-V output voltages was implemented and tested. The experimentalresults are presented to validate the performance of the proposed converter.

Keywords: high step-up DC-DC converter; interleaved operation; coupled inductor; voltagemultiplier cell

1. Introduction

Nowadays, demand for clean or renewable energy sources has dramatically increased withpopulation growth and the depletion of fossil fuel. Much effort has been made to explore renewableenergy sources, such as photovoltaic (PV), fuel cell and wind energy systems [1–3]. The renewableenergy grid-connected system with PV and fuel cells calls for high voltage-gain and high-efficiencydc-dc converters because the low voltage generated by the PV and fuel cells needs to be raised to ahigh voltage for the input of grid-connected inverter as shown in Figure 1. If the energy needs to beconverted to a single-phase 220 V ac voltage utility grid, a 380–400 V dc bus voltage is required for theinverter. However, the outputs of PV and fuel cells are generally lower than 40 V [4] due to safety and

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Energies 2018, 11, 1632 2 of 17

reliability considerations in home applications. Thus, a front-end DC-DC converter with about tentimes voltage gain is necessary to satisfy the requirement.Energies 2018, 11, x FOR PEER REVIEW 2 of 16

DC/DCConverter

High Step-Up Load

or Grid

DC/AC

Inverter

Low DC Voltage

High VoltageDC Bus

RenewableEnergy SourcesPV Panels/Fuel Cells

Figure 1. Diagram of a renewable energy power system.

In order to achieve high voltage gain, a conventional boost converter or an interleaved boost converter can be employed with operating an extreme large duty ratio. However, it causes several problems of high switching losses, severe output diode reverse-recovery losses, and electromagnetic interference (EMI) [5]. Furthermore, for a high output-voltage converter, therefore, the high-voltage-rated MOSFETs and diode with large conduction resistance are necessary due to the voltage stresses on the power devices are equal to the output voltage. It will result in large conduction and switching losses. In practice, the voltage gain of boost converters is limited due to the parasitic parameters effect [5]. These problems are the main limitations of disadvantages for the boost converters.

In the literature, a lot of converter topologies have been proposed to obtain high step-up voltage gain [6–22]. For coupled inductor-based converters [6–10], the high voltage gain can be achieved by adjusting the turns ratio of the coupled inductor and duty ratio. However, the power loss and high voltage stress on the power switches occur owing to the leakage inductance of the coupled inductor. The switched-capacitor converters [11,12] can also obtain high voltage conversion ratio. However, many switches are required for these converters, and thus it leads to complexity of design for the driving circuit. The high step-up converters without a coupled inductor or transformer are proposed in [13,14]. Several kinds of interleaved high step-up converters with voltage multiplier cells have been proposed in [15–19]. The interleaved converters with three-winding coupled inductors are proposed to achieve high voltage conversion ratio and low input current ripple [20–22]. However, they are a little complex and difficult to design, which results in the circuit complexity and cost problems.

A novel interleaved high step-up converter based on voltage multiplier cell and voltage-stacking techniques is proposed herein for high voltage gain and high-power applications, as shown in Figure 2a. The topology utilizes the two-phase interleaved boost converter with parallel-input series-output connection and introduces dual clamp circuits and a voltage multiplier cell stacking on the output side to obtain the higher voltage conversion ratio. The converter has the following features:

(1) The converter has high step-up voltage gain without operating at extreme large duty ratio. (2) The voltage stress on the power switches is significantly lower than the output voltage. The low-

voltage-rated MOSFETs with low on-resistances can thereby be adopted to reduce the conduction losses.

(3) The diode reverse-recovery problem can be alleviated by the leakage inductances of the coupled inductors for most of the diodes.

(4) Dual passive clamp circuits help to recycle the leakage energy of the coupled inductors and clamp the voltage stress of the power switches to a lower level.

(5) The input current ripple, reduces is minimized due to the current ripple cancellation in the interleaved operation. Additionally, increases power level can be increased due to the current-sharing performance in high current applications.

This paper is organized as follows. The proposed converter and its operating principle are illustrated in Section 2. The steady-state analysis, design guidelines and performance comparison of the proposed converter are presented in Section 3. The experimental results on a 1000 W prototype circuit are provided to validate the performance of the proposed converter in Section 4. Finally, some conclusions are made in the last section.

Figure 1. Diagram of a renewable energy power system.

In order to achieve high voltage gain, a conventional boost converter or an interleaved boostconverter can be employed with operating an extreme large duty ratio. However, it causes severalproblems of high switching losses, severe output diode reverse-recovery losses, and electromagneticinterference (EMI) [5]. Furthermore, for a high output-voltage converter, therefore, the high-voltage-ratedMOSFETs and diode with large conduction resistance are necessary due to the voltage stresses on thepower devices are equal to the output voltage. It will result in large conduction and switching losses. Inpractice, the voltage gain of boost converters is limited due to the parasitic parameters effect [5]. Theseproblems are the main limitations of disadvantages for the boost converters.

In the literature, a lot of converter topologies have been proposed to obtain high step-up voltagegain [6–22]. For coupled inductor-based converters [6–10], the high voltage gain can be achieved byadjusting the turns ratio of the coupled inductor and duty ratio. However, the power loss and highvoltage stress on the power switches occur owing to the leakage inductance of the coupled inductor.The switched-capacitor converters [11,12] can also obtain high voltage conversion ratio. However,many switches are required for these converters, and thus it leads to complexity of design for thedriving circuit. The high step-up converters without a coupled inductor or transformer are proposedin [13,14]. Several kinds of interleaved high step-up converters with voltage multiplier cells have beenproposed in [15–19]. The interleaved converters with three-winding coupled inductors are proposedto achieve high voltage conversion ratio and low input current ripple [20–22]. However, they are alittle complex and difficult to design, which results in the circuit complexity and cost problems.

A novel interleaved high step-up converter based on voltage multiplier cell and voltage-stackingtechniques is proposed herein for high voltage gain and high-power applications, as shown in Figure 2a.The topology utilizes the two-phase interleaved boost converter with parallel-input series-outputconnection and introduces dual clamp circuits and a voltage multiplier cell stacking on the output sideto obtain the higher voltage conversion ratio. The converter has the following features:

(1) The converter has high step-up voltage gain without operating at extreme large duty ratio.(2) The voltage stress on the power switches is significantly lower than the output voltage. The

low-voltage-rated MOSFETs with low on-resistances can thereby be adopted to reduce theconduction losses.

(3) The diode reverse-recovery problem can be alleviated by the leakage inductances of the coupledinductors for most of the diodes.

(4) Dual passive clamp circuits help to recycle the leakage energy of the coupled inductors and clampthe voltage stress of the power switches to a lower level.

(5) The input current ripple, reduces is minimized due to the current ripple cancellation inthe interleaved operation. Additionally, increases power level can be increased due to thecurrent-sharing performance in high current applications.

This paper is organized as follows. The proposed converter and its operating principle areillustrated in Section 2. The steady-state analysis, design guidelines and performance comparison ofthe proposed converter are presented in Section 3. The experimental results on a 1000 W prototype

Energies 2018, 11, 1632 3 of 17

circuit are provided to validate the performance of the proposed converter in Section 4. Finally, someconclusions are made in the last section.

2. Proposed Converter and Operating Principle

The proposed converter circuit is shown in Figure 2a, where S1 and S2 are the power switches,DC1 and DC2 are the clamp diodes, CC1 and CC2 are the clamp capacitors, D1 and D2 are the outputdiodes, C1 and C2 are the output capacitors, D3 and D4 are the switched diodes, C3 and C4 are theswitched capacitors, and Ro is the load. There are two coupled inductors in the proposed converter. Thecoupling references are marked by “·” and “∗”. The circuit model of each coupled inductor includes anideal transformer with the original turns ratio, which is in parallel with a magnetizing inductance andthen in series with a leakage inductance. The equivalent circuit of the proposed converter is shown inFigure 2b, where Lm1 and Lm2 are the magnetizing inductance, Lk1 and Lk2 are the inductance, Np andNs are the primary and secondary windings of the coupled inductors, respectively, and the turns ratioof the coupled inductor is defined as n = Ns1/Np1 = Ns2/Np2. The dual passive clamp circuits areused to recycle the leakage energy and suppress the turn off voltage spikes on the power switches.The voltage multiplier cell is realized by the secondary windings of the coupled inductors with seriesconnection, the switched diodes and the switched capacitors to increase the voltage gain.

Energies 2018, 11, x FOR PEER REVIEW 3 of 16

2. Proposed Converter and Operating Principle

The proposed converter circuit is shown in Figure 2a, where 1S and 2S are the power switches,

1CD and 2CD are the clamp diodes, 1CC and 2CC are the clamp capacitors, 1D and 2D are the output diodes, 1C and 2C are the output capacitors, 3D and 4D are the switched diodes, 3C and

4C are the switched capacitors, and oR is the load. There are two coupled inductors in the proposed converter. The coupling references are marked by “ ” and “ ∗ ”. The circuit model of each coupled inductor includes an ideal transformer with the original turns ratio, which is in parallel with a magnetizing inductance and then in series with a leakage inductance. The equivalent circuit of the proposed converter is shown in Figure 2b, where 1mL and 2mL are the magnetizing inductance, 1kL and 2kL are the inductance, pN and sN are the primary and secondary windings of the coupled inductors, respectively, and the turns ratio of the coupled inductor is defined as 11 ps N/Nn =

22 ps N/N= . The dual passive clamp circuits are used to recycle the leakage energy and suppress the turn off voltage spikes on the power switches. The voltage multiplier cell is realized by the secondary windings of the coupled inductors with series connection, the switched diodes and the switched capacitors to increase the voltage gain.

inV

2S1S

1pN 2pN

+

−

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

oV+

−ini

1C

*

*oR

Voltage multiplier cell

Clamp circuit

inV

2S1S

1pN 2pN

+

−

*

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

1mL 2mL

1kL 2kL

ini

1C

*

oV+

−oR

(a) (b)

Figure 2. Proposed converter and its equivalent circuit. (a) Proposed converter; (b) Equivalent circuit.

In the operational analysis, the proposed converter operates in continuous conduction mode (CCM), and the gate signals of the power switches are interleaved with the same duty ratio greater than 0.5 and a o180 phase shift. The key waveforms are shown in Figure 3. There are six operating modes in one switching period. The equivalent circuits for each mode are shown in Figure 4.

Mode 1 [ 0 1,t t ]: At 0tt = , the power switch 1S is turned on, and the power switch 2S remains in the turn-on state. The leakage current 1Lki rises quickly and its increasing rate is limited by 1kL . The magnetizing inductance 1mL still transfers energy to the secondary side of the coupled inductors charging the switched capacitor 3C . The diodes 1D , 2D , 4D , 1CD and 2CD are reverse-biased, and only the switched diode 3D is conducting as shown in Figure 4a. The current falling rate through the switched diode 3D is controlled by the leakage inductances 1kL and 2kL , which alleviates the diode reverse recovery problem. This mode ends when the current through the diode 3D decreases to zero at the instant 1t , and the diode 3D is turned off automatically. At the same time, the current through 1kL becomes equal to that of the magnetizing inductance 1mL .

Mode 2 [ 1 2,t t ]: During the time interval, both the switches 1S and 2S conduct, and all diodes are reverse-biased as depicted in Figure 4b. The magnetizing inductances 1mL and 2mL as well as

Figure 2. Proposed converter and its equivalent circuit. (a) Proposed converter; (b) Equivalent circuit.

In the operational analysis, the proposed converter operates in continuous conduction mode(CCM), and the gate signals of the power switches are interleaved with the same duty ratio greaterthan 0.5 and a 180

◦phase shift. The key waveforms are shown in Figure 3. There are six operating

modes in one switching period. The equivalent circuits for each mode are shown in Figure 4.Mode 1 [t0, t1]: At t = t0, the power switch S1 is turned on, and the power switch S2 remains

in the turn-on state. The leakage current iLk1 rises quickly and its increasing rate is limited by Lk1.The magnetizing inductance Lm1 still transfers energy to the secondary side of the coupled inductorscharging the switched capacitor C3. The diodes D1, D2, D4, DC1 and DC2 are reverse-biased, andonly the switched diode D3 is conducting as shown in Figure 4a. The current falling rate through theswitched diode D3 is controlled by the leakage inductances Lk1 and Lk2, which alleviates the diodereverse recovery problem. This mode ends when the current through the diode D3 decreases to zero atthe instant t1, and the diode D3 is turned off automatically. At the same time, the current through Lk1becomes equal to that of the magnetizing inductance Lm1.

Mode 2 [t1, t2]: During the time interval, both the switches S1 and S2 conduct, and all diodesare reverse-biased as depicted in Figure 4b. The magnetizing inductances Lm1 and Lm2 as well as the

Energies 2018, 11, 1632 4 of 17

leakage inductances Lk1 and Lk2 are linearly charged by the input voltage Vin. This mode ends at theinstant t2, when the switch S2 is turned off.

Mode 3 [t2, t3]: At t = t2, the switch S2 is turned off, which makes the diodes DC2 and D2 turn ondue to the continuity of the leakage current iLk2. The switch S1 remains in the turn-on state, as shown inFigure 4c. The energy kept by the magnetizing inductance Lm2 is transferred not only to the secondaryside of the coupled inductors but also to the output capacitor C2 and the clamp capacitor CC2. Thecurrent through Lk2 decreases and flows through two paths. One path is through CC1, D2, C2 andS2, so that the clamp capacitor CC1 is discharged and the output capacitor C2 is charged. The otherpath is through CC2 and DC2, so that the clamp capacitor CC2 is charged. This mode ends when S2 isturned on.


the leakage inductances 1kL and 2kL are linearly charged by the input voltage inV . This mode ends at the instant 2t , when the switch 2S is turned off.

Mode 3 [ 2 3,t t ]: At 2tt = , the switch 2S is turned off, which makes the diodes 2CD and 2D turn on due to the continuity of the leakage current 2Lki . The switch 1S remains in the turn-on state, as shown in Figure 4c. The energy kept by the magnetizing inductance 2mL is transferred not only to the secondary side of the coupled inductors but also to the output capacitor 2C and the clamp capacitor 2CC . The current through 2kL decreases and flows through two paths. One path is through

1CC , 2D , 2C and 2S , so that the clamp capacitor 1CC is discharged and the output capacitor 2C is charged. The other path is through 2CC and 2CD , so that the clamp capacitor 2CC is charged. This mode ends when 2S is turned on.

1gsv

1Lki

2Lki

1Di

1dsv

t

t

t

t

t2Di

t

2dsv

sT

t

sT21

0t 1t 2t 3t 4t 5t 6t

3Di

4Di

2gsv

t1Dv

t2Dv

t3Dv

t4Dv

t1DCv

t2DCv

1DCi2DCi

Figure 3. Key waveforms of the proposed converter. Figure 3. Key waveforms of the proposed converter.

Energies 2018, 11, 1632 5 of 17Energies 2018, 11, x FOR PEER REVIEW 5 of 16

inV

2S1S

1pN 2pN

+

−

*

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di2DCi

1mL 2mL

1kL 2kL

1DCi 2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

inV

2S1S

1pN

+

−

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di

1mL 2mL

1kL 2kL

2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

2pN

2DCi

1DCi

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

*

(a) (b)

inV

2S1S

1pN 2pN

+

−*

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di

1mL 2mL

1kL 2kL

2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

2DCi

1DCi

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

inV

2S1S

1pN 2pN

+

−

*

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di

1mL 2mL

1kL 2kL

2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

2DCi

1DCi

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

(c) (d)

*

inV

2S1S

1pN 2pN

+

−

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di

1mL 2mL

1kL 2kL

2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

2DCi

1DCi

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

inV

2S1S

1pN 2pN

+

−

*

2sN1sN4D

1CD

3D

2D

2CD 1D

1CC

2C

3C

4C

2CC

OV+

−

1Di

1mL 2mL

1kL 2kL

2Di

2CV+

−

4CV+

−

3CV+

−

4Di

3Di1Lki

ini

2Lki

1C

4Dv+

−

3Dv+

−

1CV+

−

2Dv +−

+ 1Dv −

2DCi

1DCi

1DCv +−

1CCV +−

2CCV+ −

+ 2DCv −

*

(e) (f)

Figure 4. Operating modes of the proposed converter. (a) Mode 1; (b) Mode 2; (c) Mode 3; (d) Mode 4; (e) Mode 5; (f) Mode 6.

Mode 4 [ 3 4,t t ]: At 3t t= , the power switch 2S is turned on, and the power switch 1S remains in the turn-on state. The diodes 1D , 2D , 3D , 1CD and 2CD are reverse-biased, and only the switched diode 4D is conducting as shown in Figure 4d. The current through the leakage inductance

Figure 4. Operating modes of the proposed converter. (a) Mode 1; (b) Mode 2; (c) Mode 3; (d) Mode 4;(e) Mode 5; (f) Mode 6.

Energies 2018, 11, 1632 6 of 17

Mode 4 [t3, t4]: At t = t3, the power switch S2 is turned on, and the power switch S1 remains inthe turn-on state. The diodes D1, D2, D3, DC1 and DC2 are reverse-biased, and only the switched diodeD4 is conducting as shown in Figure 4d. The current through the leakage inductance Lk2 rises quickly,and the current through the leakage inductance Lk1 falls quickly. The stored energy in the magnetizinginductance Lm2 still transfers to the secondary side of the coupled inductors charging the switchedcapacitor C4. As the current through the leakage inductance Lk2 increases, the secondary side currentof the coupled inductors decreases. The of the current through the switched diode D4 decreases andits falling rate controlled by the leakage inductances Lk1 and Lk2, which alleviates the diode reverserecovery problem. This mode ends when the diode current iD4 decreases to zero at t = t4, and D4

is turned off automatically. At the same time, the current through Lk2 becomes equal to that of themagnetizing inductance Lm2.

Mode 5 [t4, t5]: The operating state of modes 5 and 2 are similar. During this interval, all diodesare turned off, as shown in Figure 4e. The magnetizing inductances Lm1 and Lm2 as well as the leakageinductances Lk1 and Lk2 are charged linearly by the input voltage Vin. This mode is terminated as theswitch S1 is turned off.

Mode 6 [t5, t6]: The switch S1 is turned off at t = t5, which turns on the diodes DC1 and D1.The switch S2 remains in turn-on state. The current-flow path of this mode is shown in Figure 4f.The energy stored in the magnetizing inductance Lm2 begins to transfer to the secondary side of thecoupled inductors charging the switched capacitor C3 via the switched diode D3. The current throughthe diode D3 is controlled by the leakage inductances Lk1 and Lk2. The leakage current iLk1 decreasesand flows to the clamp capacitor CC1 via DC1 and S2, meanwhile it flows to the output capacitor C1

and the clamp capacitor CC2 via D1 and S2. The time t6 is the ending of a switching period Ts whenthe power switch S1 is turned on again.

3. Steady-State Analysis and Design Guidelines

In order to simplify the performance analysis of the proposed converter, the following assumptionsare made.

(1) Voltages on the capacitors are regarded as constant over one switching period due to theirsufficiently large capacitances.

(2) All of the power devices are ideal. The on-resistance Rds(ON) and parasitic capacitances of thepower switches are ignored, and the forward voltage drops of the diodes are neglected.

(3) The leakage inductances of the couple inductors are much smaller than the magnetizinginductances, and, therefore, they are neglected.

(4) The switching period is Ts. The power switches operate with the same duty ratio D and 180◦

outof phase.

3.1. Voltage Gain

Since the time intervals of modes 1 and 4 are very short, only modes 2, 3, 5 and 6 were consideredfor the steady-state analysis. Based on the operating principle discussed in the aforementioned section,the charging voltage of the magnetizing inductance Lm is the input voltage Vin during the switch is inthe turn-on state for time DTs, and the discharging voltage is the clamp voltage VCC1 or VCC2 minusthe input voltage Vin during the switch is in the turn-off state for time (1 − D)Ts. By applying thevoltage-second balance to the magnetizing inductance, the voltages on the clamp capacitors CC1 andCC2 can be calculated analogously to the output voltage of the conventional boost converter, whichcan be derived from

VCC1 = VCC2 =1

1 − DVin. (1)

Energies 2018, 11, 1632 7 of 17

At modes 3 and 6, the voltages on the output capacitors C2 and C1 can be derived from Figure 4c,f,respectively. They can be expressed as

VC2 = VCC1 + VCC2 =2

1 − DVin, (2)

VC1 = VCC1 + VCC2 =2

1 − DVin. (3)

Moreover, the voltage on the switched capacitors C4 and C3 can also be derived from Figure 4c,f,respectively. The results are given by

VC4 = nVin − n(Vin − VCC2) =n

1 − DVin, (4)

VC3 = nVin − n(Vin − VCC1) =n

1 − DVin. (5)

From Figure 4b,e, it can be found that the output voltage is the sum of VC1, VC2, VC3 and VC4.With the results of Equations (2)–(5), the output voltage can be derived from

Vo = VC1 + VC2 + VC3 + VC4 =2n + 41 − D

Vin. (6)

Therefore, the voltage gain of the proposed converter is given by

Vo

Vin=

2n + 41 − D

. (7)

Equation (7) confirms that the proposed converter has a high step-up voltage gain withoutadopting an extremely large duty ratio. The curve of the voltage gain related to the turns ratio of thecoupled inductor n and duty ratio D is shown in Figure 5. As the turns ratio of the coupled inductorsincreases, the voltage gain is extended significantly. When the duty ratio is only 0.6, the voltage gainreaches 15 with the turns ratio n = 1.


2 1 22

1= + =

−C CC CC inV V V VD

, (2)

1 1 22

1= + =

−C CC CC inV V V VD

. (3)

Moreover, the voltage on the switched capacitors 4C and 3C can also be derived from Figure 4c,f, respectively. The results are given by

4 2= ( )=1

− −−C in in CC innV nV n V V VD

, (4)

3 1= ( )=1

− −−C in in CC innV nV n V V VD

. (5)

From Figure 4b,e, it can be found that the output voltage is the sum of 1CV , 2CV , 3CV and 4CV . With the results of Equations (2)–(5), the output voltage can be derived from

1 2 3 42 41o C C C C innV V V V V V

D+

= + + + =−

. (6)

Therefore, the voltage gain of the proposed converter is given by

2 41

o

in

V nV D

+=

−. (7)

Equation (7) confirms that the proposed converter has a high step-up voltage gain without adopting an extremely large duty ratio. The curve of the voltage gain related to the turns ratio of the coupled inductor n and duty ratio D is shown in Figure 5. As the turns ratio of the coupled inductors increases, the voltage gain is extended significantly. When the duty ratio is only 0.6, the voltage gain reaches 15 with the turns ratio 1=n .

Figure 5. Voltage gain of the proposed converter verse duty ratio for several turns ratio n.

3.2. Voltage Stresses on Semiconductor Devices

The voltage ripples on the capacitors are neglected to simplify the voltage stress analysis of the power switches and diodes. From Figure 4c,f, the power switch 1S or 2S is turned off and the drain-source voltages of 1S and 2S is equal to the voltages on the clamp capacitors 1CC and 2CC , respectively. Thus, the voltage stresses on the power switches 1S and 2S can be derived from

0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.950

10

20

30

40

50

60

70

80

Duty Ratio (D)

Vol

tage

Gai

n (V

o/V

in)

n=1n=3n=5

Figure 5. Voltage gain of the proposed converter verse duty ratio for several turns ratio n.

Energies 2018, 11, 1632 8 of 17

3.2. Voltage Stresses on Semiconductor Devices

The voltage ripples on the capacitors are neglected to simplify the voltage stress analysis ofthe power switches and diodes. From Figure 4c,f, the power switch S1 or S2 is turned off and thedrain-source voltages of S1 and S2 is equal to the voltages on the clamp capacitors CC1 and CC2,respectively. Thus, the voltage stresses on the power switches S1 and S2 can be derived from

VS1−stress = VS2−stress =1

1 − DVin =

12n + 4

Vo. (8)

It can be seen that the switch voltage stress is greatly lower than the output voltage and itdecreases greatly as the turns ratio of the coupled inductor increases. As a result, the low-voltage-ratedMOSFETs with low on-resistance can be employed and the conversion efficiency can be improved.

From the operating modes of the proposed converter, the voltage stresses of the output diodes D1

and D2 are equal to the voltages VC1 and VC2, respectively. The voltage stresses of the switched diodesD3 and D4 are the voltage VC3 plus the voltage VC4. The voltage stresses of the output and switcheddiodes can be expressed as

VD1−stress = VD2−stress =2

1 − DVin =

1n + 2

Vo, (9)

VD3−stress = VD4−stress =2n

1 − DVin =

nn + 2

Vo. (10)

At mode 3, the voltage stress of the clamp diode DC1 can be obtained as the sum of the voltagesVCC1 and VCC2. On the other hand, the voltage stress of the clamp diode DC2 is equal to the voltageVCC2 from Figure 4f. Therefore, the voltage stresses of the clamp diodes can be given by

VDC1−stress =2

1 − DVin =

1n + 2

Vo, (11)

VDC2−stress =1

1 − DVin =

12n + 4

Vo. (12)

Equations (8)–(12) show that the proposed converter has the property of low voltage stresseson the semiconductor devices. The relationship between the normalized semiconductor-devicevoltage stresses and the turns ratio is depicted in Figure 6. It can be seen that the voltage stresseson S1, S2, D1, D2, DC1 and DC2 decreases as the turns ratio n increases. The voltage stress on D3

and D4 increases as the turns ratio n increases, but it is always lower than the output voltage.Therefore, the low-voltage-rated MOSFETs with low on-resistance Rds(ON) and Schottky diode withoutreverse-recovery time can be used to improve the efficiency.

Energies 2018, 11, 1632 9 of 17


1 21 1

1 2 4S stress S stress in oV V V VD n− −= = =

− +. (8)

It can be seen that the switch voltage stress is greatly lower than the output voltage and it decreases greatly as the turns ratio of the coupled inductor increases. As a result, the low-voltage-rated MOSFETs with low on-resistance can be employed and the conversion efficiency can be improved.

From the operating modes of the proposed converter, the voltage stresses of the output diodes 1D and 2D are equal to the voltages 1CV and 2CV , respectively. The voltage stresses of the

switched diodes 3D and 4D are the voltage 3CV plus the voltage 4CV . The voltage stresses of the output and switched diodes can be expressed as

1 22 1

1 2D stress D stress in oV V V VD n− −= = =

− +, (9)

3 42

1 2D stress D stress in on nV V V VD n− −= = =

− +. (10)

At mode 3, the voltage stress of the clamp diode 1CD can be obtained as the sum of the voltages

1CCV and 2CCV . On the other hand, the voltage stress of the clamp diode 2CD is equal to the voltage

2CCV from Figure 4f. Therefore, the voltage stresses of the clamp diodes can be given by

12 1

1 2DC stress in oV V VD n− = =

− +, (11)

21 1

1 2 4DC stress in oV V VD n− = =

− +. (12)

Equations (8)–(12) show that the proposed converter has the property of low voltage stresses on the semiconductor devices. The relationship between the normalized semiconductor-device voltage stresses and the turns ratio is depicted in Figure 6. It can be seen that the voltage stresses on 1S , 2S ,

1D , 2D , 1CD and 2CD decreases as the turns ratio n increases. The voltage stress on 3D and 4D increases as the turns ratio n increases, but it is always lower than the output voltage. Therefore, the low-voltage-rated MOSFETs with low on-resistance (ON)dsR and Schottky diode without reverse-recovery time can be used to improve the efficiency.

Figure 6. Normalized semiconductor-device voltage stresses versus turns ratio n.

0 1 2 3 4 5 6 7 8 9 100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vst

ress

/Vo

n

VS1,VS2,VDC2VDC1,VD1,VD2VD3,VD4

Figure 6. Normalized semiconductor-device voltage stresses versus turns ratio n.

3.3. Design Guidelines

3.3.1. Turns Ratio Design

The voltage gain expression is given in Equations (7). A proper turns ratio n can be obtained oncethe voltage gain is assigned and the duty ratio D is designed, which is given by

n =(1 − D)Vo

2Vin− 2. (13)

3.3.2. Power Switches and Diodes Selection

According to Equations (8)–(12), the voltage stresses of the semiconductor devices are obtained,which can be employed to select the power devices. In practice, voltage spikes may occur duringthe switching transition process due to the effect of the leakage inductance and parasitic capacitor.Therefore, a reasonable margin of safety is necessary for the voltage rating of the selected power devices.

3.3.3. Coupled Inductor Design

A good criterion for designing the magnetizing inductance is to maintain the continuous-conduction mode (CCM) and set an acceptable current ripple in the magnetizing inductance ofthe coupled inductor. Assume that the coupled inductors have the same magnetizing inductance, thatis Lm1 = Lm2 = Lm. The magnetizing inductance current ripple can be expressed as

∆iLm =VinLm

DTs. (14)

The average magnetizing current is given by

ILm =V2

o2VinRo

. (15)

For the CCM operation of the proposed converter, the following condition holds

ILm − 12

∆iLm > 0. (16)

Energies 2018, 11, 1632 10 of 17

Substituting Equations (14) and (15) into Equation (16), the magnetizing inductance can bedetermined for the CCM operation, which is given by

Lm>D(1 − D)2Ro

4(n + 2)2 fs, (17)

where fs is the switching frequency and Ro is the load.

3.3.4. Capacitor Design

In the preceding analysis, the capacitors are assumed to be very large to keep their voltagesconstant. In practice, the voltages cannot be kept constant with a finite capacitance. An acceptablevoltage ripple is the main consideration in designing the capacitors. The relationship of the voltageripple and the capacitance is given by

∆VC = ∆Q/C, (18)

where ∆Q is the change in charge or discharge, and ∆VC is the voltage ripple on the capacitor C.The output capacitor C1 is discharged by the load current Io during modes 2, 3 and 5. The total

time is equal to DTs. Therefore, the voltage ripple can be obtained as

∆VC1 =IoDTs

C1=

DVo

C1Ro fs. (19)

Substituting Equation (3) into Equation (19), it can be expressed by the following equation.

∆VC1 =(n + 2)DVC1

C1Ro fs. (20)

It is useful to rearrange the equation to express required capacitance in terms of specified voltageripple for the output capacitor C1, which is given by

C1 =(n + 2)D

(∆VC1/VC1)Ro fs. (21)

Similarly, the output capacitor C2, switched capacitors C3 and C4, and clamp capacitors can bederived to express required capacitance in terms of specified voltage ripple, which are given by

C2 =(n + 2)D

(∆VC2/VC2)Ro fs, (22)

C3 =(2n + 4)D

(∆VC3/VC3)nRo fs, (23)

C4 =(2n + 4)D

(∆VC4/VC4)nRo fs, (24)

CC1 =2n + 4

(∆VCC1/VCC1)Ro fs, (25)

CC2 =2n + 4

(∆VCC2/VCC2)Ro fs, (26)

where ∆VC2, ∆VC3, ∆VC4, ∆VCC1 and ∆VCC2 are the tolerant voltage ripples on the capacitors C2, C3,C4, CC1 and CC2, respectively.

Energies 2018, 11, 1632 11 of 17

3.4. Performance Comparison

The performance comparison between the converters published in [20–22] and the proposedconverter is shown in Table 1. The relationship between the voltage gain and the duty ratio in theseconverters with the turns ratio n = 1.5 is shown in Figure 7. It can be seen that the voltage gain ofthe proposed converter is higher than the other converters. In fact, if the turns ratio n of the coupledinductor is designed by less than 3, then the voltage gain of the proposed converter is the highest.Moreover, the voltage stress on the switches and the highest voltage stress on diodes of the proposedconverter are the lowest among the compared converters. The component number of the proposedconverter is less than that of the converter published in [21]. Clearly, the proposed converter is suitablefor the high step-up and high voltage applications.

Table 1. Converter performance comparison.

Topology ConverterPublished in [20]

ConverterPublished in [21]

ConverterPublished in [22]

ProposedConverter

Voltage gain 2n+21−D

3n+11−D

2n+21−D

2n+41−D

Voltage stress onswitches

Vo2n+2

Vo3n+1

Vo2n+2

Vo2n+4

The highest voltagestress on diodes

(2n+1)Vo2n+2

2nVo3n+1

(2n+1)Vo2n+2

2nVo2n+4

Switches 2 2 2 2Diodes 6 8 6 6

Capacitors 5 7 5 6Coupled inductors 2 2 2 2


Table 1. Converter performance comparison.

Topology Converter

Published in [20] Converter

Published in [21] Converter

Published in [22] Proposed Converter

Voltage gain 2 +21

nD−

3 +11

nD−

2 +21

nD−

2 +41

nD−

Voltage stress on switches 2 +2

oVn

3 +1

oVn

2 +2

oVn

2 +4

oVn

The highest voltage stress on diodes

(2 +1)2 +2

on Vn

23 +1

onVn

(2 +1)

2 +2on V

n

22 +4

onVn

Switches 2 2 2 2 Diodes 6 8 6 6

Capacitors 5 7 5 6 Coupled inductors 2 2 2 2

Figure 7. Voltage gains versus duty ratio with turns ratio n = 1.5.

4. Experimental Verifications

To validate the performance and effectiveness of the proposed converter, a 1000 W laboratory prototype with 28-V input and 380-V output voltages was built and tested with the specifications and parameters shown in Table 2. The experimental results shown in the Figures 8–15 are measured under full-load conditions 1000 W.

Table 2. Components and parameters of the prototype.

Components Parameters Input voltage Vin 28 V

Output voltage Vo 380 V Maximum output power Po 1000 W

Switching frequency fs 50 kHz Magnetizing inductances Lm1 and Lm2 245 µH

Leakage inductances Lk1 and Lk2 0.9 µH Turns ratio n 1

Switches S1 and S2 IRFP4321 Diodes DC1, DC2, D1, D2, D3, D4 30CPQ200

0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.950

10

20

30

40

50

60

70

80

Duty Ratio (D)

Vol

tage

Gai

n (V

o/V

in)

Converters in [20] and [22] Converter in [21] Proposed converter

Figure 7. Voltage gains versus duty ratio with turns ratio n = 1.5.

4. Experimental Verifications

To validate the performance and effectiveness of the proposed converter, a 1000 W laboratoryprototype with 28-V input and 380-V output voltages was built and tested with the specifications andparameters shown in Table 2. The experimental results shown in the Figures 8–15 are measured underfull-load conditions 1000 W.

Energies 2018, 11, 1632 12 of 17

Table 2. Components and parameters of the prototype.

Components Parameters

Input voltage Vin 28 VOutput voltage Vo 380 V

Maximum output power Po 1000 WSwitching frequency fs 50 kHz

Magnetizing inductances Lm1 and Lm2 245 µHLeakage inductances Lk1 and Lk2 0.9 µH

Turns ratio n 1Switches S1 and S2 IRFP4321

Diodes DC1, DC2, D1, D2, D3, D4 30CPQ200Clamp capacitors CC1 and CC2 10 µFOutput capacitors C1 and C2 100 µF

Switched capacitors C3 and C4 100 µF

Figure 8 shows t waveforms of the interleaved PWM signals vgs1 and vgs2, the input voltageVin = 28 V and the output voltage Vo = 380 V. The duty ratio is about 0.58. Thus, the high step-upvoltage gain is realized without operating at an extremely large duty ratio. The waveforms of gatesignals and the drain-source voltages vds1 and vds2 are shown in Figure 9. It can be seen that the voltagestresses on the power switches are about 63 V, which is only one-sixth of the output voltage. Thus, onecan adopt low-voltage-rated devices to reduce the conduction and switching losses.


Clamp capacitors CC1 and CC2 10 µF Output capacitors C1 and C2 100 µF


Figure 8 shows t waveforms of the interleaved PWM signals 1gsv and 2gsv , the input voltage

inV = 28 V and the output voltage oV = 380 V. The duty ratio is about 0.58. Thus, the high step-up voltage gain is realized without operating at an extremely large duty ratio. The waveforms of gate signals and the drain-source voltages 1dsv and 2dsv are shown in Figure 9. It can be seen that the voltage stresses on the power switches are about 63 V, which is only one-sixth of the output voltage. Thus, one can adopt low-voltage-rated devices to reduce the conduction and switching losses.

1: 20V/divgsv

2: 20V/divgsv

: 400V/divoV

: 20V/divinV

10us/div :Time Figure 8. Measured waveforms of the gating signals and the input and output voltages.

Figure 9. Measured waveforms of the gating signals and the drain-source voltages of power switches.

Figure 10 depicts the waveform of the voltages on the output capacitors and the switched capacitors. Because the turns ratio n is equal to one, the voltages 3CV and 4CV are half of 1CV and

2CV . The experimental results are in a good agreement with the theoretical analysis given in Equations (2)–(5). Figure 11 shows the voltages on the clamp capacitors. It can be seen that the voltage ripple is small, which can clamp the voltage stress of the power switches. Figure 12 shows the waveforms of the input current and the currents through the leakage inductances. As can be seen, the currents through the leakage inductances are interleaved such that the input current ripple is very small. The average current of is quite similar to , which is a half of the input current. Thus, the current sharing performance is good due to the symmetrical interleaved structure.

1Lki 2Lki

Figure 8. Measured waveforms of the gating signals and the input and output voltages.


Clamp capacitors CC1 and CC2 10 µF Output capacitors C1 and C2 100 µF


Figure 8 shows t waveforms of the interleaved PWM signals 1gsv and 2gsv , the input voltage

inV = 28 V and the output voltage oV = 380 V. The duty ratio is about 0.58. Thus, the high step-up voltage gain is realized without operating at an extremely large duty ratio. The waveforms of gate signals and the drain-source voltages 1dsv and 2dsv are shown in Figure 9. It can be seen that the voltage stresses on the power switches are about 63 V, which is only one-sixth of the output voltage. Thus, one can adopt low-voltage-rated devices to reduce the conduction and switching losses.

1: 20V/divgsv

2: 20V/divgsv

: 400V/divoV

: 20V/divinV

10us/div :Time Figure 8. Measured waveforms of the gating signals and the input and output voltages.


Figure 10 depicts the waveform of the voltages on the output capacitors and the switched capacitors. Because the turns ratio n is equal to one, the voltages 3CV and 4CV are half of 1CV and

2CV . The experimental results are in a good agreement with the theoretical analysis given in Equations (2)–(5). Figure 11 shows the voltages on the clamp capacitors. It can be seen that the voltage ripple is small, which can clamp the voltage stress of the power switches. Figure 12 shows the waveforms of the input current and the currents through the leakage inductances. As can be seen, the currents through the leakage inductances are interleaved such that the input current ripple is very small. The average current of is quite similar to , which is a half of the input current. Thus, the current sharing performance is good due to the symmetrical interleaved structure.

1Lki 2Lki


Figure 10 depicts the waveform of the voltages on the output capacitors and the switchedcapacitors. Because the turns ratio n is equal to one, the voltages VC3 and VC4 are half of VC1 and VC2.

Energies 2018, 11, 1632 13 of 17

The experimental results are in a good agreement with the theoretical analysis given in Equations(2)–(5). Figure 11 shows the voltages on the clamp capacitors. It can be seen that the voltage rippleis small, which can clamp the voltage stress of the power switches. Figure 12 shows the waveformsof the input current and the currents through the leakage inductances. As can be seen, the currentsthrough the leakage inductances are interleaved such that the input current ripple is very small. Theaverage current of iLk1 is quite similar to iLk2, which is a half of the input current. Thus, the currentsharing performance is good due to the symmetrical interleaved structure.Energies 2018, 11, x FOR PEER REVIEW 13 of 16

10us/div :Time

1: 100V/divCV

2: 100V/divCV

3: 40V/divCV

4: 40V/divCV

Figure 10. Measured waveforms of the voltages on the switched capacitors and the output capacitors.

10us/div :Time

1: 100V/divCCV

2: 100V/divCCV

Figure 11. Measured waveforms of the voltages on the clamp capacitors.

Figure 12. Measured waveforms of the input current and the currents through the leakage inductances.

Figures 13–15 depict the voltage and current waveforms on the clamp diodes, output diodes and switched diodes, respectively. One can see that the reverse recovery currents are very small because the current falling rates are controlled by the leakage inductances. As a result, the reverse recovery losses are alleviated. The voltage stress on the clamp diode 2CD is half of that on clamp diode 1CD, which is consistent with the theoretical analysis in Equations (11) and (12). The voltage stress on output diodes and switched diodes 1D – 4D are almost identical to the turns ratio n of one, which is in agreement well with the theoretical analysis in Equations (9) and (10). The overvoltage and ringing on the diodes 3D and 4D are larger than to the other diodes, as shown in Figure 15. This is a result of the simplified equivalent circuit with the leakage inductance introduced only on the primary side

: 50A/divini

10us/div :Time

1: 20A/divLki

2: 20A/divLki



10us/div :Time

1: 100V/divCV

2: 100V/divCV

3: 40V/divCV

4: 40V/divCV


10us/div :Time

1: 100V/divCCV

2: 100V/divCCV




: 50A/divini

10us/div :Time

1: 20A/divLki

2: 20A/divLki



10us/div :Time

1: 100V/divCV

2: 100V/divCV

3: 40V/divCV

4: 40V/divCV


10us/div :Time

1: 100V/divCCV

2: 100V/divCCV




: 50A/divini

10us/div :Time

1: 20A/divLki

2: 20A/divLki


Figures 13–15 depict the voltage and current waveforms on the clamp diodes, output diodes andswitched diodes, respectively. One can see that the reverse recovery currents are very small because

Energies 2018, 11, 1632 14 of 17

the current falling rates are controlled by the leakage inductances. As a result, the reverse recoverylosses are alleviated. The voltage stress on the clamp diode DC2 is half of that on clamp diode DC1,which is consistent with the theoretical analysis in Equations (11) and (12). The voltage stress onoutput diodes and switched diodes D1–D4 are almost identical to the turns ratio n of one, which is inagreement well with the theoretical analysis in Equations (9) and (10). The overvoltage and ringing onthe diodes D3 and D4 are larger than to the other diodes, as shown in Figure 15. This is a result of thesimplified equivalent circuit with the leakage inductance introduced only on the primary side suchthat the clamp circuits are ineffective, to limit the overvoltage on D3 and D4. Furthermore, the voltagestresses of all the diodes are much lower than the output voltage.

In order to obtain a regulated and constant output voltage in spite of input voltage variation andoutput load disturbance, the closed-loop control with type III compensator is implemented [23]. Thereare three poles (one at the origin) and two zeros provided by this compensation. The experimentalresult under the step load change from half load 500 W to full load 1000 W and vice versa is illustratedin Figure 16. It can be seen that the transient voltage ripple of the output voltage is small and insensitiveto the load change. This means that the compensator design can deliver a dynamic performance. Theexperimental conversion efficiency of the presented converter is given in Figure 17, which is measuredby the power analyzer (HIOKI 3390). The full-load efficiency is about 86% and the peak value ofefficiency is 94.5% obtained at the output power of 200 W.


such that the clamp circuits are ineffective, to limit the overvoltage on 3D and 4D . Furthermore, the voltage stresses of all the diodes are much lower than the output voltage.

1: 20A/divDCi

2: 20A/divDCi

2: 100V/divDCv

1: 100V/divDCv

10us/div :Time Figure 13. Measured waveforms of the voltages and currents on the clamp diodes.

1: 10A/divDi

2: 10A/divDi

2: 100V/divDv

1: 100V/divDv

10us/div :Time Figure 14. Measured waveforms of the voltages and currents on the output diodes.

3: 20A/divDi

4: 20A/divDi

4: 100V/divDv

3: 100V/divDv

10us/div :Time

Figure 15. Measured waveforms of the voltages and currents on the switched diodes.

In order to obtain a regulated and constant output voltage in spite of input voltage variation and output load disturbance, the closed-loop control with type III compensator is implemented [23]. There are three poles (one at the origin) and two zeros provided by this compensation. The experimental result under the step load change from half load 500 W to full load 1000 W and vice versa is illustrated in Figure 16. It can be seen that the transient voltage ripple of the output voltage

Figure 13. Measured waveforms of the voltages and currents on the clamp diodes.



1: 20A/divDCi

2: 20A/divDCi

2: 100V/divDCv

1: 100V/divDCv


1: 10A/divDi

2: 10A/divDi

2: 100V/divDv

1: 100V/divDv


3: 20A/divDi

4: 20A/divDi

4: 100V/divDv

3: 100V/divDv

10us/div :Time



Figure 14. Measured waveforms of the voltages and currents on the output diodes.

Energies 2018, 11, 1632 15 of 17



1: 20A/divDCi

2: 20A/divDCi

2: 100V/divDCv

1: 100V/divDCv


1: 10A/divDi

2: 10A/divDi

2: 100V/divDv

1: 100V/divDv


3: 20A/divDi

4: 20A/divDi

4: 100V/divDv

3: 100V/divDv

10us/div :Time





is small and insensitive to the load change. This means that the compensator design can deliver a dynamic performance. The experimental conversion efficiency of the presented converter is given in Figure 17, which is measured by the power analyzer (HIOKI 3390). The full-load efficiency is about 86% and the peak value of efficiency is 94.5% obtained at the output power of 200 W.

: 200V/divov

: 1A/divoi

Time: 10ms/div Figure 16. Output voltage response with step load change.

Figure 17. Experimental conversion efficiency of the implemented converter.

5. Conclusions

A new interleaved high step-up DC-DC converter based on voltage multiplier cell and voltage-stacking technique is proposed. The high step-up voltage conversion can be achieved without working at extremely large duty ratio. The switch voltage stress is much lower than the output voltage such that the low-voltage-rated power devices with low on-resistance can be adopted to reduce the conduction losses. Dual passive clamp circuits help to recycle the leakage energy of the coupled inductors and clamp the voltage stress of the switches to a lower level. The interleaved operation reduces the input current ripple. The diode reverse-recovery problem is alleviated by the leakage inductances of the coupled inductors for most of the diodes. The operating principle, the steady-state analysis and design guidelines of the proposed converter are presented. Finally, a 1000 W prototype converter was built and tested to validate the converter’s performance.

Author Contributions: S.-J.C. and S.-P.Y. conceived and designed the converter circuit. M.-J.S. performed the experiments. C.-M.H. and H.-M.C. analyzed the performance. S.-J.C. wrote the manuscript.

Funding: The authors gratefully acknowledge financial support from the Ministry of Science and Technology, Taiwan, under the grant number MOST 106-2632-E-168-001.

Conflicts of Interest: The authors declare that there is no conflict of interest.

Figure 16. Output voltage response with step load change.


is small and insensitive to the load change. This means that the compensator design can deliver a dynamic performance. The experimental conversion efficiency of the presented converter is given in Figure 17, which is measured by the power analyzer (HIOKI 3390). The full-load efficiency is about 86% and the peak value of efficiency is 94.5% obtained at the output power of 200 W.

: 200V/divov

: 1A/divoi

Time: 10ms/div Figure 16. Output voltage response with step load change.


5. Conclusions

A new interleaved high step-up DC-DC converter based on voltage multiplier cell and voltage-stacking technique is proposed. The high step-up voltage conversion can be achieved without working at extremely large duty ratio. The switch voltage stress is much lower than the output voltage such that the low-voltage-rated power devices with low on-resistance can be adopted to reduce the conduction losses. Dual passive clamp circuits help to recycle the leakage energy of the coupled inductors and clamp the voltage stress of the switches to a lower level. The interleaved operation reduces the input current ripple. The diode reverse-recovery problem is alleviated by the leakage inductances of the coupled inductors for most of the diodes. The operating principle, the steady-state analysis and design guidelines of the proposed converter are presented. Finally, a 1000 W prototype converter was built and tested to validate the converter’s performance.

Author Contributions: S.-J.C. and S.-P.Y. conceived and designed the converter circuit. M.-J.S. performed the experiments. C.-M.H. and H.-M.C. analyzed the performance. S.-J.C. wrote the manuscript.

Funding: The authors gratefully acknowledge financial support from the Ministry of Science and Technology, Taiwan, under the grant number MOST 106-2632-E-168-001.



5. Conclusions

A new interleaved high step-up DC-DC converter based on voltage multiplier cell andvoltage-stacking technique is proposed. The high step-up voltage conversion can be achieved without

Energies 2018, 11, 1632 16 of 17

working at extremely large duty ratio. The switch voltage stress is much lower than the output voltagesuch that the low-voltage-rated power devices with low on-resistance can be adopted to reduce theconduction losses. Dual passive clamp circuits help to recycle the leakage energy of the coupledinductors and clamp the voltage stress of the switches to a lower level. The interleaved operationreduces the input current ripple. The diode reverse-recovery problem is alleviated by the leakageinductances of the coupled inductors for most of the diodes. The operating principle, the steady-stateanalysis and design guidelines of the proposed converter are presented. Finally, a 1000 W prototypeconverter was built and tested to validate the converter’s performance.

Author Contributions: S.-J.C. and S.-P.Y. conceived and designed the converter circuit. M.-J.S. performed theexperiments. C.-M.H. and H.-M.C. analyzed the performance. S.-J.C. wrote the manuscript.

Funding: The authors gratefully acknowledge financial support from the Ministry of Science and Technology,Taiwan, under the grant number MOST 106-2632-E-168-001.


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© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open accessarticle distributed under the terms and conditions of the Creative Commons Attribution(CC BY) license (http://creativecommons.org/licenses/by/4.0/).



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1, ID 2 ID 1€¦ · The circuit conﬁguration incorporates an input-parallel output-series boost converter with coupled inductors, clamp circuits and a voltage multiplier cell stacking