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Hogan’s Notes For visit to JPL.

Present from JPL/CIT: Kieran, Pekka, Todd, Rodrigo, Mary Present from FNAL: Donna Kubik, Fritz DeJongh, HNSept 3-4th 2009

Warm DC Power-draw test of W-band Modules

Block diagram W-band Module

d1

d2

d3

d4

hybrid

LNA1 LNA2 PS LNA3

Leg A

Leg B

Test Goal:

To verify drain currentsof the Low Noise Amplifiers (LNA) areclose to nominal.

To verify gate voltages required toturn on/off the drain current areclose to nominal.

Detects shorts and opens

Nominal Values----------------------------------Drain Voltage 0.7 VDrain current 10-15 mAGate Current 1.6 uA

Gate Voltage required to openthe drain current 0.5 V

Procedure

1. No inputs into Legs A or B

2. Turn off ALL Gate Voltages, set Drain Voltage to nominal.

3. Turn ON a Gate voltage to nominal, and record corresponding Drain current.

Kieran performs warm DC power-draw test manually on every module. Test takes approximately 15 minutes per module.

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Warm RF Isolation Optimization of W-band Modules

Magic T (0,180 deg) coupler

Ea

Eb

(PSA,PSB) = (+1,+1)---------------------------------D1 S(GAS(Ea,Eb),GBD(Ea,Eb))D2 D(GAS(Ea,Eb),GBD(Ea,Eb))D3 S(D1,iD2) D4 D(D1,-iD2)

Purpose: Expose module to RF power from room T BB source, and from swept RF source.

Adjust Gains GA and GB to optimize isolation

W-band

S(Ea,Eb)

D(Ea,Eb)

Notation

Ea,Eb are E-field Vectors

S(Ea,Eb) = (Ea+Eb)/sqrt(2)

D(Ea,Eb) = (Ea-Eb)/sqrt(2)

GA = Gain in Leg A

GB = Gain in Leg B

SG = GA + GB and DG = GA - GB

PSA,PSB = phase switch states of Leg A and Leg B

p1,…,p4 = detector diode pedestals, defined as when PSA,PSB are both OFF

Without loss of generality, let the pedestals p1,…,p4 = 0.

D1,…,D4 = Inputs to the Detector Diodes

(PSA,PSB) = (+1,-1)---------------------------------D1 S(GAS(Ea,Eb),-GBD(Ea,Eb))D2 D(GAS(Ea,Eb),-GBD(Ea,Eb))D3 S(D1,iD2) D4 D(D1,-iD2)

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(PSA,PSB) = (+1,+1)---------------------------------D1 = S(GAS(Ea,Eb),GBD(Ea,Eb)) D2 = D(GAS(Ea,Eb),GBD(Ea,Eb)) D3 = S(D1,iD2) D4 = D(D1,-iD2)

Writing out the detector diode input signals

D1 = { SGEa + DGEb}/2

D2 = { SGEb + DGEa}/2

D3 = {(SG + iDG)Ea + (DG + iSG)Eb)}/(2sqrt(2))

D4 = {(SG - iDG)Ea + (DG - iSG)Eb)}/(2sqrt(2))

Special Case 1:

Assume ideal case where gains are matched, so GA=GB=G.

D1 = GEa D3 = (Ea + iEb)G/sqrt(2) D2 = GEb D4 = (Ea - iEb)G/sqrt(2)

Special Case 2 (and Equalized Leg Gains)

If inputs Ea and Eb are from BB sources with temperatures Ta and Tb, then Ea and Eb are relatively incoherent.

<D1> = G2 Ta

<D2> = G2 Tb

<D3> = G2 (Ta + Tb)/2

<D4> = G2 (Ta + Tb)/2

where < > denotes the time-averaged detector diode outputs.

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Magic T (0,180 deg) coupler

W-band

S(Ea,Eb)

D(Ea,Eb)

18.7 GHZ RF GeneratorFreq sweep

Agilent 83751BSynthesizedSweeper*

8x freq up-converter

manual rotaryvane

attenuatorset to32 dB

(99,1) combiner

300K BB

300KBB

A

B

DiodePower

Frequency

D1

D2

Ideal case, where gain and phase is matched. D2 shows no “cross-talk” from function generator. See special case 1, slide 3.

DiodePower

Frequency

D1

D2

Typical case, where gain and phase is not matched exactly. D2 shows “cross-talk” from function generator.

Kieran manually adjusts the gate voltages to match gain and phase, to optimize the isolation.

Freq. Sweep to Optimize Isolation

For (PSA,PSB) = (+1,+1)

*For Phase II, CIT will purchase a “Hittite” 20 GHz FG for $8K

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Magic T (0,180 deg) coupler

W-band

S(Ea,Eb)

D(Ea,Eb)

300K BB

HEMT amplifier

calibratedmanual rotaryvane

attenuator

(99,1) combiner

20K BB

30KBB

A

B

DiodePower

Setting on Vane Attenuator

D2

Y-factor (or Module Temperature Determination)

For (PSA,PSB) = (+1,+1)

WaveGuide

Isolator*

* Wave Guide Isolator prevents feed-backinto the output of the HEMT amplifier.See eg. Microwave Resources Inc. model FRW 110.

Test is done COLD

D4

D1D3

Vane Attenuator Setting corresponds to a temperature seen by diodes D1, D3, D4 (see slide 3)

For (PSA,PSB) = (+1,+1), D2 only sees only a constant 30K BB source if isolation is ideal.

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Other Notes about W-band module design:

The best LNA is placed mostupstream.

LNA1,3 are the same design, and have different band pass from LNA2. The combo gives flat band pass. In practice BW = 13 GHz (design is 19 GHz).

Generally, only astronomy cares about coldMMICs. For non-astronomical applications,device views ~300K bodies, so they don’t care about low temperature MMIC’s. So Northrop-Grumman has not optimized the case for cold MMICs.

Other Notes about JPL W-band Procedure for QUIET PHASE-1

Every MMIC (LNA’s, Phase Switches, Hybrid)was warm-tested at the wafer level.

Voltages were set manually for all tests. Rotary vane attenuator was set manually. Frequency was automatically swept. Detector Diode outputs were recorded automatically. Warm DC Power-Draw Test took 15 minutes permodule.

Every module that survived the Warm DC Power-Draw test was “MADE TO WORK”. Kierandid what he could to get the best isolation.Every functional module was needed, so none were rejected by the isolation optimization procedure.

Warm DC Isolation Optimization took 30 minutesper module.

With module cold, Kieran re-determined the bestisolation, and measured the Diode noises. This took 2 hours per module, not including cool downtime. Every module was cold-tested by Kieran.Modules can work at room T, but problems such as oscillations can show up when cold. Isolation optimization takes 40-45 min. Y-factor test takes 40-45 min. All per module.

Kieran’s voltages (optimized for best isolation) was used by Chicago as input to their algorithm, to optimize the sensitivity.

Kieran demonstrated a Y-factor test doneat room T on Module #26. At this temperature, T module = 575K, which Kieran says is typical.

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Notes on DC Power Filtering

Filtration of DC power sent to the modules must be done, otherwise the V-spikes above 2 volts can destroy the MMICs.

JPL also used 5-to-1 voltage divider to reduce the spikes.

Filter caps of varying strengthsalong the DC power line.

For Phase 1 testing, Kieran/JPL used power supplies from “Berkshire Technologies PS-16M”. Berkshire now out of business.

My notes aren’t detailed about this portion. Rely on Donna’s and Fritz’s notes on DC filtering.

W-band module

4R

R

Ground

DC Voltage

“big cap”farther from MMIC

“little cap”near to MMIC

GroundGround

Other Teststand and tools

JPL is setting up a single-LNA teststand, butmust utilize the heterodyne technique since the gain of single LNA gain is too small.

JPL uses the HP-EPM441A power meter to calibrate their equipment.

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Phase II discussions (w/ Todd, Kieran)

CIT/JPL plan to cold-test every MMIC at the wafer level.

JPL recently award a grant (Not KISS) forMMIC R&D. Will look at 35 nm waferprocess.

HN says that technically-limitedFNAL production schedule, could begin 1 yrfrom Sept. 09.

Non-MMIC components (ie Alumina strip lines)are also long-lead time items. But did notget info on what the lead time was. FNALagreed to handle the procurement of all butthe MMIC components.

Our knowledge of the institutions involved in some aspect of W-band modules for phase II are:

Caltech/JPL MMIC delivery, Small Scale Module TestingChicago Receiver Int. (with FNAL)FNAL Assembly, Module Testing, Receiver Int. (with Chicago) KEK Module Testing, Receiver Int.MPI Receiver Int. at the 66 module levelPrinceton Receiver Int.

For Phase II, Todd says it will be impractical to test every module via a single-module teststand the way it was done for Phase I (ala Kieran-style).

CIT/JPL will have a warm/cold module teststand, at the single-module level.

KEK has shown work on multiple-module cold test stand. It was shown at the QUIET meeting at FNAL in June-09. Teststand requires horn, OMT, BB, grid, etc…

It was unclear to us the MPI plans for module testing.

FNAL will likely do production warmtesting of all modules:

- Warm DC Power-Draw test- Warm RF testing (Dave McGinnis recommendation)

FNAL will have a cold teststand.The level of cold module production testing is under discussion. We’rewary that cold-testing all modules could be very time consuming.

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Module Assembly Discussions

Mary showed us how she applies Ag Epoxy, ie. with a “Swiss Oiler”. MPEG movie was taken by Fritz.

In applying waveguide coupler, mustremove Ag Epoxy that leaks into the waveguide. Mary uses a small mirror to see into the waveguide, and a small pick to scrape the glue.

HN asked whether parts can be placeddown in random order. Mary says it will be difficult, since we would need good position and part size tolerance.

Kieran gave us miniature Alumina parts and bad LNA’s to practice pick-and-place at FNAL.

Pekka says probably ok to use double wire-bonds instead of ribbon bonds.

Top of LNA needs grounding, and this was done by Indium wrapping. For Phase II, everyone agreed that could be done easier by adding a small pedestal to the brass chassis, and then wirebonding to it.

pedestalAg Epoxy

wirebond

LNA

Waveguide coupler

Scrape off ExcessAg Epoxy

Waveguide channel

HN says that pick-and-placing the small capswill be hard. Kieran says that NxGen also haddifficulty too, as they used up more capacitorsthan anticipated. Pekka says o.k. to use 3-packcapacitors, to increase the device size.

Pekka says it is critical to get Epoxy to uniformly cover the substrate, to ensure goodadhesion and for RF properties.

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JPL and NxGen experience with W-bandmodule assembly (for Phase I)

Kieran recalls Todd saying that NxGen may have done a few assemblies manually, due to inconsistencies.

NxGen did not get the dies to attach well initially. They used too little epoxy. So the wire/ribbon bonds were done against a springy surface (bad), rather than a hard surface (good). So there was wire/ribbon bonding failure.

Due to time pressure, modules that came back from Chicago for repair had multiple fixes done to them, to ensure that the module would work. Didn’t have time to do systematic debugging. Some of the fixes were probably not necessary.

At HN’s request, Kieran provided a document (reproduced here) to summarize experience with Phase I assembly.

This document attempts to answer Hogan’s questions about our experience with the QUIET Phase-I modules. I have only considered the final 48 modules which were die-attached at NxGen and completed at JPL.

1 What is the success rate for NxGen for die attachment?

This question is difficult to answer for the following reasons. The result of die attachment is not binary. A substrate may function, but under-perform, if the die attachment is not optimal. For example, if insufficient epoxy has been used on an RF substrate, the RF path may still function, albeit with higher loss.

In many cases, the MMIC amplifier chips needed to be replaced either because they were visibly damaged or because they were not performing well (usually identified through a process of elimination). Since the chips were individually tested prior to selection, we assume that the chips must have been damaged after this.

However, at this point we cannot tell whether the damage occurred while preparing kits for NxGen, or during the die attachment process at NxGen.

If a module does not work satisfactorily, a process of troubleshooting is carried out to identify the location of the problem(s). Due to time constraints, the lack of certainty about the origin of the problem and the desire to minimize the number of times a module is opened, rework may involve many changes at once.

For example, a loose bond may be re-bonded, an apparently loose substrate is replaced, epoxy is cleaned from various areas, etc. Then the module is tested again. If the module works, it is often not obvious which of the various ‘fixes’ resulted in the improvement.

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Therefore it is not always possible to associate a given problem with its solution. In the example given, it is not clear if a bond had failed or a substrate was loose. This makes it difficult to compile bond or die-attachment failure rates in general.

A common problem with the modules was a detected level on one or both legs of the polarimeter which was too low. It was usually difficult to identify which MMIC in the chain was responsible and so the MMICs were replaced in a process of elimination.

Thus, some MMICs were inevitably replaced even though they were functioning correctly. Also, if a MMIC chip was replaced on one leg, it was not always possible to ensure that it was from the same wafer as the corresponding chip on the other leg. If the new chip was from a different wafer, then the corresponding chip on the other leg would also be replaced. Therefore, not every case of MMIC replacement was due to a faulty chip which might result from a die-attachment fault.

Taking the above into consideration, for 5/48 modules loose substrates were recorded which were replaced. For 12/48 modules, the replacement of amplifier, phase-switch or hybrid chips was recorded.

2 What is the success rate for JPL for die attachment? Detailed re-work records were not kept for the JPL die-attached modules.

3 What is the success rate for JPL for wire or ribbon bonding ?

24/48 modules had at least one wire bonding problem; there were 31 recorded wire bonding problems in all.

These fall into two categories: bonding errors (11/31, e.g. missing or misplaced bonds) and bond quality (20/31, e.g. bonds too low or high and therefore shorting to case, ).

When considered on a per module basis, this is a high module failure rate (50%).

However, considering that a typical module will have over 200 bonds, then this is much lower (0.3%) bond failure rate.

4 What were the repairs that you/JPL had to do? Table 1 lists the categories of re-work that we had to do in Phase I.