1. General Description · 2017. 5. 11. · 02h Program-verify, Erase-verify 11h Pattern-program, Pattern-erase (Note 1) Refer to “Test flow guide” for more information of test

5.0V MTP (Multi-Time Programmable) Macro IP Block For 0.18um BCD Process of Dongbu Hitek Product Code: WD18MB_32B/64B/128B/256B/512B

Rev.1C

1. General Description “WD18MB_32B/64B/128B/256B/512B” is a 1P3M (one-poly, three-metal), non-volatile MTP (Multi-

Time Programmable) Macro IP block which is embedded into 0.18um BCD process of DBH.

Key features

5V Single power supply

Read frequency : 5MHz

Read data bus : x8

Byte Erase : 10msec ( typical )

Byte Program : 10msec ( typical )

Low active current : 2mA ( Max. ) at 5MHz

Low write current: 1.5mA ( Max. )

Idle mode for low power consumption : 1uA ( typical )

Data retention : more than 10 years

E/W cycle endurance: Min. 1K

Table. 1 Available MTP Macro blocks

Product code Memory organization Address bits Address range

WD18MB_512B 512 x 8 ADD[8:0] 0h ~ 1FFh

WD18MB_256B 256 x 8 ADD[7:0] 0h ~ FFh

WD18MB_128B 128 x 8 ADD[6:0] 0h ~ 7Fh

WD18MB_64B 64 x 8 ADD[5:0] 0h ~ 3Fh

WD18MB_32B 32 x 8 ADD[4:0] 0h ~ 1Fh

0.18um BCD process, WD18MB Datasheet (Rev.1C)

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Embedded MTP (180nm Dongbu Hitek BCD)

Fig 1. Circuit block diagram

HV Generator

Address

Decoder

Control

Logic

X-D

eco

de

rMain Memory

Write Decoder

YMUX, DOUT Latch

DIN[7:0]

ADD

(Address)

CEn

CLK

RSTn

WEn

ERSn

PGMn

PDEn

MODE[4:0]

DOUT[7:0]

Table 2. Signal description

Symbol Pin name Function

MODE[4:0] Mode select bits To select the functional modes.

ADD[AMS:0] Address inputs Memory addresses.

DIN [7:0] Data inputs Input data for write.

DOUT[7:0] Data outputs Output data for read.

CEn Chip Enable To activate the device

CLK Clock Clock for reading data from the memory.

WEn Write Enable To control write operations.

RSTn Reset Enable To reset the device

ERSn Erase Enable To erase the memory.

PGMn Program Enable To program the memory.

PDEn Idle mode Enable

To force the device into the idle mode, in which the power

consumption of the device is deeply suppressed down to less

than 5uA typically.

Note 1 ) AMS : The Most Significant Address Bit


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2. Functional Modes

Two groups of functional modes are provided. Main functions for normal user application, while test

modes for wafer-level test. Each function can be selected by mode bits (MODE [4:0]) with two key

signals (PGMn, ERSn).

Table 3. Functional modes and Mode selection bits ( MODE[4:0] )

Group MODE[4:0] Name of function Operational

base

Functional

type PGMn ERSn

Main mode 00h

Read

Byte

Read H H

Byte-program Write

L H

Byte-erase H L

Test mode for

wafer-level test

01h Bulk-program, Bulk-erase

02h Program-verify, Erase-verify

11h Pattern-program, Pattern-erase

(Note 1) Refer to “Test flow guide” for more information of test modes.

(Note 2) All functions in table above should be completely set up into the main customer design by a user.

Table 4. Pin description and status for basic functions.

Main Modes

Idle Reset Standby Read Write operations

x8 Erase Program

MODE[4:0] X X X 0h 0h 0h

ADD [AMS:0] X X X Ain Ain Ain

Din[7:0] X X X X X Input data

DOUT[7:0] X X X Output data X X

CEn X X H L L L

CLK X X X Toggle X X

WEn X X X H L L

ERSn X X X H L H

PGMn X X X H H L

RSTn X L H H H H

PDEn L H H H H H

(Note 1 ) X (Don’t care or unknown): Vil or Vih for input pins, Vol or Voh for output pins

(Note 2 ) Ain : Address Input


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3. Read Just after the device is powered up, it automatically enters the read mode.

The device should be first enabled by CEn before reading any data. Read operation is driven by CLK

signal and ATD signal (Address Transition Detect) is internally generated at the rising edge of CLK, at

which “data sensing” is started. But, the address (ADD) should be kept stable during the whole period

of the read operation for getting a correct data because they are not internally latched. “Read access

time” is defined as the sum of tRAS, tATD, and tATO as described in the timing diagram below.

Fig 2. Read Operation Timing Diagram

RSTn

MODE[4:0]

CEn

CLK

ADD

DOUT[7:0]

tRS

tMODE

tRC

tCES tRAS tATD tRAH

n n+1 n+2

Invalid Valid (n) Valid (n+1)

tATO

00h

Table 5.

Symbol Parameter Min. Typ. Max. Unit

tRC Read Cycle Time 5 MHz

tATD CLK High Width Time 100 ns

tRAS Read Address Setup Time 0 ns

tRAH Address Hold Time 20 ns

tATO CLK Low to Valid Output Time 20 ns

tCES CEn Setup Time 10 us

tMODE Mode set-up time 0 ns

tRS RSTn Setup Time 10 us

tVPES PGMn/ERSn Setup Time 0 ns

Note 1 ) For read access time, Cload (Load Capacitance at output) is assumed to be less than 0.3pF.


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4. Byte-program Operation

“Byte-program” (to change “bit 1” to “0”) is operated with a byte base (8 bits).

To perform the program operation, user should load data (DIN[7:0]) first at an address location to

which an user wants to write data. At minimum, 10msec of program time (tPGM) is needed.

Only “bit 1” can be changed to “0” by program operation. Meanwhile, “bit 0” can’t be changed back to

“1” by program operation. “Bit 0” can return to “bit 1” only by erase operation. So, erase operation

should be first executed before performing any program operation.

It should be noted that byte address (ADD) and data (Din [7:0]) should be kept stable for the whole

program operation, as shown in the Fig.3. This is because the data and address are not latched

internally by the device.

Recovery Time (tPGMH) from Program

Program (writing data) is actually performed during the period of tPGM, in which some high biases

are internally generated. Therefore, 10usec of recovery time (tPGMH) is required for the device to

return to the normal mode after the program operation is completed.

Fig. 3 Program Timing Diagram

CEn

MODE

ADD

PGMn

WEn

tMODE

Byte Program = 00h, Bulk Program=01h, CKB Program=11h

tCES

tAS/tDS

tPGMS tPGMH

tAH/tDH

tCEH

tCEHW

Valid Address

tPGM

DIN[7:0] Valid Data Input

Resetting an internal

register by CEn high

Resetting an internal register by CEn high

For a write operation, an internal register is used. So, this internal register needs to be reset (cleared)

by letting CEn go high before starting any other following operations like read, verify, erase, and

program, as shown in the figure 3.


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5. Byte-erase Operation

“Byte-erase” (to change bit “0” to “1”) is operated with a byte base (8 bits). To perform the erase

operation, user should first load an address location of the byte to erase. At least, 10msec of erase

time (tER) is needed. It should be noted that “bit 0” can return to “bit 1” only by erase operation.

Byte address (ADD) should be kept stable for the whole erase operation, as shown in the Fig.4. This

is because the address is not latched internally by the device.

10usec of recovery time (tERH) is required for the device to return to the normal mode after the

erase is completed.

Fig. 4 Erase Timing Diagram

CEn

MODE

ADD

ERSn

WEn

tMODE

Byte Erase = 00h, Bulk Erase = 01h

tCES

tAS

tERS tERH

tAH

tCEH

tCEHW

Valid Address

tER

Table. 6


tCES CEn to Address/Data setup time 10 us

tAS Address Setup Time 20 ns

tAH Address Hold Time 20 ns

tDS Data Input Setup time 20 ns

tDH Data Input Hold time 20 ns

tPGMS PGMn Low to WEn Low setup time 100 ns

tPGM Program time 10 ms

tPGMH WEn High to PGMn High hold time 10 us

tERS ERn Low to WEn Low setup time 100 ns

tER Erase time 10 ms

tERH WEn High to ERn High hold time 10 us

tCEH ADD/Data to CEn High hold time 0 ns

tCEHW CEn High width time 20 ns


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6. Stand-by Mode When CEn is driven to high, the device goes to “stand-by mode”, in which most of the internal circuits

of the device except some analog circuit parts are disabled and the output DOUT[7:0] gets invalid

(with random logic values, low or high). In this stand-by mode, less than 20uA (typically) of the

operating current is consumed through the entire device.

7. Idle mode When PDEn is driven to low, the device goes to the so called “idle mode” in which all internal circuits

of the device is completely disabled and the output DOUT[7:0] gets invalid. Under this mode, less

than 5uA (typical) of the current is consumed over the entire device.

And, at least 100usec of wake-up time (tWAKE) is required for the device to get woken up to the

normal read mode, exiting out of the idle mode.

Fig. 5 Idle mode

tIDLE

ICC

PDEn

CEn

Idle current (ipd)

tWAKE

Active read Current

Table 7.


tIDLE Idle mode enable Time 5 us

tWAKE Wake Up Time 100 us

8. Device Reset When the device is reset, the following operations take place.

All internal registers and latches are completely reset.

Any operations in progress are immediately terminated.

When a write operation is terminated by reset, the data which is being written can be

corrupted and its integrity of the MTP Macro block will not be guaranteed.

10usec of set-up time (tRS) is needed for the device to return to normal (read) mode after the

device gets out of reset state.


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Fig. 6 Reset

RSTntRSTL

CEn

tRS

Table 8.


tRSTL RSTn Low Width Time 20 ns

tRS RSTn Setup Time for read 10 us

9. Safe power-up and down by device reset

During power-up and down, all electrical signals and environments get unstable until Vcc power-

supply voltage is fully ramped up or ramped down to a specific voltage level.

Under this unstable situation, some unwanted noise can be generated and added to specific input

pins like PGMn or ERSn. In this case, some part of data stored in the MTP macro IP block can be

changed or corrupted by such unstable writing signals. Therefore, PDEn or RSTn signal needs to be

securely kept low until Vcc reaches to a specific level of voltage.

Fig. 7 Main Circuit & MTP Macro IP block

Customer’s Main circuit block

MTP Macro IP block

RSTn or

PDEn

VCC


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Fig. 8 Device reset during power-up and power-down

Voltage

time

Vcc 5.5V max.

4.5V

> 3.0V > 3.0V

RSTn or PDEn

tSR (100us)

tRSTS (0ns)

CEn

Table 9.


tRSTS RSTn Set Time 0 ns

tSR System Ready during power-up 100 us


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10. DC Operating Characteristics

Table 10.

Description Symbol Condition Min Typ Max Unit

Operation Temperature Temp. Read -40 25 125

℃ Write -40 25 125

Power Supply Voltage VDD 4.5 5.0 5.5 V

Stand By Current ISB CEn= High 10 30 μA

Idle Current Ipd PDEn=Low 1 5 μA

Read Current ICC

0MHz (CLK = Low) 0.2 mA

1MHz 1 mA

5MHz 2 mA

Write Current IWR VDD 1 1.5 mA

Input Low Voltage VIL -0.3 0 0.5 V

Input High Voltage VIH VDD -0.3 VDD VDD +0.3 V

Output High Voltage VOH Ioh=1uA 0.9 X VDD 1.1 X VDD V

Output Low Voltage VOL Iol=1uA -0.3 0.1XVDD V

Input Capacitance CIN VIL=0V; Temp. 25℃ 0.1 pF

Output Capacitance COUT VIL=0V; Temp. 25℃ 0.3 pF

(Note) The write current in average (IWR) is 1.5mA at max., but its peak current is 5mA at max.


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Revisions Revision No: Rev.0A (Draft)

DEC 04, 2013

Revised by S.D Kim ( [email protected] )

Initial release of the datasheet (preliminary version)

Revision No: Rev.0B

APR 14, 2014

Modified by Albert ([email protected])

-. Idle mode for low power consumption: Typ. 5uA … p1

-. tIdle value changed from max 5us to min 5us … Table8. p12

-. Added tVPES : Table4.p6 & Fig6.p10

-. Deleted OEn pin & related signal.

-. tATO changed from 100ns to 20ns.

-. VIH, VIL, VOH, VOL Changed. Table9. p13

-. tRS changed from 100ns to 10us. Table7. p11

-. MODE MODE revised. Table2. p4 & Fig2. p5 & Fig6. p10

-. TMPADH deleted. Fig1. p2 & Table1. p3

Revision No: Rev.0C

APR 18, 2014

Modified by Albert ([email protected])

-. tRS changed from 100ns to 10us. Table4. p6

-. DIN[7:0] don’t care for Erase operation revised. Table3. p4

-. Figure including tRAH revised. Fig2. p5 & Fig6. p10

-. Operation temperature & VIL revised. Table9. p13

Revision No: Rev.0D

JUN 12, 2014

Modified by sdkim ([email protected])

-. TBD Deleted p1

Revision No: Rev.1A

Jan 2, 2015 (Newly described over the entire document)


Revision No: Rev.1B

Jul 21, 2015


-. Temperature changed to 125C from 85C p10

Revision No: Rev.1C

Jan 7, 2016


-. Idle Current changed to 1uA/5uA from 5uA/30uA p10

-. Standby Current changed to 10uA/30uA from 20uA/200uA p10

-. Write Current changed to 1.5mA/5uA from 2mA p10

mailto:[email protected]


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Documents

1. General Description · 2017. 5. 11. · 02h Program-verify, Erase-verify 11h Pattern-program, Pattern-erase (Note 1) Refer to “Test flow guide” for more information of test