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“Fast FPGA-based trigger and data acquisition system for the CERN experiment NA62: architecture and algorithms”

AuthorsG. Collazuol(a), S. Galeotti(b), E. Imbergamo(c), G. Lamanna(d), G. Magazzù(b), M. Sozzi (d)

(a) Scuola Normale Superiore and INFN section of Pisa, Italy(b) INFN section of Pisa, Pisa, Italy

(c) University of Perugia and INFN section of Perugia, Italy(d) University of Pisa and INFN section of Pisa, Italy

Speaker: E. ImbergamoDSD08, September 3-5 2008, Parma, Italy

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Application framework

Elementary particle physics NA62 experiment (CERN laboratories) Status of designing/prototyping Design of the DAQ and trigger system

Input data rate 10-15 Mhz Input data bandwidth ~ 2 TB/sec Number of input channels ~ 20K No undetected electronics failures up to 10-7

Out of the shelf electronics

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Trigger & daq tradition / our challenge

L0 & L1: very fast & fast (~0.1 & 1. µs) logic conditions in dedicated hardware

Duplicate channels // create special assemblies

L2: partial reconstruction in on-line processors (~1-10ms)

L3: full reconstruction in off-line pc-farm

Our challenge: a common trigger & daq systemOur challenge: a common trigger & daq system

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Hardware building blocks

HPTDC chip (Time to Digital Converter, developed by CERN) 100 ps resolution/channel 32 input channels (LVDS) // daisy chain-able Programmable via JTAG

TDCB board (4xHPTDCs, Altera StratixII, QPLL, miniature connectors)

TDCs configuration // readout // emulation // data pre-processing

TELL1 board (4xTDCB, 4+1xAltera Stratix, 4x96MB SDRAM, 4x GigaBitEthernet, 1xControl PC, developed by EPFL Lausanne)

Data buffering // Implement L0 trigger primitive // Interface to the software level of trigger

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Hardware building blocks (TDCB)

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Hardware building blocks (TELL1)

GBE

CCPC

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Example of building blocks assembly

4x512 input channels (times)

Input data buffered in TELL1

L0-L1 primitives evaluated in daisy chained TELL1s

Make trigger decision (L0T)

Send trigger decision (TTC)

Transmit input data to PCs

Trigger decision evaluated Trigger decision evaluated on the same readout dataon the same readout data

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L0-L1 primitive definition (I)

Tell1

Count matching times Multiplicity threshold

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L0-L1 primitive definition (II)

Produce full list of times (no append, rather merge) Send the list to the L0T Predictable/fixed latency

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L0-L1 primitive implementation

Histogram-like algorithm Map times into time-bins of preset length For any new time increment the number of entries for the corresponding time-bin

Simple VHDL description Naively: N counters and one mux Very few resources: 100 Stratix LEs Up to 260 Mhz operating rate on our -7 speed grade Scalable

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Preliminary hardware characterization

Clock stability issue (40MHz input to TDCs)

Measured ~20ps (rms) jitter Cables (signal detector inputs to TDCs)

Delicate issue (hard manufacturing) TDC resolution (pulser inputs to TDCs)

Better than 90ps (rms) resolution

Intrinsic TDC performance seems to be achievedIntrinsic TDC performance seems to be achieved

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Conclusion

We are developing a triggerless-like trigger and daq system for high energy physics application

Key building blocks functionality looks fine

Time-matching algorithms have been designed for implementation in FPGA replacing traditional electronics for “coincidences”.

Hardware characterization/prototyping has started