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1
Extending Atmel FPGA Flow
Nikos Andrikos
TEC-EDM, ESTEC, ESA, NetherlandsDAUIN, Politecnico di Torino, Italy
NPI Final Presentation
25 January 2013 - ESTEC
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Making Atmel FPGA Flow Work
Nikos Andrikos
TEC-EDM, ESTEC, ESA, NetherlandsDAUIN, Politecnico di Torino, Italy
NPI Final Presentation
25 January 2013 - ESTEC
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Outline
• Introduction• FPGAs in Space• Atmel FPGAs• Atmel IDS
• Methodology
• Results
• Conclusion
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Field Programmable Gate Arrays
• General purpose configurable circuitso Compared to Application-Specific Integrated
Circuits (ASICs)
• Proso Rapid prototypingo Fixed cost per unito Reprogrammability
• Conso Lower performanceo Higher power consumption
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FPGAs in Space
• Aforementioned advantageso Increased momentun in their usage in space
• Electronic circuits subject to radiationo Need for radiation hardening
• ITAR regulationso Increased bureaucracyo Preventing export to embargoed countries (e.g.
China)
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Atmel FPGAs
• The only FPGA option that iso RAD-hardo ITAR-free Suitable for ESA applications
• Many technologies availableo 180nm AT58KRHA 180nm CMOS
ATF280 Family (used in this project)o AT40KEL040 350nm CMOSo ATFS450 150nm SOI
Available in the future
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Atmel IDS
• Atmel Integrated Development Systems (IDS)o Default software to program Atmel FPGAso Provided by Atmel
• But,o Has not been significantly updated recentlyo Usability issueso Obsolete algorithms Leaves much to be desired
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IDS Examples
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Outline
• Introduction
• Methodology• Scope of the work• Default flow• Proposed flow• VPLACE• Experimental Setup
• Results
• Conclusion
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Scope of Work
• Improve IDS flowo Usability issueso Explore various implementation options
• Try alternative algorithmso VPLACE for placement
• Quantative evaluationo Use of various designso Comparison between default IDS and VPLACE
algorithms
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Default Flow
• Hardware specificationo Hardware Description
Language (HDL)
• Mentor Precisiono Logic Synthesis
• Atmel IDSo Technology mappingo Placemento Routingo Bitstream Generation
HDL
Tech Mapping
Placement
Routing
Bitstream
Atmel IDS
Netlist
Mentor Precision
Logic Synthesis
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Proposed Flow
• Automate the flowo Makefile usageo Constraint generationo Tool invocationo Optimize IDS options
• Replace IDS placemento Parse project DBo VPLACE placemento Update project DB
Tech Mapping
Placement
Routing
Bitstream
Netlist
HDL
Mentor Precision
Atmel IDS
Logic Synthesis
DB Parse
Placement
DB Update
VPLACE
Project DB
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VPLACE
• Academic algorithm for FPGA placemento Previously developed in Politecnico di Torino, Italyo Already used for Xilinx FPGAs
• Algorithm still not optimized for Atmelo Not timing-driveno Not tuned for Atmel architectureso But, already promising results
• Project database (DB) interfaceo Specifically developed during this projecto Reverse-engineering of Atmel DB format (.fgd)o Around 3K C++ lines of code
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Experimental Setup
• Compare the two flowso Implementation targeting ATF280 FPGA familyo IDS vs VPLACE placemento Compare performance (circuit period)
• Use of designs of interesto ITC ‘99 benchmarks (initial verification)o HurriCANe 5.2.4 (CAN bus)o Crf 0.90 (by Astrium Crisa)
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Outline
• Introduction
• Methodology
• Results• ITC/HurriCANe• CRF
• Conclusion
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Results 1/2
Design IDS VPLACE Diff % Design IDS VPLACE Diff %
HurriCANe 91.6 89.6 -2.2
b01 9.2 30.1 226.5 b10 20.8 27.9 34.1
b02 7.2 9.0 24.6 b11 35.1 - N/A
b03 21.4 31.7 48.5 b12 57.5 54.5 -5.5
b04 43.5 42.7 -1.9 b13 24.1 27.1 12.7
b05 45.1 44.1 -2.4 b14 156.4 148.8 -4.8
b06 9.0 17.4 93.8 b14_1 161.4 160.4 -0.6
b07 24.7 30.2 22.2 b15 115.9 115.8 -0.0
b08 34.2 39.2 14.7 b15_1 114.8 120.5 5.0
b09 28.5 33.5 17.4 b17 134.4 151.0 12.39Critical Period (ns) Critical Period (ns)
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Results 2/2
• Compare critical period of two runso Different placement algorithmso VPLACE vs default IDS
• IDS pushed to maximum efforto Enabled timing-driven optimizations
• VPLACE still not optimizedo Much way to go
Route congestion Suboptimal results
o But, already some improvement Up to 5% for some ITC benchmarks 2.2% better for HurriCANe
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CRF Results
• Design by Astrium Crisao Contact made during latest SEFUW (Nov 2012)o Provided only synthesized netlist
Flow does not necessarily need RTL anywayo Targeting AT40KEL040 family
• Desired frequency of 10 MHzo Crisa’s implementation had reached 4 MHzo Our flow reached 9.6 MHz (2.4x speedup)!
Just by using our default IDS flow VPLACE does not support inout ports
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Conclusions
• Fully automated Atmel FPGA flowo More user friendly
Only few lines of configuration needed for each projecto Unattended runso Fast constraints explorationo Fine tuning of IDS options
Better results even than industrial attempts
• VPLACE algorithmo Alternative to default IDS placemento Still not optimized for Atmel
Not timing-driven Not tuned for Atmel architecture
o But, some promising results already
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Future Work
• Wait for newer version of VPLACE
• Try additional designso SpaceWireo Other you suggest?
• Further exploration of IDS configuration options
