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Error Detecting Adder

Yugandhar AsmathSaikiran Vodela

Pavan PolumPuneet Shrivastava

Advisor: Dr. David W Parent8th May 2006

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Agenda• Abstract• Introduction

– Why– Simple Theory– Back Ground information (Literature Review)

• Summary of Results• Project (Experimental) Details• Results• Cost Analysis• Conclusions

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Abstract

• We designed an error detecting carry free adder based on the architecture proposed by Whitney J. Townsend, Jacob A. Abraham & Parag K. Lala. in ‘On-Line Error Detecting Constant Delay Adder’.

• The data width was taken as four bits and the circuit was designed to operate at 200 MHz and had dimensions of 200.7x324.1 m2 with a power consumption of 44.1 mW.

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Introduction

• Why the need for error tolerance? • What possibly could cause errors?• How can errors be detected? – Different error

detecting codes– Hamming code– Gray code– m-out-of-n code

• We have chosen to use the 1-of-3 code for error detection!

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1-of-3 code in error detecting adder

• We use constant delay arithmetic with decimal number representation.

• As suggested in [1] and [2], we encode the binary inputs to the adder as– 0 is coded as 010– 1 in any of the n-1 bits is coded as 001– 1` (-1 in signed bit representation) in the MSB as 100

• The figure illustrates a two operand addition/error detection operation.

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Project Summary

• Inputs – Two 4-bit words as addend and augend.– A reset pin.– Clock

• Outputs– A 4-bit sum.– One Carry bit.– Error indication pin.

• Specs– Clock Frequency – 200MHz– Worst Propagation delay – 3.3ns.– Cell height 30 microns– Power consumption – 44.1 mW.– Area – 200 x 324 microns

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Project Details

• The 1-of-3 code is split into two 1-of-2 codes to simplify logic realization.

• The encoder consists of a simple inverter.

• Addition is carried out in two stages– The output of the 1st stage is called intermediate sum and carry.

– The intermediate sum and carry are then summed up to get the final sum.

• The final outputs in 1-of-3 code are then checked for errors using the checker circuit.

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Schematic

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Internal gate logics

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Verilog output

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Longest Path CalculationsCELL BIT# WN Load WP Load Cg or Cin of

loadCg+Cint phl WN WP

INV 12 1.50E-04 1.50E-04 2.0000E-14 2.5000E-14 1.00E-10 2.84E-04 5.12E-04

NOR3 11 2.84E-04 5.12E-04 1.3355E-14 1.8355E-14 3.70E-10 1.76E-04 9.20E-04

INV 10 1.76E-04 9.20E-04 1.8394E-14 2.3394E-14 1.00E-10 2.67E-04 4.82E-04

NOR2 9 2.67E-04 4.82E-04 2.5139E-14 3.0139E-14 2.20E-10 2.63E-04 9.35E-04

INV 8 2.63E-04 9.35E-04 4.0228E-14 4.5228E-14 3.00E-10 1.18E-04 2.07E-04

AOI333 7 1.18E-04 2.07E-04 5.4404E-15 1.0440E-14 7.00E-10 2.05E-04 3.40E-04

INV 6 2.05E-04 3.40E-04 1.8309E-14 2.3309E-14 1.50E-10 1.52E-04 2.73E-04

INV 5 1.52E-04 2.73E-04 7.1280E-15 1.2128E-14 1.03E-10 1.44E-04 2.59E-04

AOI22 4 1.44E-04 2.59E-04 1.3515E-14 1.8515E-14 3.00E-10 2.41E-04 4.23E-04

INV 3 2.41E-04 4.23E-04 1.1137E-14 1.6137E-14 1.00E-10 1.92E-04 3.46E-04

AOI22 2 1.92E-04 3.46E-04 1.8038E-14 2.3038E-14 3.30E-10 2.28E-04 3.99E-04

INV 1 2.28E-04 3.99E-04 2.1039E-14 2.6039E-14 1.50E-10 1.68E-04 3.02E-04

Total = 2.92 ns.

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Floor Planning

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Layout

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Verification

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Simulations

Propagation delay for post-extraction - 3.36nsPropagation delay for pre-extraction - 3.22ns

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Cost Analysis

• Time spent on each phase of the project– Designing the logic - 2 week– Verifying logic – 2 week– Verifying timing – 1 week– Layout – 2 weeks.– Post extraction verification – 2 days.

• Total labour involved –200 hrs

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Summary

• Designed an error detecting carry free constant delay adder that works at 200MHz.

• Extensively used the concepts learned as a part of EE166.

• Used IC5.0 by Cadence systems to verify gate level logic and then lay out the logic in CMOS technology (AMI06 Process)

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Lessons learnt

• Start early, that’s the key to avoid last minute pressures.

• Take full advantage of Dr.Parent’s expertise.

• Work as a team, and plan well before you start.

• Break the projects into smaller modules and proceed step by step. Don’t be ambitious.

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References and Bibliography1. On-Line Error Detecting Constant Delay Adder - Whitney J. Townsend, Jacob A.

Abraham & Parag K. Lala.2. On-Line Error Detection in a Carry-Free AdderWhitney J. Townsend and Mitchell A.

Thornton Parag K. Lala.3. Evolution of fault-tolerant and noise-robust digital designs - M. Hartmann and P.C.

Haddow.4. On the Design of Combinational Totally Self-checking 1-out-of-3 Code Checkers

JIEN-CHUNG LO AND SUCHAI THANAWASTIEN.5. A MOS Implementation of Totally Self-checking Checker for the 1-out-of-3 Code -

D. L. TAO, PARAG K. LALA AND CARLOS R. P. HARTMAN

Acknowledgements• We thank Prof. Parent for his support and guidance which helped us

in successfully completing the project.• We would thank the Cadence Design Systems to have generously let

us use their tools in our Cadence lab.• We would also like to thank all our counterparts in this class who

helped us in a way or the other.

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Supplementary Slides

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Supplementary Slides

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Supplementary Slides

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Supplementary Slides

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Supplementary Slides