1 Digital Logic

8/8/2019 1 Digital Logic

1/46

Lecture #1

Analog system Continuous Digital system Discrete

Advantages of digital system

Noise margin Error detection and correction Easily programmable High processing speed Representation of numeric data with high precision Information storage and retrieval

Binary system digital system with two steps HIGH and LOW

Digital system types

Combinational circuits

Sequential circuits -- clocked


2/46

Lecture #2

General Radix Number System

1 1 0 1 2 1...... ......n n m mr K k k k k k k k k

11 1 0.....n nn nr K k r k r k r k 1 2 1

1 2 1.....m m

m mk r k r k r k r

r is the base or radix of the number system r = 10 Decimal system r = 2 Binary system r = 8 -- Octal system r = 16 -- Hexadecimal system

A number system of radixr has r numerals in the range 0 tor 1

k n is the most significant digit in (K )r

k m is the least significant digit in (K )r

Also called positional number system


3/46

Lecture #3

Conversion from decimal to other radix number system

Radix Divide and Multiply Method:

Integer part repeated divisions by r yield LSD to MSD

Fractional part repeated multiplications by r yield MSD to LSD

Other number system conversion methods

Series substitution method

General conversion method via intermediate conversion to and from decimal system Conversion between base A and base B when B = A x and x is a positive integer:

To convert a given number (K ) A to its equivalent number in baseB, group the digits of (K ) A in groups of x digits in both directions from the radix point and then replace eachgroup with the equivalent digit in baseB.

For the reverse, replace each base B digit in with the equivalent x digits in base A.


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Lecture #4

Representation of signed numbers

Traditional number system: + and Radix number system (including decimal system):

Signed-magnitude representation Excess representation Complement number system

-- Radix complement representation-- Diminished radix complement representation

Signed-magnitude representation

Sign represented by leftmost digit:0 represents positive; (r 1) represents negative.

Range of representation :

Let, magnitude part of the signed number (unsigned number) is

1 1 0 1 2 1...... ......n n m mr K k k k k k k k k

Range of magnitude of integer part is0 r (n+1) 1

Range of magnitude of fractional part is0 1 r m

Considering only the fractional part, when all the digits are (r 1), the value is1 2 1( 1) ( 1) ..... ( 1) ( 1)m mr r r r r r r r

1 2 1 0( 1) ( 1) ..... ( 1) ( 1)m m mr r r r r r r r r

1 1m m mr r r

Combining we have the overall range of the magnitude0 r (n+1) r m

Therefore, range of signed number is [r (n+1) r m] 0 +[r (n+1) r m]

Note : Zero can be represented in both forms (r 1)0000..0000 and 00000..00000, but tworepresentations of zero not required conventionally the former combination is discarded. So, while total number of possible combinations is 2r (n+1) , only 2r (n+1) 1 combinations are used.

Disadvantage : Requires examining the sign-digit using complicated circuit before execution of any arithmetic operation.


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Excess representation Suppose the range of the numbers to be represented is to + . We add to the number. This is Excess- representation. The value that is added is calledbias. The range of the biased numbers, therefore, is 0 to +2 . Therefore, the biased number is always non-negative and hence, we may represent it only by

its magnitude. Number of digits necessary for the representation of the biased number has to be properly

decided, i.e.,n and m has to be chosen such that

12 1 log 2 1 1n r r n

2 2 1 log 1 2 2m r r m

However, higher m may be required if more precision is desired.

Radix complement representation

Generally used for integer.

1 1 0......n nr K k k k k By convention, for non-negative(K )r the MSD is less thanr /2 , i.e., k n < r /2 (assuming r even)

For (n+1)-digit number as above, corresponding radix complement is

1n r r K r K

Radix complement of the complemented number is

1 1 1n n n r r r r K r r K K

Thus, we see that the negative of a negative number gives the positive number as expected.

When all the digits arezero, i.e., (K )r = 0, the radix complement isr n+1 which will require (n+2 )

digits with MSD equal toone and all other digitszero. But, since the number representationsystem here allows only (n+1 ) digits, the overflow digit may be discarded we are left with(n+1 ) zeroes only negative (radix complement) of 0 is 0 as expected.

For non-zero positive number, it can be shown that the MSD is greater than or equal tor /2.

< 2 2r r MSD for non-negative number (by convention) MSD for negative number


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2s complement

Radix complement representation in binary system.

For (n+1) bits, MSB =0 for non-negative numbers (by convention).Range of positive numbers: min. +1 (0000..00001) to max.2n 1 (01111..1111)

Corresponding negative numbers: max. 1 to min. (2n 1).

It can be shown that in 2s complement the representations of the numbers are1111.1111 (max.)to 1000.0001 (min.).

So, for negative numbers MSB =1 as desired.

However, the combination10000000 is not used in the above.12 ( ) 2 2 2n n n n ordinarily 2's complement :1000.....0000

The number does not have any complement in 2s complement system.

However, we do not discard this combination rather take it as the representation for 2n (since,MSB =1 indicates negative number)

Overall range of representation :

2n (1000 . 0000 ) 1 ( 1111 .. 1111 ) 0 ( 0000 .. 0000 )

+1 ( 0000 . 0001 ) 2n 1 (01111..1111)

How to find the value of a given number in 2's complement system :

If the MSB is0, then the number is non-negative and the magnitude is given by the decimalequivalent of the bit-string.

If the MSB is1, then the number is negative. To find the magnitude we first require to find thecorresponding positive number by taking 2's complement of the given negative number. Themagnitude of the corresponding positive number (determined by the above rule for non-negative number) gives the magnitude of the given negative number.


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Lecture #5

2s complement arithmetic

Case 1 : z = x + y , x and y are non-negative and so z also is non-negative.

Simple binary addition will give the result but only if z 2n 1 that is MSB =0

Both x, y 2n 1 z 2n+1 1 no overflow but result incorrect if z > 2n 1

On the number wheel, start from x and move y steps clockwise but crossing of the dotted line atQ not allowed.

Case 2 : z = x y, x and y are non-negative.

Equivalently, addition of x with 2s complement of y: z x y

Therefore, simple binary addition of x with2s complement of y will give the result.

When x y, z is non-negative and within the permitted range. So result is always correct.

On the number wheel, start from complement of y and move x steps clockwise crossing the dottedline atP . Overflow is generated whenever the dotted line is crossed atP .

1 1(2 ) 2 ( )n n z x y x y x y

This shows overflow and discarding the overflow we will be left with the binary number ( x y) .

When x < y , z is negative and within the permitted range. So result is always correct.

On the number wheel, start from complement of y and move x steps clockwise.

The result is expected to be the negative of ( y x )1 1(2 ) 2 ( )n n z x y x y y x

This shows the result to be the 2s complement of ( y x ) as expected.

000

100

010110

001111

011101

P

Q


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Case 3 : z = x y, x and y are non-negative and so z is negative.

Simple binary addition will give the result but only if z 2n that is MSB =1Desired result is the 2s complement of ( x + y ).

z x y x y

That is on the number wheel, start from 2s complement of x and move y steps anti-clockwise butcrossing of the dotted line atQ not allowed.

Anti-clockwise move generates overflow.1 1 1 1(2 ) (2 ) 2 2 ( )n n n n z x y x y x y x y

So we see an overflow. Discarding the overflow will give the desired2s complement of ( x + y ).

Summary of addition/subtraction method in 2s complement system : For all numbers preceded by minus sign, take their 2s complement. Perform simple binary addition. Discard any overflow. Care should be taken so that the result is always within the number range.

000

100

010110

001111

011101

P

Q


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Diminished radix complement

Radix complement can be rewritten as

1 1( 1) ( ) 1n n r r r K r K r K

The first number in RHS is the number with all digits (r 1).

(r n+1 1) (K )r is the diminished radix complement of (K )r radix complement diminished byone.

Check that it is very easy to get diminished radix complement as the subtraction from (r n+1 1) willnot involve any borrow.

To obtain diminished radix complement, replace eachk i by (r 1) k i

To obtain radix complement just add 1 to the diminished radix complement.

In binary case, it is called 1s complement.

To get 1s complement just do bit flipping. In decimal case, it is called 9s complement.

1s complement representation

1s complement of 0000..0000 is 11111111 which also should bezero.

Hence, 11111111 is discarded.

Range of representation :

(2 n 1) ( 1000 . 0000 ) 1 ( 1111 .. 1110 ) 0 ( 0000 .. 0000 )+1 ( 0000 . 0001 ) 2n 1 (01111..1111)

Arithmetic :

Case 1, same as in radix complement system.

Case 2, for x y, 1(2 1)n z x y x y x y

So we see that we will get ( x y ) if we add 1 and discard the overflow.

Addingone is related with the discarding of the combination11111111.

For x < y , 1 1(2 1) (2 1) ( )n n z x y x y x y y x

So simple binary addition will give desired 1s complement of ( y x ).

Case 3, 1 1 1 1(2 1 ) (2 1 ) 2 1 (2 1) ( )n n n n z x y x y x y

So we see that we will get complement of ( x + y ) if we add 1 and discard the overflow.

1s complement arithmetic is same as 2s complement arithmetic except that whenever there isoverflow we have to add 1.


10/46

Lecture #6

Numeric codes

Used to represent numbers for storing and/or processing.

Fixed point number

Either, only integer in sign-magnitude form with binary point implied on the right.

Or, only fraction in sign-magnitude form with binary point implied between sign-bit andMSB of magnitude.

Floating point number

1 1 0 1 2 1...... ......n n m mr K k k k k k k k k

1

1 1 0 1 1. .... .....n E

n n m mk k k k k k k r M r

M is pure fraction calledmantissa or significand represented in fixed point fraction.

E is pure integer (pos. or neg.) called exponent or characteristic represented in excess- 2scomplement form (excess- representation using 2s complement arithmetic for adding the bias).

Binary coded decimal (BCD) number

Number represented in decimal format using 4 bits for every decimal digit.

Weighted codes

Used to represent decimal digits using 4 bits.o 8-4-2-1 code BCD itself.o 2-4-2-1 code self complementing code.

Excess-3 code

Used to represent decimal digits using 4 bits. Also self complementing.

ASCII code

Represent 128 characters as 0 to 127 using 7 bits and an 8th bit at left as parity-check bit(1 for odd and0 for even parity)

Gray code

Used to represent any number. Only one bit changes from one number to next. Oneapplication is to determine the angular position of a rotating wheel.

Gray code construction: 1. by reflection

2. g i = 0 if k i = k i+1, else 1; MSBgn = k n.


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Lecture #7

Boolean algebra developed by George Boole in 1849

A closed algebraic system containing a setB

of two or more elements and two binary operators (.)and (+) such that the following postulates, called theHuntington's Postulatesare satisfied

1. , .a b a b a b , B Band

2. B contains two elements0 and 1 (also calleduniversal bounds) which satisfy:

.0 0, 0 , .1 1 1a a a a a a a , and

Therefore, 0 is called the identity element for (+) operation and 1 is called the identity element for (.) operation.

3. (.) and (+) are commutative, associative and distributive:

, ,a b c B

Commutative: . .a b b a a b b a and

Associative: ( ) ( ) .( . ) ( . ).a b c a b c a b c a b c and

Distributive: ( . ) ( ).( ) .( ) ( . ) ( . )a b c a b a c a b c a b a c and

4. There exists a unary operation, denoted byprime or overline,such that

,a a a a B Bcomplement of is or

and the following complementation laws hold:

. 0 1a a a a and

( , , , ). + forms the Boolean algebra.

Elements of B are Boolean elements 1 2, ,....., n x x x B ; a Boolean variable assumes avalue equal to any of the Boolean elements. For a finite Boolean algebra system thenumber of Boolean elements is fixed whereas the number of Boolean variables is unlimited.

Boolean function: 1 2( , ,......, ) :n

n f A A A f B B where Ai are Boolean variables.


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Theorems on Boolean algebra

Duality: If some relation (identity, equation, etc.) holds then its dual relation obtained by replacing (.)with (+)and vice versa will also hold.

Example: ( ). ( . ) ( . ) ( . ) ( ).( )a b c a c b c a b c a c b c

Idempotency: .a a a a a a and

Involution: ( )a a

Absorption: .( ) ( . )a a b a a a b a and

De Morgans Laws: ( ) . ( . )a b a b a b a b and

Theorems on canonical forms Every Boolean function of n variables can be uniquely expressed as a join (sum) of terms of

the form

1ni i bq m B

where q i is a Boolean variable or its complement, the wedge represents (.) operation the product termmb is calledminterm

Thus, f ( A1 ,A2 ,..,A n) = bm B the vee represents (+) operation sum-of-product (SOP) canonical form or calleddisjunctive canonical form

Dual of the above gives product-of-sum (POS) canonical form or calledconjunctive canonical form each term calledmaxterm.

1ni i bq M B sum term

f ( A1 ,A2 ,..,A n) = b M B POS form

Switching function

Boolean function when only two Boolean variables0 and 1.

Basic operations OR, AND and NOT

Other operations NOR (NOT of OR), NAND (NOT of AND),

XOR (Exclusive OR -- modulo-2 binary addition),

XNOR (NOT of XOR)

Truth Table representation of switching function in tabular form for various conditions of theswitching variables.


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Deriving switching function from truth table

Example of a truth table:

A B C Y = f (A,B,C)

X 0 0 0 0 0

X 1 0 0 1 1

X 2 0 1 0 1

X 3 0 1 1 0

X 4 1 0 0 0

X 5 1 0 1 0

X 6 1 1 0 1

X 7 1 1 1 0

SOP form: 1 2 6 (1, 2,6)Y ABC ABC ABC m m m m

POS form:0 3 4 5 7

( )( )( )( )( )

. . . . (0,3, 4,5,7)

Y A B C A B C A B C A B C A B C

M M M M M M

Deriving Canonical forms by Shannons expansion theorems:

1 2 1 2 1 1 1 2 1 1( , ,......, ) . ( , ,..., ,1, ,..., ) . ( , ,..., ,0, , ..., )n i i i n i i i n f A A A A f A A A A A A f A A A A A

1 2 1 2 1 1 1 2 1 1( , , ......, ) ( , , ..., , 0, ,..., ) . ( , , ..., ,1, ,..., )n i i i n i i i n f A A A A f A A A A A A f A A A A A

Deriving canonical SOP form:

For all product terms not involving A1, expand each one of them, say f j as 1 1 j j A f A f

For all product terms involving A1, keep them intact. Apply the above two steps to the resultant expression for A2 ,A3 , and so on till An.

Deriving canonical POS form: The dual of the above.


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Lecture #8

Logic gates

Basic gates: OR, AND and NOT

Universal gates: NAND and NOR because any switching function can be implemented using onlyNAND or only NOR gates.

Any output in SOP form can be implemented by replacing AND, OR and NOT gates by NANDgates.

Any output in POS form can be implemented by replacing AND, OR and NOT gates by NORgates.

Circuit implementation by NOR gates:Following the duality method

Build the circuit for using NAND-gates. Complement all inputs and output and replace NAND gates by NOR gates.

Note: In general, NAND gates and NOR gates are used for implementing SOP and POS,

respectively.

However, if the number of inputs to the gates are restricted, say 2-input NAND/NOR gatesthen we have to check which implementation (SOP or POS) will require minimum number of gates. For example,

( )( )( )Y ABC BC B C A C B C

The above switching function will require 8 2-input NOR gates for implementing the SOPexpression while the POS expression will require 9 2-input NOR gates.


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Lecture #9

Karnaugh-map method for simplification of switching function

Minimal SOP form from K-map Form a K-map with 2n squares, each square representing a minterm. For the minterms included in the given function, enter 1 in the corresponding square. Enter

0 for the remaining squares. Each square on a K-map has logicallyn adjacent squares, with each pair of adjacent

squares differing in exactly one variable. Combine minterms (squares with entry1) on a K-map in groups of squares in power of 2

two squares (pair), four squares (quads), eight squares (octets) and so on. Grouping inpair eliminates one variable, quad eliminates two variables, octets eliminate three variablesand so on, that is grouping 2n squares eliminaten variables.

Group as many squares as possible this will reduce the number of literals in the resultingproduct term.

Make as few groups as possible covering all the minterms this will reduce the number of product terms in the SOP expression.

Each minterm may be used as many times as it is needed. However a minterm may nothave any adjacency and may remain uncovered no reduction is possible for that minterm.

Note: (1) The K-map may be wrapped around during grouping. (2) Finally check for anyredundancy.

A K map with all1s (or all0s) gives Y = 1 (or 0).

Minimal POS form from K-map:

Get the SOP form for Y by applying the above procedure to the squares with entry0. Then get thecorrespondingY in POS form by complementing all the variables and replacing (+) by (.) and vice-versa (De Morgans law).

Dont care condition:

Dont care conditions are those not specified in the truth table.

They can be assumed to be either Y = 1 or Y = 0, as appropriate and represented as Y = X

As such, the corresponding minterms or maxterms are included both in canonical SOP as well asin canonical POS expressions, respectively, but separately.

Also, in K-map the terms are treated as1 or 0, as necessary for better grouping.


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Lecture #10

Quine-McCluskey method for simplification of switching functions

We explain it using one example.

( , , , ) (2,4,6,8,9,10,12,13,15) f A B C D m

Step 1: Form List 1 by grouping minterms according to the number of 1s in the binaryrepresentation of the minterm number.

Step 2: Combine logically adjacent terms through exhaustive search in List 1. Put thecombinations in List 2.

Step 3: Combine the terms in List 2 to generate List 3 and so on. Take care that while combiningtwo terms in List 2, 3, and so on the position of the dash in the two terms must be same.

Step 4: Form prime implicant chart. Separate the prime implicants having different number of literals.

Step 5: Choose as few prime implicants as possible to cover all the minterms:

-- Find allessential PIs.

-- Remove the essential PIs and the minterm columns that they cover.

-- A row thatis covered by another row may be eliminated.

-- A column thatcovers another column may be eliminated.


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List 1 List 2 List 3

Minterms ABCD Minterms ABCD Minterms ABCD

2 0010 2,6 0-10 PI-2 8,9,12,13 1-0- PI-1

4 0100 2,10 -010 PI-3

8 1000 4,6 01-0 PI-4

4,12 -100 PI-5

6 0110 8,9 100-

9 1001 8,10 10-0 PI-6

10 1010 8,12 1-00

12 11009,13 1-01

13 1101 12,13 110-

15 1111 13,15 11-1 PI-7

2 4 6 8 9 10 12 13 15

PI-1 x x x x

PI-2 x x

PI-3 x x

PI-4 x x

PI-5 x x

PI-6 x x

PI-7 x x

Essential PIs: PI-1 and PI-7

PI rows to be removed due to covering by other rows: PI-5 and PI-6

Columns to be removed for covering other column: column for minterm 2

Again PI row to removed: PI-2


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Lecture #11

Q-M method in some special cases

Cyclic PI chart :

That contains no essential PI and that cannot be reduced by thecovering rules.

Select one PI (that includes maximum number of minterms) arbitrarily. If the resulting chart is nownot cyclic apply the covering rules. Else, make a second arbitrary choice and so on.

Incompletely specified function (function with dont cares):

Include the dont cares in forming the lists. But exclude the dont cares in the PI chart.

Systems with multiple outputs:

1. To each minterm affix a flag to identify the function in which it appears.

2. Two terms can be combined only if they posses at least one common flag and the termthat results from the combination should bear the common flag(s).

3. Each term in the minimizing table can be checked off only if all the flags that the termpossesses appear in the resulting combined term.

4. Make separate column listings for different functions in the PI chart.

Example:

( , , , ) (0, 2, 7,10) (12,15)a f A B C D m d

( , , , ) (2, 4,5) (6, 7,8,10)b f A B C D m d

( , , , ) (2,7,8) (0,5,13)c f A B C D m d

We will get 2 5 13a f PI PI PI

1 5b f PI PI

2 3 13c f PI PI PI

In implementing the functions, we first generate the PIs in the first stage and then sum them asrequired to generate the functions in the second stage. The advantage here is that we canminimize the circuit size by making use of the same PI-2, PI-5 and PI-13 in more than onefunctions.


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MINIMIZING TABLE

List 1 List 2 List 3

Minterms ABCD Flags Minterms ABCD Flags

0 0000 ac 0,2

0,8

00-0

-000

ac

c

PI2

PI3

4,5,6,7 01.. b PI1

2

4

8

0010

0100

1000

abc

b

bc

PI10

PI11

2,6

2,10

4,5

4,6

8,10

0-10

-010

010-

01-0

10-0

b

ab

b

b

b

PI4

PI5

PI65

6

10

12

0101

0110

1010

1100

bc

b

ab

a PI12

5,7

5,13

6,7

01-1

-101

011-

bc

c

b

PI7

PI8

7

13

0111

1101

abc

c

PI13 7,15 -111 a PI9

15 1111 a


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PI CHART

f a f b f c

0 2 7 10 2 4 5 2 7 8

PI-1 b x x

PI-2 ac x x x

PI-3 c x

PI-4 b x

PI-5 ab x x x

PI-6 bPI-7 bc x x

PI-8 c

PI-9 a x

PI-10 abc x x x

PI-11 bc x

PI-12 a

PI-13 abc x x

Essential PIs: PI-1, PI-2, PI-5

PIs due to dont cares only and hence removed: PI-6, PI-8, PI-12

PI rows to be removed due to covering by other rows: PI-9, PI-7

Now we may choose either PI-3 or PI-11 but PI-3 is to be chosen as it has fewer literals.


21/46

Lecture #12

Transistor as switch

Modes of BJT operation: cut-off, active, saturation

Switching requires abrupt transition from cut-off (OFF) to saturation (ON) spending very little timein active mode in between.

Analytical expressions for BJT characteristics

Considering base and collector currents entering the transistor while the emitter current is leavingthe transistor, we have for normal mode of operation

/ 1 pn T V V C N E CO I I I e eqn. (1)

And for inverse mode of operation we have

/ 1 pn T V V E I C EO I I I e ..eqn. (2)

pnV and pnV are the p-n voltages at the base-emitter and base-collector junctions. For thenpn transistor switch circuit above

and BC pn BE pnV V V V

B

EC

+

I B

I C

I E

R L

V CC


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The above two equations are calledEbers-Moll equationsand the corresponding model is theEbers-Moll model . The model for npn transistor is shown above.

We can consider both the equations simultaneously if we consider that the response of thetransistor to a current injected at the emitter junction is independent of that at collector junction andvice-versa. Solving we get

/ / 1 11 1 pn T pn T V V V V EO I CO

E N I N I

I I I e e

..eqn. (3)

/ / 1 11 1 pn T pn T V V V V N EO CO

C N I N I

I I I e e

eqn. (4)

The base current can be calculated as B E C I I I eqn. (5)

The junction voltages in terms of the currents:

ln 1 E I C pn T EO

I I V V

I

..eqn. (6)

ln 1 C N E pn T CO

I I V V

I

....eqn. (7)

Relation between N and I 1, 1 N EO I CO N I I I eqn. (8)

Considering the switch circuit again,

CC C L CE CE CC C LV I R V V V I R .eqn. (9) load-line equation

For the npn transistor (as above circuit):

CE CB BE BE BC pn pn CC C LV V V V V V V V I R eqn. (9-a)

For pnp transistor we have:

CE CB BE CB EB pn pn CC C LV V V V V V V V I R eqn. (9-b)

where V cc and I C are negative.

Therefore, general expression,

pn CC pn C LV V V I R ..eqn. (10)


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With B-E junction forward biased ( pnV above the cut-in voltage which is typically 0.65 Volt ), if the

collector current is small enough to satisfy 0CC pn C L pnV V I R V , then the B-Ccollector junction is reverse biased.

This is active region of transistor operation.

In normal mode and in active region, the base-collector junction is reverse biased. Then we mayapproximate eqn. (1) as

C N E CO I I I ..eqn. (11)

And using the relation E B C I I I we have

1 1 N CO

C B N N

I I I

..eqn. (12)

If we ignore the second term for very small I CO we get the dc current gain as

1C N

FE B N

I h

I

eqn. (13)

This is approximately same as the that you have studied in analog electronics.

[ Similarly, for inverse operation,

1 I

FC I

h

eqn. (14) ]

Therefore, (1 )C B CO B I I I I ..eqn. (15)

The CE output characteristic (I c vs V CE) shows that the curve for a given base current is almosthorizontal, that is collector current is constant, in the active region in accordance to eqn. (15)

Now, for 1 N is very large for very small base current we have very large collector current.Therefore,

E C B E C I I I I I eqn. (16)

Again, eqn. (3) can be reduced as

/ 0, , 1 pn T V V pn pn T I E EOV V V I I e eqn. (17)


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Transistor switch in cut-off

In active region, if the B-E forward bias is decreased magnitude of base current decreases magnitude of collector current decreases magnitude of V CE increases

Collector current decreases emitter current decreases

Now, say we make 0 (1 ) B C CO I I I which is not insignificant.

But, we want no collector current for ideal SWITCHING OFF. Hence just making base currentzero will not serve the purpose.

So, to have cut-off, we approach the condition when the base-emitter junction is not sufficientlylarge to forward bias the junction resulting in emitter (and hence collector) current to be nominallyzero. That is, to achieve cut-off we have to make pnV V .

/ / 1 11 1 pn T V V EO I CO

pn T E N I N I

I I V V I e

eqn. (18)

Applying the relation in eqn. (8) we get

/ / / 11 1 pn T pn T pn T V V V V V V EO EO

E N EO N I N I

I I I e e I e

.eqn. (19)

Thus, the emitter current is like the diode current expression and there will be no current if thebase-emitter junction does not exceed the cut-in voltage.

Under this condition, we have B C CO I I I base and collector current approx. zero. eqn.(15) does not hold any further.

Also, assuming collector current zero we have CE CC V V


25/46

Lecture #13

Transistor switch in saturation

In active region, if the B-E forward bias is increased magnitude of base current increases

magnitude of collector current increases magnitude of V CE decreases From eqn. (10), with increasing collector current magnitude the reverse biasing of C-B junctiondecreases a condition is reached when C-B junction is just forward biased saturation regionstarts This is the transition point or edge between active and saturation region.

Typically, this condition should be reached when 0.65 pnV V V and so 0CE V

However, due to wider C-B junction, the junction starts conducting much before at about 0.4 Volt.

To reach this condition, typically 0.75 0.35 pn CE V V V

A slight decrease in B-E forward bias will take the transistor out of saturation soft saturation

With further increase in B-E forward bias (or base current), forward biased current across C-B junction starts flowing in opposition to the collector current.

Eqn. (15) is no more valid for the same base-current, collector current in saturation isless than that in active.

For the same decrease in the magnitude of V CE more increase in base current required(than that in active)

For constant base current ( pnV kept constant) and with decrease in the magnitude of V CE (may be possible by increasing the load heavily), while collector current remains constantin active region, it decreases in saturation finally becoming zero (as pnV increases).

Thus, from soft saturation point pnV is increased by large amount base-current magnitudeincreases by large amount collector-current increases to some extent magnitude of V CE decreases approaching zero transistor is driven into hard saturation.

Some typical approximate values:

Cut-off : 0.65 , , 0 pn CE CC C E BV V V V I I I

Active: 0.65 0.75 pnV V V and we generally consider fixed 0.7 pnV V

Saturation: 0.75 ,0 0.35 , 0.4 pn CE pnV V V V V V


26/46

Ebers-Moll equations in saturation

Define: C FE B

I h I eqn. (20)

This parameter is equal to 1 in active while in saturation it ranges from 0 to 1 a measure for theextent of saturation lower value for harder saturation.

CE pn pnV V V for npn while CE pn pnV V V for pnp

Using eqns. (6), (7), (13) and (14) and by some manipulation we get for npn

,

(1 )

ln1

FC FE

FC FC CE sat T

hhh h

V V

eqn. (21)

We now make a plot of ,CE sat V vs to see the behavior of npn transistor in saturation.

In normal mode 1st quadrant plot:

Increase by keeping I B fixed and increasing I C (by reducing load) asymptote betweenactive and saturation occurs at = 1.

Decrease I C (by increasing load) with fixed I B or by increasing I B with I C fixed. At = 0 (we canonly approach close to this) we have minimum voltage across transistor:

, 1lnCE sat T I

V V

eqn. (22)

In inverse mode 3rd quadrant:

1 E FC B C B FC I h I I I h .eqn. (23)

The asymptote between active and saturation is at 1 FC FE

h

h

Min. voltage across transistor is obtained at 10 E C BFE

I I I h and we get

,

1lnCE sat T

N

V V

..eqn. (24)


27/46

Switch circuit modified with the base=drive current source returned to collector instead of emitter 2 nd quadrant as well as 1st and 3rd :

In this circuit collector current in a reverse direction (when saturated very hard) possible in normalmode.

Collector current is zero for 1lnCC T

I B

L

V V I

R

Transistor output voltageV CE,sat is zero for

1

FE FC h h and 1CC FE B

L FC

V h I

R h

which is practically extremely large value.


28/46

Lecture #14

TTL Logic

The above is a TTL inverter circuit.

Our aim is to plot output-input characteristic (V o vs V i): (1) PlotV o vs V B4, and then(2) plotV B4 vs V i

Plot of V o vs V B4

(a) For 40 0.65 BV V

T4 is cut-off T3 is cut-off and T2 conducting

4 2 2 2o CC C B BE D CC BE DV V R I V V V V V (explain why I B2 may be neglected)

If both T2 and D are both just at cut-in, output voltage isV cc 1.3

If both T2 is in saturation and D conducting, output voltage isV cc 1.45

If both T2 is in active and D conducting, output voltage isV cc 1.4 we generallyconsider this situation.

V o

R e

R C2

T2

T3

V CC

DV i

R b

R C4

T1

T4

V B4


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(b) For 40.65 1.35 BV V

T4 goes to just cut-in butV B3 is still at zero potential T3 still in cut-off

Then T4 gradually starts conducting with 4 0.7 BE V and V B3 slowly rising to 0.65 T3

goes to just at cut-in.

T2 remains in conduction through out.

4 0 0 42

4 2 4

, 1C C B B e B B e

R V V RV V R V V R

At 4 1.35 BV , T3 will be just at cut-in while T4 conducting.

Then, current through T4, 4 4 0.65C E e

I I R

And once T3 starts conducting, 4 4 0.7C E e

I I R

Now, 4 4 2o CC C C BE DV V R I V V R C4 I C4 is the additional drop in output voltage[than that in case (a) above] during this transition.

(c) For 41.35 1.45 BV

T2 and T4 remain in conduction.

While we have 4 0.7 BE V through out,V B3 rises from 0.65 to 0.75 T3 starts conductingand then goes to saturation when 3 3 0.75 BE BV V

As in case (b), 0 44

C

B e

V R

V R with the resistance in the denominator different than above:

e R above is replaced by e e ie R R h where ieh is the B-E resistance of T3 and so also for

all transistors. ieh is same as the r i in the approximate transistor model below.

The slope 04 B

V V

will be more than that in case (b)


30/46

Lecture #15

Base Collector

Emitter

h ie =r i hfe I B = I B

I B

Since T3 conducting there is a second factor affecting change in the output voltage as

follows, making 04 B

V

V still higher:

4 4 34 3

o o FE L B E B

B B ie

V V h RV V V

V V h

Where RL is the effective load due to D and looking into emitter of T2 (when operatingwithout load, that is no fan-out).

Impedance of transistor with base resistanceRC4, looking from emitter side: 4ie C FE

h R

h

We consider diode impedance same as that offered by B-E junction: ieFE

hh

Overall, 0 4 44

( )2C e ie C

B e ie ie

V R R h RV R h h

1 T ie FE E

V h h I as T3 conducts emitter current increases h ie decreases

from infinite value to lower value depending on the amount of saturation when T3 goes

to saturation at V B4 = 1.45 or V B3 = 0.75 slope 04 B

V

V gradually increases (not

constant).


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If the gate is loaded (non-zero fan-out), effectiveRL decreases & and so larger hie slope

0

4 B

V V

will be smaller than that without load V CE (sat) at V B4 = 1.45 or V B3= 0.75 will be

higher than that without load Quite obvious because loaded gate will sink currentresulting more collector current in T3 giving larger which means higher V CE (sat).

Also, f or T3 we have large and hence h ie , slope at V B4 = 1.45 will be smaller.

Therefore, without load T3 should go deep into saturation to allow fan-out.

(d) For 41.45 1.5 BV

T3 remains in saturation withV B3 = 0.75, V B4 increases from 0.7 to 0.75 T4 enterssaturation V B2 = V CE4 (sat) + 0.75 < 1.3 which is not enough to forward bias both D and

B-E junction of T2 T2 cuts-off. I B4 increases I E4, I B3 increases of T3 decreases output voltage decreases more.

If the gate is not loaded, atV B4 = 1.5 when T2 turns off,

3

10 0 lnC o T

I

I V V

Plot of V B4 vs V i

(a)

For 1.5

iV

As seen before, 4 1 11.5 B E C V V V T1 operates in inverse mode (3rd quadrant of V CE vs plot earlier)

With 4 1.5 BV , 1 44 12.2

1 1 1CC BC B CC B B FC FC FC b b

V V V V I I h h h

R R

We shall always takeV BC1 = 0.7 as this is valid in active and at saturation, as we will see,the current through the B-C junction of T1 is so small that the drop across it can bereasonably taken as 0.7 and not 0.75

Now sayV B4 < 1.5, then I B4will be still higher which implies T4 and T3 will be in saturationT4 and T3 in saturation with 4 1.5 BV and I B4constant output logic0

With decreasing input voltage, magnitude of V CE1 (which otherwise is negative) decreasesat one point T1 enters saturation in inverse mode


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Now onwards some part of base current of T1 starts diverting towards the emitter I B4 and I E1 starts decreasing magnitude of (which otherwise is negative) startsdecreasing (T1 goes to harder saturation in inverse mode).

At one point of time emitter current in T1 becomes zero: 11

lnCE T N

V V

I B4

reduces by h FC I B1 This small reduction in I B4 will not be enough to take T4 and T3 outof saturation.

(b) For 1.5iV

1 1

1 10 0CE E

FE FC FE

V I h h h

This condition is very close to the

final condition in case (a) T4 and T3 still in saturation.

Further decrease in input voltage will reverse direction of emitter current in T1 and T1operates in the second quadrant. Also, I B4 decreases further.

(c) As the input voltage is reduced further, I E1 increases and so I B4 decreases further causingT4 out of saturation at one point.

Treating T4 as in active we can calculate its collector and hence base current at the vergeof coming out of saturation for T1 can be calculated accordingly.

Gradually T3 comes out of saturation and goes to cut-off.

Then T4 cuts off when 4 11

0 0 ln B CE T I

I V V

However, for all the conditions in this case (c) for T1 is very close to 0. Therefore, we

can approximate 11

lnCE T I

V V

through out this case (c)

As such, T4 comes out of saturation at 11.5 lni T I

V V

and thereafter we have V B4

decreasing with the input at the same rate maintaining a constant difference of 1

lnT I

V


33/46

Lecture #16

Specifications

Noise margins: ,oH iH iL oL

V V V V 1 0

Fan-out : Maximum number of gates that can be connected to the output withouttaking the output logic to indeterminate state.

TTL NAND and NOR gates

NAND gate: Using multi-emitter input transistor T1.

NOR gate: Using parallel single-emitter input transistors with their collectors tied up.

Active Pull-upConsider a basic TTL inverter as follows which is basically a simplified form of the TTL inverter circuit above.

The output transistor T3 has some stray capacitance across the output (from T3 collector to

ground), sayC o

For transition of output from logic0 to logic1, the output voltage has to rise from almost 0 Volt toV CC The output stray capacitance must be charged from the supply voltage viaRC ( pull-upresistor ) the time constantC o RC should be small for fast transition lower load resistanceRC desired.

But lower RC will make it difficult to take T3 to saturation during transition from logic1 to logic0.

V o

V i

R b

R C

T1

T3


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Therefore, active load offering dynamic resistance is recommended.

The T2-D combination in the TTL inverter circuit serves the purposelower load when conducting(output logic1) and higher load when cut-off (output logic0)

Intention is to operate the transistors T2 and T3 in opposite, when one is ON the other OFF These two transistors form the so calledtotem-polepair.

This switching of T2 and T is accomplished by T4 T4 is called phase splitter it provides thebases of T2 and T3 with voltages thatswingin opposite direction.

Diode D is necessary to keep T2 OFF when T3 and T4 are ON.


35/46

Lecture #17

ECL Logic: OR/NOR gate

V i

V R

NOR

OR

V o1

V 02T1

T2

T3

T4

R C1 R C2

R e

R E3R E4

-V EE

Typical values:

1 2

3 4

, ( 1) ,

290 , 300 , 1.18 k

1.5 k , 1.5 k, 5.2 V, 1.175 V

0.7 V, 0.8 V, 0.75 V

100

C C e

E E EE R

BE sat BE active

FE

R R R

R R V V

V V V V

h

Transfer characteristic for OR output :

When at least one of the inputs is at logic1, T2 is OFF.

4, 4 2 4

2 4 2 4,

1 EE BE active B C FE E

o B C BE active

V V I R h R

V I R V

For the given values we have the ORoutput as 0.758 Volt which is logic1


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When all the inputs are at logic0, T2 ONLY is conducting.

2,

2 2 4 4, 2 4,1

E R BE active

E EE E

e

FE o C E B BE active C E BE active

FE

V V V

V V I R

hV R I I V R I V

h

For the given values OR output can be calculated to be 1.583 Volt which is logic0

NOTE: V E and hence I E will remain constant as long as T2 conducts.

Transition region when T2 as well as at least one input transistor conducts.

Suppose all except one input (say input of T1) is held at logic0

Then

1 2

1 21 0 2 0

1

2

( )

exp , exp

1 exp

and1 exp

E E E

BE BE E E E E

T T

E E

R i

T

E E

i R

T

I I I const

V V I I I I V V

I I V V

V

I I V V

V

And if we assume that the two extremes of the transition region is defined as when 95% and 5% of the total constant emitter current flows in the transistors T1 and T2, we can calculate that for thegiven value of reference voltage the transition starts at input voltage1.25 Volt (T1 startsconducting) to 1.1 Volt (T2 starts going to cut-off)

Also the width of the transition region is calculated as 2 ln 20 150 mVi T V V

The mid-point of the transition region is atV i = V R = 1.175 Volt when equal currents flow inT1and T2.

Therefore, input voltage range: 1.25 V , 1.1V 0 Vi iV V 0 1for logic for logic


37/46

Transfer characteristic for NOR output :

When all the inputs are at logic0, T2 is conducting and ALL input transistors are OFF.

Then NOR output voltage will be 1 3 1 3,

0.76 Vo B C BE active

V I R V which is logic1

As long as all the input transistors are OFF, the output voltage will not be affected by any change inthe input voltage(s) and the output voltage will remain constant.

As per the discussion above, the transition region extends from input voltage 1.25 Volt (T1starts conducting current through RC1 and hence the voltage drop across it increasesresulting in decrease in NOR output voltage) to 1.1 Volt (T2 starts going to cut-off outputgoes to logic0)

When at least one of the inputs is at logic1 (say T1 input), T2 is OFF and T1 conducts.

Initially asV i increases from 1.1 Volt, T1 is in active region and so we have,

1 3 1o B c

i i e

V V RV V R

So the transfer characteristic curve descends with the above slope (unlike that for OR where outputlogic0 is constant)

NOTE: While with T2 conductingV E, I E and hence voltage drop across RC2 remain constant incase of LOW OR output, for LOW NOR output with T2 OFF and T1 conducting,V E and hence I E will increase with increasing input voltage. Therefore, when T1 is in active current throughRC1 andhence the voltage drop across it increases resulting in decreasing NOR output voltage.

With further increase in the input, at some point T1 goes to saturation.

Assuming thatV CE(sat) = 0.3 Volt at the edge of saturation (soft saturation), for the given circuit

parameters we have the total drop acrossRC1 and Re equal to (5.2 0.3) = 4.9 Volt.Now, current throughRC1 is the T1 collector current + T3 base current

And current throughRe is the T1 collector current + T1 base current

So we can approximate equal current through bothRC1 and Re


38/46

Therefore, voltage drop acrossRC1 is

1

1

1

1

1

1, ( 1)

4.9 0.97 V

0.97 V0.97 0.75 1.72 V

0.3 1.27 V

0.47 V

C

C e

C

o

E C

i E BE sat

R R R

V V

V V

V V V

With further increase in the input (above 0.47 Volt in the given case), T1 goes to har der saturation.

With increasing input voltage till 0 Volt,V E increases drop across Re increases (by 0.47 Volt in this case)

V CE(sat) decreases (at most by 0.3 Volt in this case)

That means, increase in the drop across Re is more than the decrease inV CE(sat) overall there is an increase in the total drop across T1 andRe

drop across RC1 must be decreasing

This implies that the output voltage now starts rising and the curveascends.

Physically we may understand the situation as this: For a large increase inV i (and hence V E), theincrease in T1 base current is quite large. But, because of the comparatively largeRe, current I E needs to increase by a small amount only. Hence, some part of the base current will now bediverted through the forward biased BC junction of T1. This will reduce the current throughRC1 andsubsequently drop across RC1 decreases.

For V i = 0 Volt,V E = 0.8 Volt and assumingV CE(sat) at this point equal to 0.1 Volt wehave

1

1

0.7 V0.7 0.75 1.45 V

C

o

V V

NOTE: When more than one input transistor conducts, drop acrossRC1 will be more. To keep theLOW NOR output more or less at par with the LOW OR outputRC1 is taken slightly less thanRC2


39/46

Lecture #18

MOSFET as switch

JFET

Source generally grounded, V DS is the voltage across drain-source, V GS across gate-source, I DS is the drain current through the channel.

For n-channel,V DS and I DS are positive whileV GS generally negative (gate junction reversebiased JFET operates indepletionmode).

For p-channel,V DS and I DS are negative whileV GS generally positive.

Pinch-off voltage is P PO GSV V V where V PO is the pinch-off voltage withV GS = 0.

The JFET will be cut-off if pinch-off occurs at 0 Volt the condition for cut-off isGS POV V for n-channel and GS POV V for p-channel.

Before pinch-off occurs, JFET acts as a linear resistor whose resistance value can becontrolled by the gate voltage.

After pinch-off, the drain current saturates.

With further increase inV DS a point is reached when the gate junction breaks down.Breakdown voltage is DS DSO GS BV BV V where V DSO is the break-down voltage withV GS = 0.

MOSFET

Channel induced in the substrate between drain and source by applying gate voltage(positive for NMOS, negative for PMOS).

Source generally grounded whileV DS is applied at the drain (positive for NMOS,negative for PMOS).

Potential (magnitude) at the drain is GS DSV V and is the minimum over all points inthe channel.

Pinch-off occurs when the drain-source voltage reduces the field at the drain to almostzero for a threshold voltageV th (positive for NMOS, negative for PMOS), this pinch-off occurs at


40/46

DS GS thV V V .eqn. (1)

Typically, magnitude of V th is in the range 2 to 4 Volt.

Cut-off occurs when GS thV V for NMOS and GS thV V for PMOS.

This type of MOSFET operation where the channel requires to be induced is calledenhancement mode.

MOSFET can also be made to operate in depletion mode if a channel is diffused apriori into the substrate between drain and source. Nevertheless, such MOSFET canalso operate in enhancement mode.

The conductance of the channel will also be affected by the bias applied to thesubstrate substrate acts as back gate. Change in the magnitude of thresholdvoltage due to this bias is given as

th SBV C V ..eqn. (2)

V SB is the source-substrate voltage that reverse biases the channel-substrate junction positive for NMOS, negative for PMOS no change in threshold voltage when thesubstrate is tied to the source.

Parameter C depends on doping of substrate and is typically in the range 0.5 to 2.0.

Expressions for current:In triode-mode (non-saturation):

22 ,0 DS GS th DS DS DS GS th I k V V V V V V V for NMOSeqn. (3-a)

22 ,0SD SG th SD SD SD SG th I k V V V V V V V for PMOS.eqn. (3-b)

In saturation mode:

2 ,0 DS GS th GS th DS I k V V V V V for NMOSeqn.(4-a)

2 ,0SD SG th SG th SD I k V V V V V for PMOSeqn. (4-b)

The constant k is given as

2W

k t L

.eqn. (5)


41/46

Where is mobility of carriers in the channel, is the dielectric constant of oxide insulation,t isthickness of oxide layer, W is channel width, L is channel length.

Note:

Drain current is never zero even with no induced channel (in cut-off) a small amount of current I DSS flows due to flow of charges through the semiconductor substrate.

GS th D DSSV V I I and GS th D DSSV V I I ..eqn. (6)

In digital circuitry enhancement type MOSFET is preferred as here we get cut-off at about zerogate voltage.

MOS switch

As in BJT switch, a large load required to drive transistor to saturation in MOSFETswitch load required still larger A second MOSFET is used as load which offers highresistance when ON.

V O

V DD

V GG


42/46

Therefore, two MOSFETs one load transistor other driving transistor. Load substrateeither connected to source or grounded. We take substrate connected to source so thatthe threshold voltage is fixed.

When driving transistor ON, output voltage will be approx. zero if the load resistance ishigh and large current flows load transistor must also be ON required drop acrossdriving transistor almost zero while drop across load resistance almost equal toV DD high load resistance but small driving transistor resistance load having large length butsmaller width, driving transistor having just the opposite.

When driving transistor OFF, current I DSS flows through it load transistor must be ON toallow this current as the I DSS of the load transistor will be smaller (because its resistance ismore; so keeping the load OFF will not help) so maximum output is

O GG thV V V ..eqn. (7)

And the drop across the load is required to be very small ( DD O

V V ).

Case 1: DD GG o DD thV V V V V The output voltage will be less than thesupply drain voltage and the drop across the load transistor is equal to the thresholdvoltage.

Case 2: GG DD th o DDV V V V V The output voltage will be equal to thesupply drain voltage (as desired) and the drop across the load transistor is zero.

Case 3: DD GG DS DD o GG o GS GS thV V V V V V V V V V The load willbe always in saturation.

Case 4: DD GG DS GS GS thV V V V V V The load will never be in saturation.

NOTE: With the substrate of the load transistor grounded, the output voltage will befurther reduced by the factor th oV C V

MOS inverter

The MOS switching circuit discussed earlier acts as an inverter. We now list some of the importantpoints with respect to an NMOS inverter. For PMOS inverter we can have the equivalent relationsby reversing the sign.

We take load transistor as TL and drive transistor as TD.

The load transistor should be conducting at all times. This requires

, , , ,GS L th L GG o th L o GG th LV V V V V V V V


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When , , ,i th D GS D th DV V V V the drive transistor is OFF and the output is

,o GG th LV V V . This corresponds to output logic1 for input logic0.

When ,i th DV V the drive transistor conducts and the output starts decreasing.

( ,o GG th LV V V and hence the load conducts)

The slope of this transition region depends on the ratio of parameter and is given as

( )( )

D D R

L L

W LW L

We see that if the drive transistor is wider but the load is longer in length then we will havesharp transition. This is also a required condition to have high load resistance but smalldriving transistor resistance.

When the drive transistor starts conducting, initially for low input voltage (but greater thanthe threshold voltage), the output is high. That means the drive transistor will be insaturation as long as

, , , ,, , , ,i th D o i th D o DS D i GS DV V V V V V V V V where

When the input voltage increases and output voltage decreases so that ,o i th DV V V ,the drive transistor goes to triode region of operation.

So here we see that with increasing input voltage the drive transistor first goes tosaturation from cut-off and then to triode region of operation.

When the input is sufficiently high, the output goes down to almost zero (check from thecharacteristic curve for MOSFET that with a constant load the load-line will be a straightline with negative slope as G-S voltage is increased we move up the load-line andeventually the D-S voltage decreases). This corresponds to output logic0 for input logic1.

Now we wish to check the condition of the load transistor. As before, we consider four cases:

1. , , , , , DD GG DS L GS L DS L GS L th LV V V V V V V

2. , , , , , DD GG DS L GS L DS L GS L th LV V V V V V V

3. , , , , DD GG th L DS L GS L th LV V V V V V


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4. , , , , DD GG th L DS L GS L th LV V V V V V

So we see that in the first three cases the load will be always in saturation irrespective of the inputand output voltages while in the fourth case the load will be always in triode region.

Now we consider a case where the gate of the load transistor is tied to the output, i.e., G-S voltagefor the load is zero. Such a case is possible only with a depletion type NMOS as the load where theload threshold voltage is negative so that even with zero G-S voltage the transistor conducts.

In this case the load will be in saturation when

, , , , , DS L GS L th L DD o th L o DD th LV V V V V V V V V

When the output voltage is above this the load transistor moves to triode region.

(Note that the threshold voltage for the load here is a negative number.)


45/46

Lecture #19

CMOS inverter

V i V o

V SS

S

S

D

D

, ,

, ,

,

,GS n i DS n o

GS p i SS DS p o SS

V V V V

V V V V V V

When the input is LOW (0 Volt to the threshold voltage of NMOS, i.e.,V th,n) the NMOS is cut-off.

When the input is aboveV th,n the NMOS transistor conducts: It will be in saturation as long as,o i th nV V V and then it enters the triode region.

On the other hand, when the input is HIGH (V ss to V ss |V th,p|) the PMOS is cut-off.

When the input is belowV ss |V th,p| the PMOS transistor conducts: It will be in saturation aslong as , ,o i th p i th pV V V V V and then it enters the triode region.

Therefore, input logic0 and output logic1 corresponds to NMOS at cut-off and PMOS in triode:

, ,i th n o SSV V V V

Therefore, input logic1 and output logic0 corresponds to PMOS at cut-off and NMOS in triode:

, , , 0SS th p SS th p i SS oV V V V V V V

In between we have the transition region when both transistors conduct. We now split thetransition region into thee parts.


46/46

Just after NMOS comes out of cut-off, NMOS is saturated while PMOS is in triode, the transfer characteristic curve may be obtained from the following:

2 2, , , , DS n n GS n th n n i th n I k V V k V V

22

, , , , , ,2 2 p SG p th p SD p SD p p SS i th p SS o SS o SD pk V V V V k V V V V V V V I

Then with increasing input voltage at some point of time PMOS goes to saturation while NMOScontinues to remain in saturation, the transfer characteristic curve may be obtained from thefollowing:

2 2, , , , DS n n GS n th n n i th n I k V V k V V 2 2

, , , , p SG p th p p SS i th p SD pk V V k V V V I

Finally, we have NMOS entering triode region while PMOS continues in saturation. Then we have

2 2, , , , , ,2 2 DS n n GS n th n DS n DS n n i th n o o I k V V V V k V V V V 2 2, , , , p SG p th p p SS i th p SD pk V V k V V V I

Now we always try to have the two transistors symmetric in the sense that thek parameter besame (mobility in PMOS is less so the W/L ratio is to be taken large with respect to NMOS).However, generally the threshold voltages are somewhat different in magnitude although we willassume them to be same, i.e., the CMOS offers perfect symmetry.

Interestingly, we will see that when both the transistors are in saturation, the equation above do notinvolve any output voltage term. That means when both the transistors are saturated at someunique input voltage, the output drops (or rises) abruptly till NMOS (or PMOS) goes out of saturation.

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1 Digital Logic