1 Digital Cartesian feedback linearization Digital Cartesian Feedback Linearization of Switched Mode Power Amplifiers Alejandro Viteri, Amir Zjajo, Thijmen

1Digital Cartesian feedback linearization

Digital Cartesian Feedback Linearization of Switched Mode

Power AmplifiersAlejandro Viteri, Amir Zjajo, Thijmen Hamoen, Nick van der Meijs

Delft University of Technology


• Motivation

• Linearization by means of feedback

• Cartesian feedback modeling

• Digital design

• Simulation results

• FPGA synthesis & results

• Conclusions

Outline


Motivation

• A power efficient switch mode PA in the transmitter

• No power losses due to dissipation• Improves lifetime of batteries• Better use of the solar panels• Non-linear

ISIS Innovative Solutions In

Space

• New version of the transceiver

• Previous version of the transceiver

• A linear mode power amplifier (PA)


Feedback system with distortion

)()(1

)(

)(1

)()(

)(1

)(

)(

1)( sD

sL

sL

sL

sDsr

sL

sL

ssy fb

fw

Linearization by means of feedback

)()()( ssGsL Loop gain:

• In a feedback system linearity depends on the loop gain

• Distortion in the feedback is not attenuated

• Better control of the system linearity is achieved


General model

61 TpA

Cartesian feedback

• Stability condition (PM ≥ 60o)

• The signal is decomposed in Cartesian components

• Feedback is applied to each component

• A delay (e-Ts ) will model the latency of the digital domain


Phase shift problem

Cartesian feedback

Sources of phase shift

• Delays in the loop

• Distortion in the PA and

• Up/Down converters

• To changes and aging


Mixed signal model

Cartesian feedback

• The dominant poles of this system determine the stability• Oversampling allows to relax the order of the LPFs

• Allows integration

• Reduces area usage and weight in the satellite

• Low power consumption

Benefits


Stability analysis by root locus

Mixed-signal Cartesian feedback

21 TTApPM 1A

System root locus

60PM

Compensated system root locus

ff

f

zp

pz

10

3



seCs

fffs

TsDrPdin

error

0

22)(

Phase regulation

• Source signals modeled as a ramp signal s

fs s

s

2

)(

• Transfer function of phase error



DrPdin fffC 20

Phase regulation

• Final value theorem: )( lim)( lim0

sst errors

errort

00

20

s

TsDrPdin

eCs

fff

seCs

fffs

TsDrPdin

error

0

22)(



DrPdin fffC 20

IQQIkk

Ct

dt

dshift '')(

21

0

Phase regulation

'sin'' 21 kkIQQI

21

''

kk

IQQIerror


Digital design

• Delay correction by signal rotation

• Magnitude signal for envelope restoration


Architecture


Simulation results

• Amplification of 20 dB

• IMD -40 dBc satisfied


Logic

Utilization

Used/

Available%

4 input LUTs 428/1536 27%

MULT18x18 2/4 50%

I/O Blocks 87/97 89%

FPGA synthesis

• Spartan3 X3s50-4tq144• 50K System gates• 1536 equivalent logic

cells


Item Value Units

Bandwidth 9.6 kHz

Loop Gain 10

System delay 400 ns

Bit length 12 bits

Clk freq. 83.33 MHz

Clk cycles 15

Latency 180 ns

Slack 220 ns

Area 27 %

Power 33.31 † mW† Xilinx Xpower Analyzer

Results

• Power budget 1.7 W

• 33.31 mW in a FPGA

• 1.96% of the total power budget

• Latency of 180 ns

• Slack of 220 ns for A/D and D/A


• Mixed-signal Cartesian feedback proves to be an efficient linearization method for a stable system with sufficient phase margin.

• Feedback improves linearity when provided with an adequate amount of loop gain.

• The results show that the use of the CORDIC algorithm proves to be a simple, low-power and robust solution for the low bandwidth input signal.

Conclusions


THANK YOU

Documents

1 Digital Cartesian feedback linearization Digital Cartesian Feedback Linearization of Switched Mode Power Amplifiers Alejandro Viteri, Amir Zjajo, Thijmen