1 Delay Insensitivity does not mean slope insensitivity!
Vainbaum Yuri
Slide 2
2 Delay Insensitivity does not mean slope insensitivity! Paper
presented in NOC-2010 Authors : Florent Ouchet, Katell
Morin-Allory, Laurent Fesquet - TIMA Laboratory
4 Asynchronous circuit quality Self-timed circuit robustness
evaluation: PVT variations Chip aging: transistors, nets, vias Low
supply voltage Harden the behavior in harsh environment Avoid dead
locks Avoid wrong operations
Slide 5
5 Asynchronous circuit quality-Slopes Local effects on the
circuit: Very slow signal variations Slow slopes on pads and nets
Ex.: In synchronous design slopes are treated carefully Tools
developed to check slopes Designer must fix all slopes
violations
Slide 6
6 Asynchronous circuit quality-Slopes Self-timed circuit
assumptions usually reduced to delays But slopes must be
considered