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Chapter 2: Computer-System Structures

Computer System Operation I/O Structure Storage Structure Storage Hierarchy Hardware Protection General System Architecture

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Resources

MOST OF SLIDES: Operating System Concepts, Seven Edition; by: Silberschatz, Galvin, and Gane; publisher Wiley: http://www.os-book.com/

SOME PICTURES: Modern Operating Systems, Second Edition; by Andrew S. Tanenbaum; publisher: Prentice Hall.

SOME PICTURES: Internet Sites.

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Computer-System Architecture

Computer System:CPU & device controllers, connected to system bus and compete to access shared memory.

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Architecture of Pentium 3 Processor

http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1161a.html

http://www.vast.uccs.edu/~tboult/FRAME/Cutler/frame99.htm

I/O DeviceController

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Loading OS

Bootstrap program is first loaded ROM, E2PROM, Register initialization

Bootstrap loads Kernel of OS

Kernel loads rest of OS as needed I/O and applications mostly use hardware or software

interrupts to get service

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Computer-System Operation

I/O devices and the CPU can execute concurrently.

Each device controller is in charge of a particular device type.

Each device controller has a local buffer and programmable registers.

CPU moves data from/to main memory to/from local buffersIs there any other alternative?

I/O is from the device to local buffer of controller.

Device controller informs CPU that it has finished its operation by causing an interrupt.

General features:

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Interrupt-driven I/O operation Interrupt transfers control to the interrupt service routine

generally, through the interrupt vector, which contains the addresses of all the service routines.

Interrupt architecture must save the address of the interrupted instruction.

Incoming interrupts are disabled while another interrupt is being processed to prevent complicated situation to handle.

A trap is a software-generated interrupt caused either by an error or a user request.

Current operating systems are

interrupt driven.

Stack

Save /Restorestate

Role of DMA?

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Direct Memory Access Structure

Used for high-speed I/O devices able to transmit information at close to memory speeds.

Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.

Only one interrupt is generated per block, rather than the one interrupt per byte.

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Interrupt Handling

The operating system preserves the state of the CPU by storing registers and the program counter.

Determines which type of interrupt has occurred: polling vectored interrupt system

Separate segments of code determine what action should be taken for each type of interrupt

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Interrupt Time Line For a Single Process Doing Output

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I/O Structures Synchronous: after I/O starts, the user program waits

till the I/O operation is complete. Wait instruction idles the CPU until the next interrupt Wait loop (loop: jmp loop) At most one I/O request is processed at a time, no

simultaneous I/O processing.

Asynchronous: after I/O starts, control returns to user program without waiting for I/O completion. Requirements:

System call – request to the operating system to allow user to wait for I/O completion.

Device-status table contains entry for each I/O device indicating its type, address, and state.

Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt.

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Two I/O Methods

Synchronous Asynchronous

Interrupt handler not used

Device controllerIs programmed

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Device-Status Table

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Storage Structure Main memory – the only large storage media that the CPU can access directly.

DRAM; von Neuman architecture; Memory-Mapped I/O;

Secondary storage – extension of main memory that provides large nonvolatile storage capacity.

Magnetic disks – rigid metal or glass platters covered with magnetic recording material

Disk surface is logically divided into tracks, which are subdivided into sectors. Same tracks in platterrs: cylinder

Seek and latency time The disk controller determines the logical interaction between the

device and the computer. Floppy disk: low capacity / low speed disk

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Moving-Head Disk Mechanism

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Storage Hierarchy

Storage systems organized in hierarchy. Speed Cost Volatility

Caching – copying information into faster storage system; main memory can be viewed as a last cache for secondary storage.

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Caching

Use of high-speed memory to hold recently-accessed data.

Requires a cache management policy.

Caching introduces another level in storage hierarchy. This requires data that is simultaneously stored in more than one level to be consistent.

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Migration of A From Disk to Register

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Storage-Device Hierarchy

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numbers shown are rough approximations

Storage-Device Hierarchy….

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Hardware Protection

Dual-Mode Operation I/O Protection Memory Protection CPU Protection

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Dual-Mode Operation

Sharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly.

Provide hardware support to differentiate between at least two modes of operations.

1. User mode – execution done on behalf of a user.

2. Monitor mode (also kernel mode or system mode) – execution done on behalf of operating system.

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Dual-Mode Operation (Cont.)

Mode bit added to computer hardware to indicate the current mode: monitor (0) or user (1).

When an interrupt or fault occurs hardware switches to monitor mode.

Privileged instructions can be issued only in monitor mode.

monitor user

Interrupt/fault

set user mode

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I/O Protection

All I/O instructions are privileged instructions.

Must ensure that a user program could never gain control of the computer in monitor mode (I.e., a user program that, as part of its execution, stores a new address in the interrupt vector).

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Use of A System Call to Perform I/O

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Memory Protection

Must provide memory protection at least for the interrupt vector and the interrupt service routines.

In order to have memory protection, add two registers that determine the range of legal addresses a program may access:

Base register – holds the smallest legal physical memory address.

Limit register – contains the size of the range

Memory outside the defined range is protected.

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Use of A Base and Limit Register

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Hardware Address Protection

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Hardware Protection

When executing in monitor mode, the operating system has unrestricted access to both monitor and user’s memory.

The load instructions for the base and limit registers are privileged instructions.

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CPU Protection

Timer – interrupts computer after specified period to ensure operating system maintains control. Timer is decremented every clock tick. When timer reaches the value 0, an interrupt

occurs. Timer commonly used to implement time

sharing. Time also used to compute the current

time. Load-timer is a privileged instruction.

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Network Structure

Local Area Networks (LAN) Wide Area Networks (WAN)

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Local Area Network Structure

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Wide Area Network Structure