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CAD Challenges for Leading-Edge Multimedia Designs

CAD Challenges for Leading-Edge Multimedia Designs

Ira Chayut, Verification Architect

(opinions are my own and do not necessarily represent the opinion of my employer)

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Topics

Unique Requirements

Functional Verification

Synthesis

Physical Design

Manufacturability

Costs

Conclusions

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Unique Requirements

Short design cycles

Large international teams

Among the most complex and largest commercial creations

GPU Technology Transistors FrequencyPlaceable Instances Flops

Models C vs V

Directed Arch Tests

GDS2 File size

Gen1 0.25u 9M 125MHz 1M ~60K 90K/300K 300 800KBGen2 0.18u 25M 250MHz1 1.5M ~200K 100K/300K 6000 2GBGen3 0.15u 57M 350MHz1 3M ~500K 400K/800K 25000 4.5GBGen4 0.13u 130M 450MHz1 5.5M ~750K 700K/1.3M 50000 8GBGen5 0.11u 222M 525MHz1 12M ~1.2M 1M/1.6M 90000 16GBGen6 90nm 302M 700MHz1 16M ~1.6M 1.2M/1.9M 100000 19GB

1 - dual edge clocking

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Example: PS3 Graphics Chip

More than 300M transistors

About the same as the sum all of the following:

XBOX GPU (60M)

PS2 Graphics Synthesizer (43M)

Game Cube Flipper (51M)

Game Cube Gekko (21M)

XBOX Pentium3 CPU (9M)

PS2 Emotion Engine (10.5M)

Athlon FX 55 (105.9M)

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Each Generation Demands More

Copyright © NVIDIA Corporation 2005

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Looking Into the Crystal Ball

Features are set by the software industry leaders – we have to guess when new features will be required by the market

Shorter development cycles decrease the fuzziness in ourpredictions

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The Family Grows Quickly

Time matters - each new flagship product must be followed by derivatives – almost concurrently

Design Flow

Drivers

Class Definitions

C-models

Validation

Physical Verification

Custom cells

Test Insertion

Logic Verification

RTL

Micro-architecture

Floor Plan

TestReqmnts

Speed/PWR/Area Requirements

Data Path / STD Cell

Place&Route; Timing Optimize;

Data Path FoundryReqmnts

FoundryData

ExternalReqmnts

Emulation

Architecture & Algorithms

Simulation

TapeOut

Architecture ASIC Physical Design Software Marketing Operations Sales

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Size Matters

We are quickly approaching 1 Billion transistors with high logic-to-memory ratios

The complexity of our designs is growing faster than the number of transistors

All aspects of chip design affected, including: Verification, Synthesis, Physical Design, and Manufacturability

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Complexity Increases Exponentially

Chip component count increases exponentially over time (Moore’s law)

Interactions increase super-exponentially

IP reuse and parallel design teams mean more functions per chip

Verification gets combinatorially more difficult

Transistors per chip

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1995 2000 2005 2010 2015

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Functional Verification

Speed matters – Multimedia designs have a large pool of legacy tests, many of which are long running

Multiple vendor CAD tools must inter-operate smoothly

Verification now limits what features make it to silicon

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Why Verification is Unable to Keep Up

Verification effort gets combinatorially more difficult as functions are added

BUT

Verification staffing/time cannot be made combinatorially larger to compensate

AND

Chip lifetimes are short, which decreases the time available for verification

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Emulation – Necessary and Costly

$100 Million worth of emulators .... and growing

Multiple boxes needed for a single chip

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Synthesis

Synthesize early and synthesize often – CAD tools must support early synthesis to provide area, timing, and power estimates

Must have better correlation between logic synthesis and post-layout results

Early synthesis and layout can change the architecture and the design – this is only possible if problems are caught early in the design cycle

ECO support is growing in importance

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Physical Design

Deep submicron designs pose new problems for timing, power, and signal integrity

Leading-edge multimedia designs are so large that we have to decompose the problem into partitions

The number of partitions is growing and the size of chips (in clock cycles) is increasing

Timing budgeting across partitions can be very wasteful – CAD tools must be able to work across partitions (at least “skin deep”)

ECO support is growing in importance

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Holistic Approach

CAD tools and flow must consider power, area, and timing throughout the design process

Information from each tool must be able to fed back and forward to other tools in the flow

Each chip must be able to choose the best vendor’s tool for each step

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Manufacturability

Deep submicron technologies are much more affected by tiny variations between dies – CAD tools need to help increase yields by designing in margins (realizing that there are tradeoffs between these margins and size/speed)

At-speed wafer testing of enormous chips require on-chip support – CAD tools must make this automatic and painless with minimal silicon cost

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Money Matters

The costs of CAD tools and R&D staff are growing faster than the Multimedia TAM

CAD tools must decrease their cost-per-seat

CAD tools must make each engineer more productive over the entire design cycle

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Conclusions

Size matters

Performance matters

Inter-operability matters

Holistic view matters

Money matters