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Advanced Digital DesignSynthesis of Control Circuits
by A. Steininger and J. LechnerVienna University of Technology
© A. Steininger & J. Lechner / TU Vienna 2Lecture "Advanced Digital Design"
Outline
Control Circuits Petri Nets & Signal Transition Graphs
Properties Common PN/STG fragments
Synthesis of SI control circuits State Encoding Next-state functions Implementation
Synthesis tool: Petrify
© A. Steininger & J. Lechner / TU Vienna 3Lecture "Advanced Digital Design"
Control Circuits
Control logic essential part of asynchronous circuits How to specify? How to implement?
Control ?
Latc
h
Comb.Logic
Latc
h
Comb.Logic
Latc
h
Req Req ReqAck Ack Ack
Req
Ack
Req
Ack
© A. Steininger & J. Lechner / TU Vienna 4Lecture "Advanced Digital Design"
Petri Nets (PNs)
For modelling concurrent systems Directed graph with nodes and arcs Nodes: places, transitions Places can be marked with tokens Transition is enabled (allowed to fire) if
all input places have tokens When a transitions fires:
Token removed from all input places Token added to each output place
© A. Steininger & J. Lechner / TU Vienna 5Lecture "Advanced Digital Design"
STGs
Restricted subclass of petri nets PN transitions = signal transitions Simple places omitted (places with a
single input and a single output) Places/arcs represent causal
relationships between signal transitions Marking represents circuit state
© A. Steininger & J. Lechner / TU Vienna 6Lecture "Advanced Digital Design"
PN/STG - Example
Muller C-gate
Source:[Sparso 06]
© A. Steininger & J. Lechner / TU Vienna 7Lecture "Advanced Digital Design"
Properties of STGs I
Input free choice Alternative transitions only controlled by
mutually exclusive inputs 1-bounded
Max. one token per place Liveness
STG is live iff from every reachable marking, every transition can eventually fire
© A. Steininger & J. Lechner / TU Vienna 8Lecture "Advanced Digital Design"
Typical PN/STG Fragments
Choice
Merge
Fork Join
© A. Steininger & J. Lechner / TU Vienna 9Lecture "Advanced Digital Design"
PN/STG Fragments - Example
Source:[Sparso 06]
© A. Steininger & J. Lechner / TU Vienna 10Lecture "Advanced Digital Design"
Properties for STGs II
STGs can be implemented as speed-independent circuits. Requirements: Consistent state assignment
In any execution, any transition alternates between rising and falling
Persistency Enabled signals will eventually fire, cannot be
disabled by other transition Complete state coding (CSC)
Different markings must represent different states
11Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Speed-Independence (SI)
Delay-model: speed-independence Arbitrary gate delays (bounded but
unknown) Ideal zero-delay wires
Source:[Sparso 06]
12Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
STG Synthesis
Specification
State graph
State Graph with CSC
Next-State functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
13Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Specification
Source: [Sparso 06]
14Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State Graph
0000
0100
0110
0010
1000
1100
1110
1111
1101
b+
c+
b-
c-
a+
b+
d+
c+d-
a-
(a,b,c,d)
15Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Excitation Regions for Output Signal c
0000
0100
0110
0010
1000
1100
1110
1111
1101
b+
c+
b-
c-
a+
b+
d+
c+d-
a-
QR1(c+)
ER1(c+)
ER2(c+)
ER1(c-)
16Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Quiescent Regions for Output Signal c
0000
0100
0110
0010
1000
1100
1110
1111
1101
b+
c+
b-
C-
a+
b+
d+
c+d-
a-
QR1(c+)
QR1(c-)
17Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Next-State FunctionsKV Diagram for c
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
0000
0100
0110
0010
1000
1100
1110
1111
1101
b+
c+
b-
C-
a+
b+
d+
c+d-
a-
QR1(c+)
ER1(c+)
ER2(c+)
ER1(c-)
QR1(c-)
18Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Atomic Complex Gate Implementation
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
c = d + a‘b + bc
Attention: Decomposition into simple gates can introduce hazards!
19Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding Gates Implementation
Signals toggle between excitation and quiescent/stable regions ER(c+) QR(c+) ER(c-) QR(c-) etc.
Implementation with SR-latches, C-gates or generalized C-gates possible
Generalized C-element
Source: [Sparso 06]
20Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding GatesSet/Reset Functions
c = Set + c ∙ Reset‘ Set ∙ Reset = 0 Set Function:
must contain all states in ER(c+) may contain states in QR(c+) may contain not reachable states
Reset Function: must contain all states in ER(c-) may contain states in QR(c-) may contain not reachable states
21Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding Gates Implementation
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
Set function:c-set = d + a‘b
22Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding Gates Implementation
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
Set function:c-set = d + a‘b
Reset function:c-reset = b‘
23Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding Gates Implementation
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
Set function:c-set = d + a‘b
Reset function:c-reset = b‘
24Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding GatesHazards
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
0000
0100
0110
0010
1000
1100
1110
1111
1101
b+
c+
b-
c-
a+
b+
d+
c+d-
a-
010
010
0101 0
010
25Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding GatesMonotonic Cover Constraint
A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint)
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
Hazardous set function:c-set = d + a‘b
26Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
State-holding GatesMonotonic Cover Constraint
A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint)
cdab 00 01 11 10
00 0 x x F
01 R x x 1
11 0 R 1 1
10 0 x x x
Fixed set function:c-set = d + a‘bc‘
27Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
ExampleVME Bus Controller
LDS+ LDTACK+ D+
DTACK-
DTACK+ DSr- D-
DSr+
LDS-LDTACK-
VME BusController
DSr
DTACK
LDS
LDTACK
D
STG of Read Cycle
28Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
VME Bus ControllerCSC Conflict
DSr+10000 00000 01000
10100 00100 01100
10110 00110 01110
11111 01111
10010
10110
10111
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDTACK- LDTACK- LDTACK-
LDS- LDS- LDS-
LDS+
LDTACK+
D+
DTACK+ DSr- D-
(DSr, DTACK, LDTACK, LDS, D)
29Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
VME Bus ControllerCSC Conflict
LDS+ LDTACK+ D+
DTACK-
DTACK+ DSr- D-
DSr+
LDS-LDTACK-
10110
LDS+ LDTACK+ D+
DTACK-
DTACK+ DSr- D-
DSr+
LDS-LDTACK-
10110
30Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Resolving CSC ConflictConcurrency Reduction
Solution I: Remove conflict state by concurrency reduction
DSr+10000 00000 01000
10100 00100 01100
10110 00110 01110
11111 01111
10010
10110
10111
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDTACK- LDTACK- LDTACK-
LDS- LDS- LDS-
LDS+
LDTACK+
D+
DTACK+ DSr- D-
31Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Resolving CSC ConflictConcurrency Reduction
Solution I: Remove conflict state by concurrency reduction
DSr+10000 00000 01000
10100 00100 01100
00110 01110
11111 01111
10010
10110
10111
DSr+
DTACK-
DTACK-
DTACK-
LDTACK- LDTACK- LDTACK-
LDS- LDS-
LDS+
LDTACK+
D+
DTACK+ DSr- D-
32Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Resolving CSC ConflictConcurrency Reduction
Concurrency reduction reflected by adding an arc to the STG specification. Introduces timing assumption (LDS- before
DSr+)
LDS+ LDTACK+ D+
DTACK-
DTACK+ DSr- D-
DSr+
LDS-LDTACK-
33Lecture "Advanced Digital Design" © A. Steininger & J. Lechner / TU Vienna
Resolving CSC ConflictAdding State Signal
Solution II: Inserting an internal state signal to make conflict states unique
DSr+100000 000000 010000
101000 001000 011000
101100 001100 011100
111111 011111
100101
101101
101111
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDTACK- LDTACK- LDTACK-
LDS- LDS- LDS-
LDS+
LDTACK+
D+
DTACK+ DSr-
D-
(DSr, DTACK, LDTACK, LDS, D, CSC)
100001CSC+
011110CSC-
© A. Steininger & J. Lechner / TU Vienna 34Lecture "Advanced Digital Design"
Petrify
Synthesis of speed independent control circuits from STG specifcations Simple text format for describing STGs
Petrify can solve CSC problem Public domain tool
Developed at different universities http://www.lsi.upc.edu/~jordicf/petrify/
© A. Steininger & J. Lechner / TU Vienna 35Lecture "Advanced Digital Design"
Petrify - Example
.model cgate
.inputs a b
.outputs c
.grapha+ c+b+ c+c+ a-c+ b-a- c-b- c-c- a+c- b+.marking { <c-, a+> <c-, b+> }.end
© A. Steininger & J. Lechner / TU Vienna 36Lecture "Advanced Digital Design"
Petrify
Set of command-line tools petrify: synthesis command write_sg: derives state graph draw_astg: draws STGs/state graphs
Different circuit implementations Complex gates (-cg) Generalized C-elements (-gc) Specific target library (-tm)
© A. Steininger & J. Lechner / TU Vienna 37Lecture "Advanced Digital Design"
Summary
Control logic essential part of asynchronous circuits
PNs/STGs convenient for modeling control circuits
STGs need to fulfill certain properties Input-free choice, 1-bounded, CSC, etc.
Synthesis from STGs to SI gate implementations possible Tool available: Petrify