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Adaptive Data Analysis and Processing Technology

(ADAPT)

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Reconfigurable Computers for Spacecraft Use

• Adapt to changing mission requirements after launch• Reduce spacecraft resources for onboard storage and downlink from

high data bandwidth instruments by reducing data rates from the instruments

• Hardware fabrication before algorithms are completed• Update or correct algorithms after launch• Reduce engineering set up times for science observatoriesReduced

setup times• FPGAs offer high performance and processing power • Physical design remains the same; easily tailor control and data

interfaces • Minimizes instrument and system development time• Mitigates hardware and software errors in flight • Multiple configurations can be stored for rapid adaptations

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AIM 1st Demonstration – Reconfigurable Computing in Space

• FedSat-1 – 50 kg microsatellite, LEO ~1000 km altitude

• Adaptive Instrument Module (AIM) - Precursor to ADAPT

– Includes an 80C196 processor and a Xilinx XQR4062 FPGA that performs reconfigurable processing

– 890 grams, dissipates < 2 W

– Launched December 14, 2002 on Australian FEDSAT

– AIM partners - APL, Queensland University of Technology, Goddard Spaceflight Center, and Langley Research Center

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Challenge

• Challenges for effective use in spacecraft: Configuration Memory Upsets: SRAM-based FPGAs are

susceptible to radiation-induced upsets in configuration memory. The frequency of these upsets must be investigated, and techniques developed to detect and correct them.

Management of Multiple Configurations: Spacecraft have limited onboard resources and limited communications to ground stations. Techniques for managing the configuration data for FPGAs onboard a spacecraft will be very different than ground applications. These techniques need to be investigated, developed and analysed.

Prototype Demonstration: A prototype AIM needs to be flown as a standalone experiment on a space mission to validate the initial design decisions made and evaluate improvements in satellite performance.

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Requirements

• Implement a low cost, radiation hardened, reconfigurable processor for Fedsat-1 and other spacecraft

• Use Xilinx XQR4062 FPGA as the heart of the reconfigurable processor

• Store and manage multiple Xilinx FPGA configurations• Able to upload additional configurations• Detect, correct, and log single event upset induced configuration

errors autonomously in the Xilinx FPGA• Run standalone reconfigurable computing experiments• Process instrument data with reconfigurable hardware• Interface to spacecraft command and data handling system• Generate voltages from spacecraft +28V bus

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Design• The AIM consists of the following components:

– A 62,000 gate SRAM-based FPGA ( Xilinx XQR-4062XL)– A 16-bit microcontroller ( UTMC UT80C196KD) – 512 kbytes of EEPROM to hold microcontroller boot and application

code– 8 Mbytes of non-volatile Flash to hold configurations for the Xilinx– 1 Mbyte of SRAM for microcontroller program and data– 0.5 Mbytes of SRAM for Xilinx data processing memory– An RS422 serial port for communication with the satellite command &

data handling system– An uncommitted communications port connected directly to the Xilinx, to

be configured on a mission-by-mission basis.– Power converter circuitry to provide 3.3V and 5V from 28V– Voltage and Temperature status lines

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AIM Flight Module Area Study

175 mm (6.83 in)

Flight Unit Characteristics

• Weight: estimated 1 kg

• Size: 16 cm x 17.5 cm x 3.0 cm

• Power: 2.5W (from +28V)

• Parts selected for radiation tolerance and availability:

– Xilinx XQR4062XL - 62,000 gate SRAM-based FPGA

– UTMC UT80C196KD 16-bit microcontroller

– SEI 28C010TRPFB-15 512Kx8 EEPROM

– SEI 29F0408RP 4Mx8 Flash

– Austin/Motorola 5C512K8F 512Kx8 SRAM

– Actel A1280A fuse link FPGA

D C /D C C onv.h = 8 .38

LT1086

LM193

LM18

5

Xilinx XQ R 4062XLFP G A

A cte l 1280AFP G A

U TM C80C 196K D

M icrocon tro lle r

128K x 8E E P R O M

128K x 8E E P R O M

512K x 8S R A M

512K x 8S R A M

512K x 8S R A M

4M B x 8FLA S H

4M B x 8FLA S H

HC

14H

C14

HC

14

422R

422T

HC14

Osc.

S pareS pare

E M I F ilte rh = 8 .38

25

pin

9 p in

9 p in

9 p in

AC74

145 mm (5.65 in)

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AIM Flight Unit Test

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ADAPT Objectives• Develop a prototype reconfigurable processor utilizing state-of-the-art

Field Programmable Gate Array technology

• Develop algorithms that meet the requirements for two Earth Science Enterprise mission scenarios

– Microwave Radiometers

– Fourier Transform Spectrometers (FTS)

• Design, fabricate, and test a flight-grade reconfigurable processor

• Demonstrate algorithms using flight-grade reconfigurable processor

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ADAPT Hardware Design- commercial standards

• Xilinx Virtex II FPGA (XC2V1000)– Equivalent of 1 million gates and 720k bits of RAM– 40 Dedicated 18x18 Multipliers (300 MHz) – A wide range of IP cores are available:

• DSP functions• Processors• Math functions

• New designs can be implemented with a wide range of development tools

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ADAPT - Hardware Definition• ADAPT stores multiple FPGA configurations in flash memory. • Instrument processing algorithms can be changed in real time.

– Fuse-programmed Actel FPGA implements the system interface – Host processor chooses configurations for the Xilinx Virtex II FPGA.

• Operation:– Host selects configuration– Second Actel FPGA reads back and verifies configuration of Xilinx FPGA – Automatically corrects the configuration and notifies the host processor when it detects

discrepancies.• Xilinx FPGA connects to external SRAM memory to store intermediate results,

coefficients, and variables• Voltage regulators supply the low-voltage• Backplane supplies standard +3.3 and +5V power• Xilinx clock may derive from:

– on-board oscillator – the PCI bus clock– or from the I/O connector

• Xilinx FPGA on-chip temperature sensor routes to I/O connector.• Instrument data flow through:

– PCI bus – I/O connector

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ADAPT Board Block Diagram

Front Panel I/O Connector (Instrument Data)

Xilinx Virtex II FPGA (XC2V1000)

SRAMOscillator Voltage Regulators

PCI Bus Power

J2 I/O Connector on back-plane (Instrument Data)

Actel Host interface

Actel Supervisor

(Configuration/Readback)

Flash Memory

PCI Bus (Host Processor Communications)

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Xilinx Virtex-II Million-gate FPGA

Supervisor FPGA (Actel A54SX32) performs continuous Xilinx configuration checking

Host FPGA (Actel A54SX32) implements32-bit CompactPCI interface

Instrument Interface, 192-pin connector

128Kx32 SRAM

CompactPCI J1 Connector forHost interface

CompactPCI J2 Connector provides

additional I/Ocapability

FLASH MemoryHolds multiple

Xilinx FPGAconfigurations

ADAPT Breadboard

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ADAPT Configuration Manager

• Implemented in Actel 54SX32 radiation hardened FPGA– Hardware Triple-Voted S-Modules

• Runs at 50MHz

• VHDL Design– modeled after C program which was initially

used to verify the config/readback scheme

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ADAPT Configuration Manager

Flash MemoryInterface

XilinxSelectMapInterface

StateMachine

Data to PCI Actel

Commands from PCI Actel

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ADAPT Configuration Manager Modes

START(IDLE)Xilinx configuration

UPLOAD

On Command ThroughPCI Host Actel

Configuration occurs frame by frameAs opposed to normal Xilinx UploadThis allows data structure stored inMemory to be the same for readback /SEU correction.

Xilinx ContinuousFrame-wise readback

During frame-by-frame readback, Contents of each frame are comparedWith contents of rad-hard Flash. (Mask and config bits are interleaved)

If all goes well

error

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ADAPT Configuration Manager Modes

Put Xilinx backinto write mode

Write CorrectedFrame, Pad Pipeline

Switch Xilinx back to read Mode

Xilinx Active Partial Reconfiguration is used, new configuration frame is uploaded while the device is operating.

Xilinx experiences no operation interruption

Signal PCI Host Interfacewhich makes IRQ

Manager continues reading where it left off before encountering SEU

Times : Programming : 100 msRoundtrip Readback : 200 ms

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ADAPT Host Interface FPGA

• Implemented in Actel 54SX32 • Uses Actel IP : PCI Core v 5.2.1

– APL is targetting this core for other space missions

– some corrections incorporated • bug fixes• workarounds for Actel timing hazards as they are

discovered.

• 33 MHz, 32-bit PCI Target Only

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ADAPT Host Interface FPGA

Flash Control / Data

Write - Fifo

PCI Interface

To 3V CompactPCI Backplane Config Manager

Control / Status

Read - Fifo

To Xilinx

From Xilinx

under development

To ConfigManager

Interrupt (currentlyAssociated with SEU Detection)

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ADAPT Usage Flow + Software

• Design Xilinx using ISE Foundation Toolset– Use Rad-tolerant techniques to protect RAM and flipflops

• Use ADAPT compiler and linker to generate files suitable for residing in flash memory

• Use ADAPT flash-software to program flash from flashfile.

• Send command through PCI interface to start (configure) Xilinx with a particular config from flash.– If option is enabled, SEU mitigation will proceed immediately

upon successful configuration– Status of configuration / readback process can be read through

software driver.

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Upcoming Test / Refinements

• Testing of Host Interface FIFOs to allow Xilinx to send data via PCI if desired

• Make slight modification to Compiler / Linker to store multiple configurations in Flash

• Packaging Software into a more user-friendly installation package

• Simulation of SEU in Xilinx FPGA• Environmental tests• Radiation tests

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Example of ADAPT Instrument

• ADAPT will implement real time data reduction, compression, and feature extraction algorithms.

• Minimizes spacecraft resources– onboard data storage– downlink bandwidth

• Generic design can be used for different instruments

ADAPT

SpacecraftC&DH

Interface

InstrumentSensor

SpacecraftPower

InstrumentProcessor

Front EndElectronics

SpacecraftInterface

3U

Co

mp

act P

CI

Ba

ckpla

ne

DC/DCConverters

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Microwave Radiometer Digital I & Q

Z-1

Z-1

Z-1

Z-1

Z-1

1/64

-5/64

20/64

20/64

-5/64

1/64

Σ

Z-1 Z-1 Z-1 -32/64

1,-1,1,-1,…

-1,1,-1,1,…

DemultiplexerDigitized

Radiometer Signal (6-bit

data)

QX

IX

64 MHz data rate 32 MHz data rate

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Microwave Radiometer Digital Correlator

Ch 2, 6-bit data

Digital I & QDigital I & Q

Digital I & QDigital I & Q

MAC

I1xI1

I1xQ2

Q1xQ1

Q1xI2

I2xI2

I2xI1

Q2xQ2

Q2xQ1

(0.1 sec Integration Period)

MAC

I1xI1

I1xQ2

Q1xQ1

Q1xI2

I2xI2

I2xI1

Q2xQ2

Q2xQ1

(0.1 sec Integration Period)

Ch 1, 6-bit data

I1

Q1

I2

Q2

Parallel-to-Serial

Converter/Multiplexer

Parallel-to-Serial

Converter/Multiplexer

Serial Output

ADAPT BOARD

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LVDS Receiver Box

Radiometer Interface

Box

ADAPT Hardware

Microwave Radiometer Interface Hardware

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FTS Motion Control Application

VHDL-coded 16-bit Motion Controller for Fourier Transform Spectrometers

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FTS System

MotionControl

GSE&

DataCollection

ADC18-bits

LaserDetector

IR Detector

)(*IR

VelocityetSampleOffs

Velocity Spectral Resolution (~0.25 cm-1)

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Control Configuration

CNTin PID(COMPENSATOR)

HW

Decode

-

+ Electronics

VHDL

CNTfbk

Motion Control

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)]([)()(PINDIIINP

EEKEKEKDAC

& Compensator

CL

AM

P

CL

AM

P

TC

toMO(-) PID DAC

CNTin

CNTfbk

Tc

20

2021 20 40 16 16

Latch

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Electronics

U4

PA07/AMOUT1

+4

-5

CL+2

CL-8

V+3

V-6

BAL7

Vdd

Vee

Rs175k

C1 0.1U

Vee

C2 0.1U

Vdd

C3 10U

C4 10U

0

0

ToMotor

Rl+0.64

Rl-0.64

Vdd

VeeU1

OP-27/AD

+3

-2

V+7

V-4

OUT6

N11

N28

U2

OP-27/AD

+3

-2

V+7

V-4

OUT6

N11

N28

C1 10u

C2 10u

C3 10u

C4 10u

C5 0.01u

C6 0.01u

C7 0.01u

C8 0.01u

Vdd

Vdd

0

0

0

0

Vee

Vee

R1 1.1k

R2 1.5k

R3 10k R4 10k

R5 10k

R6 10k

Voffset

0

R1110k

R1210k10K POT

0

D31N43761

2

D41N43761

2

R135k

R8 =1k

D1

1N4742

1 2

D2

1N474212

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Resource Utilization for Xilinx Virtex-II Million Gate Device• Number of Slices:

324 out of 5,120 – 6%

• Number of Flip Flops:

182 out of 10,240 – 1%

• Number of LUTs: 592 out of

10,240 – 5%

RMS Velocity Error

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Use of ADAPT Technology in IIP3U CompactPCI Chassis

Real-Time Display/User Interface Computer

Real-Time Display/User Interface Computer

1.26 GHz PXI Embedded Controller

1.26 GHz PXI Embedded Controller

Ethernet InterfaceEthernet Interface

Solid State Disk (OS, Program

files, etc.)

Solid State Disk (OS, Program

files, etc.)

IDEInterface

CompactPCI Bus

4-Axis Controller4-Axis ControllerLRE Etalon Control Electronics

LRE Etalon Control ElectronicsLRE EtalonLRE Etalon PZT Control

Capacitive

Sensor Feedback

4-Axis Controller4-Axis ControllerHRE Etalon Control Electronics

HRE Etalon Control ElectronicsHRE EtalonHRE Etalon PZT Control

Capacitive

Sensor Feedback

Stepper Motor for Scene Selection

Mirror

Stepper Motor for Scene Selection

Mirror

Pixel Binning and Frame Averaging

Electronics

Pixel Binning and Frame Averaging

Electronics

Readout Integrated

Circuit

Readout Integrated

CircuitFPAFPA

Analog Inputs (Housekeeping

Parameters)

Analog Inputs (Housekeeping

Parameters)

Analog Interface Electronics

Analog Interface Electronics 16-Channel A/D16-Channel A/D

73 GB Rugged Removable Hard

Drive

73 GB Rugged Removable Hard

DriveSCSI InterfaceSCSI Interface

GPS InterfaceGPS Interface

Yellow = Performed by ADAPT hardwareGreen = Could be performed with ADAPT hardware

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Accomplishments

• Developed a simplified technique for partial-reconfiguration (SEU correction)

• Efficient format for storing configuration/readback data in flash memory developed (3 x reduction in memory over standard bitstream format)

• Convert Xilinx bitstream files to ADAPT formatFabricated ADAPT board• Completed design/assembly/test of test-adapter board that allows

software driven testing of Xilinx configuration interface• Demonstrated configuration / active readback / partial active

reconfiguration (correction) Host Actel designed and tested• Developed Host Software:

– Linux Device Driver– Bitfile Compiler / linker– Flash erase / program / verify– Configuration Loader

• Demonstrated upload,readback, partial reconfiguration under Actel control