1 A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani Email: {msaeedi, msedighi, szamani}@ aut.ac.ir

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A Novel Synthesis Algorithm for Reversible Circuits

Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb ZamaniEmail: {msaeedi, msedighi, szamani}@ aut.ac.ir

Quantum Design Automation Lab, Computer Engineering Department

Amirkabir University of Technology

Tehran, Iran

ICCAD 2007

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Outline

Introduction Basic Concept Previous Work Proposed Synthesis Algorithm Experimental Results Future Works Conclusions

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Introduction

Boolean reversible functions n-input, n-output, Unique output

assignment Example: a 3-input, 3-

output function (0,1,2,7,4,5,6,3)

a0 a1 a2 f0 f1 f2 F

0 0 0 0 0 0 0

0 0 1 0 0 1 1

0 1 0 0 1 0 2

0 1 1 1 1 1 7

1 0 0 1 0 0 4

1 0 1 1 0 1 5

1 1 0 1 1 0 6

1 1 1 0 1 1 3

AND

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Power dissipation

Landauer’s paper Every lost bit causes an energy loss When a computer erases a bit of information,

the amount of energy dissipated into the environment is at least kBTln2

Bennett’s paper To avoid power dissipation in a circuit, the

circuit must be built with reversible gates

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Applications of reversible circuits

Low power CMOS design Reversible 4-bit adder

“A reversible carry-look-ahead adder using control gates”, Integration, the VLSI Journal, vol. 33, pp. 89-104, 2002

384 transistors with no power rails

Optical computing Quantum computing

Each unitary quantum gate is intrinsically reversible

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Basic Concept

Definition: A -CNOT is a (k+1)(k+1) gate. It leaves the first k inputs unchanged, and inverts the last if and only if all others are 1. The unchanged lines are referred to as control lines.

Clearly, the -CNOT gates are all reversible. The first three of these have special names.

k inputs

(k+1)th input

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Basic Concept

The zero-CNOT is just an inverter or NOT gate, and is denoted by N. It performs the operation (x)(x1)

The one-CNOT, which performs the operation (y,x)(y,xy) is referred to as a Controlled-NOT , or CNOT (C).

The two-CNOT is normally called a TOFFOLI (T) gate, and performs the operation (z,y,x)(z,y,xyz)

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Basic Concept

Reversible gate Various reversible gates

CNOT-based gates NOT, CNOT, C2NOT (Toffoli), …

Generalized Toffoli gate Positive controls Negative controls

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Synthesis of Reversible Circuits

High-levelDescription

Gate-level circuits

Physical Implementation

Synthesis

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Synthesis Algorithms Categories

Constructive algorithms Construct a circuit from a given specification

(i.e. truth table, PPRM expansion, decision diagrams, …)

The resulted cost may not be optimized The time complexity of the algorithm may be

too high

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Synthesis Algorithms Categories (Cont’d)

Search-based methods Also called substitution-based methods Use common sub-expressions to simplify the input

function All possible gates should be evaluated at each step The best possible gates are selected based on a

predefined function The algorithm convergence is not guaranteed An extensive exploration is required A time consuming procedure

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Transformation-based algorithms Used to improve the cost of circuit Sometimes applied on the results of other

algorithms Usually use templates to optimize a circuit

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A transformation based algorithm [18] Basic algorithm

Uses row-based operations Output permutation

Tries all n! output permutations to simplify the result

Control input reduction To reduce the number of control qubits

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Bidirectional algorithm To apply the method in both directions

simultaneously Template matching

A template consists of a sequence of gates to be matched and the sequence of gates to be substituted when a match is found

A time consuming procedure

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The Proposed Algorithm

Definition: Output Translation The application of a reversible CNOT-based

gate at the output side of a reversible specification F

The result of using an output translation will also be reversible

Only one function is changed at a time after using an output translation

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The Goal of the Algorithm

To generate a set of ordered output translations

When applied to the reversible specification F, generates ai from fi

g1 g2 gk

a1

a2

an

f1

f2

fn

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Applying an Output Translation

Lemma 1 explains the results of using an output translation on a given specification: (a) Applying an output

translation, exchanges the location of 2k minterm pairs where k≤n-1

a0 a1 a2 f0 f1 f2 F

0 0 0 0 0 0 0

0 0 1 0 0 1 1

0 1 0 0 1 0 2

0 1 1 1 1 1 7

1 0 0 1 0 0 4

1 0 1 1 0 1 5

1 1 0 1 1 0 6

1 1 1 0 1 1 3

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Exchanging Minterm Locations

(b) Exchanging the location of 2k-1 (k=n-m+1) minterm pairs produces the same result as applying an output translation if: All 2k minterms have the same value on m-1

particular bit locations The two minterms of each pair differ only in

one bit position

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Proof: An output translation CNOTm(f1,f2,…,fm-1,fm) is applied to F where fk for k {1 to m-1} can also be a ∈complemented function.

This output translation maps fm to (f1 f2 …fm-1) f⊕ m where the value of (f1 f2 …fm-1) is 1, there are 2k (k=n-m+1) minterms.

By using CNOTm, the location of these 2k minterms are changed. Moreover, it can be checked CNOTm exchanges the locations of all 2k-1 minterm pairs mi : fm = 0 and mj : fm = 1.

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1111

0

00

1111

1

00

Exchange location of minterm pair

n-m

m

m-1

f1

f2

f3

f4

f5

f6

f7

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Specification F(a1,a2,…,an) = (f1,f2,…fn)

1111

0

00

1111

1

00

Exchange location of minterm pair

f1

f2

f3

f4

f5

f6

f7

1111

1

00

1111

0

00

a1

a2

a3

a4

a5

a6

a7

CNOTm(f1,f2,…,fm-1,fm)

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Select the ith minterm of output functions

Mark it as visited

If its jth variable is not correct

Find a minterm which differs from it in its jth

variable

If the new minterm is below the current

minterm

Exchange their locations

Mark it as visited

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The Proposed Algorithm (Cont’d)

If the new minterm is above the current

minterm

If the new minterm is not in the right location

Exchange their locations

Mark it as visited

Repeat the previous steps for all minterms

and all variables

until ak=fk for each k

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Input: A reversible specification F (a1, a2, …, an) = (f1 , f2, …, fn)

Output: A set of reversible CNOT-based gates which when applied to F

produces an identity function.

Notation: The ith function (variable) of jth minterm is denoted as fi,mj

(ai,mj). Consequently, The ith minterm of jth function (variable) is

denoted as mi,fj (mi,aj)

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i = 1;

repeat

reset all of the 2n minterms to be unvisited.

for each minterm mj (j = 1 ... 2n) do

if mj is not visited then

if fi,mj ≠ai,mj then

Extract the set of output translations (gates) based on Lemma 1

i = (i+1) mod n;

until fi=ai for each i (1…n)

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The Proposed Algorithmbegin

mark the minterm mj,fi as a visited minterm

select the minterm mk,fi which differs from mj,fi in its ith variable

if mk,fi is below mj,fi then

exchange the locations of mj,fi and mk,fi. (Therefore fi,mj =ai,mj)

mark the minterm mk,fi as a visited minterm

else if mk,fi is above than mj,fi then

if fp,mk ≠ap,mk (p=1...n) for at least one p then

exchange the locations of mj,fi and mk,fi. (Therefore fi,mj =ai,mj)

mark the minterm mk,fi as a visited minterm

end

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Example

a0 a1 a2 f0 f1 f2 f0 f1 f2 f0 f1 f2 f0 f1 f2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 1 0 0 1 0 0 1 0 0 1

0 1 0 0 1 0 0 1 0 0 1 0 0 1 0

0 1 1 0 1 1 0 1 1 0 1 1 0 1 1

1 0 0 1 1 1 1 0 1 1 0 0 1 0 0

1 0 1 1 0 1 1 1 1 1 1 1 1 0 1

1 1 0 1 1 0 1 1 0 1 1 0 1 1 0

1 1 1 1 0 0 1 0 0 1 0 1 1 1 1

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Gate Extraction Method

1

1

1

1

f2(new)=f2f1f3

1 1

1

1

f3(new)=f3f1f2'

1

1

1

1

f2(new)=f2f1f3

a1

a2

a3

f1

f2

f3

Obtained gates should be applied in the reverse order

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The Algorithm Convergence

Theorem 1: The proposed algorithm will converge to a possible implementation after several steps Each output translation does not change the

results of the previous ones Only one function is changed at a time after

using an output translation

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The Time Complexity

Assumption: At most h gates are needed Search-based method

n2n-1 gates must be evaluated to select the best possible gates at each step

At most (n2n-1)h gates should be evaluated The proposed algorithm needs O(h×2n) steps to

reach a result

111

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21 2)...(2 nn

nnnn nCCnCC

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Search-based Tree

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Experimental Results

Ckt # Specification

Number of GatesNumber of Searched Nodes

& Steps

Proposed Algorithm

(Basic)[15],[17]

Proposed Algorithm

(Basic)[17] [15]

1 (1,0,3,2,5,7,4,6) 6 4 48 15 11

2 (7,0,1,2,3,4,5,6) 3 3 24 300 761

3 (0,1,2,3,4,6,5,7) 3 3 24 10 7

4 (0,1,2,4,3,5,6,7) 7 5 56 786 156

5(0,1,2,3,4,5,6,8,7,9,10,11,12,13,14,15)

15 7 240 8256 9515

6 (1,2,3,4,5,6,7,0) 3 3 24 4 4

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Experimental Results (Cont’d)

Specification

Number of Gates Searched Nodes

Proposed Algorithm

(Basic)[15], [17]

Proposed Algorithm

(Basic)[17] [15]

7 (1,2,3,4,5,6,7,8,9,10,11,12,13,14, 15,0) 4 4 64 5 5

8 (0,7,6,9,4,11,10,13,8,15,14,1,12,3,2,5) 3 4 48 139 230

9 (3,6,2,5,7,1,0,4) 8 7 64 66 -

10 (1,2,7,5,6,3,0,4) 8 6 64 77 -

11 (4,3,0,2,7,5,6,1) 8 7 64 4387 -

12 (7,5,2,4,6,1,0,3) 6 7 48 352 -

13 (6,2,14,13,3,11,10,7,0,5,8,1,15,12,4,9) 23 15 368 678 -

Average 7.46 5.76 87.38 1159 1336

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Circuit # Specification

Number of Gates

Proposed Algorithm

(Bidirectional)

[18](Bidirectional)

1 (1,0,3,2,5,7,4,6) 4 4

2 (7,0,1,2,3,4,5,6) 3 3

3 (0,1,2,3,4,6,5,7) 3 3

4 (0,1,2,4,3,5,6,7) 5 6

5(0,1,2,3,4,5,6,8,7,9,

10,11,12,13,14,15)7 14

6 (1,2,3,4,5,6,7,0) 3 3

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Specification

Number of Gates

Proposed Algorithm

(Bidirectional)

[18](Bidirectional)

7(1,2,3,4,5,6,7,8,9,10,

11,12,13,14,15,0)4 4

8(0,7,6,9,4,11,10,13, 8,15,14,1,12,3,2,5)

4 4

9 (3,6,2,5,7,1,0,4) 6 7

10 (1,2,7,5,6,3,0,4) 6 7

11 (4,3,0,2,7,5,6,1) 5 7

12 (7,5,2,4,6,1,0,3) 5 9

13 (6,2,14,13,3,11,10,7,0,5,8,1,15,12,4,9) 9 17

Average 4.92 6.72

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All possible 3-input/3-output reversible circuits (8!=40320) are synthesized

Average number of gates per circuit The proposed algorithm: 7.28

Average number of steps per circuit = 63.87 It takes about 4 minutes to synthesize all circuits

0.006 seconds for each circuit on average

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Future Directions

Working on the improvement of the resulting synthesized circuit By combining the proposed approach and the

search-based methods By selecting the best possible variable at each

step

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Conclusions

A new non-search based synthesis algorithm was proposed

Several examples taken from the literature are used

The proposed approach guarantees a result for any arbitrarily complex circuit

It is much faster than the search-based ones

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Thank you for your attention!

Documents

1 A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani Email: {msaeedi, msedighi, szamani}@ aut.ac.ir