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C.A.D. Intellectual AgendaC.A.D. Intellectual Agenda Roadmapping: “Living Roadmap” to connect applications, architectures, Roadmapping: “Living Roadmap” to connect applications, architectures,

components, technologiescomponents, technologies Design envelopes; Impacts of innovations; FCRP portfolio gapsDesign envelopes; Impacts of innovations; FCRP portfolio gaps Synergies: Drivers, Power-Energy, Reliability, C2S2 Fabrics, MSD, IFCSynergies: Drivers, Power-Energy, Reliability, C2S2 Fabrics, MSD, IFC

Focus on SiP physical implementation platforms (CLC, SOS)Focus on SiP physical implementation platforms (CLC, SOS) Huge hole in FCRP understandingHuge hole in FCRP understanding Need technology and cost modeling, tools, implementation, roadmappingNeed technology and cost modeling, tools, implementation, roadmapping Concrete high-end design driver (initially, CLC SiP driver highlighting logic-DRAM Concrete high-end design driver (initially, CLC SiP driver highlighting logic-DRAM

integration, DARPA MSP (Boeing STAP))integration, DARPA MSP (Boeing STAP))

Interfaces and standards (“infrastructure”) for design processInterfaces and standards (“infrastructure”) for design process Internal to flows and methodologiesInternal to flows and methodologies External: down (manufacturing variability models, mask flow handoff, cluster tool External: down (manufacturing variability models, mask flow handoff, cluster tool

abstractions, … ) or up (IO cells, signaling standards, logic, system-level, …)abstractions, … ) or up (IO cells, signaling standards, logic, system-level, …) Measurement and quantification of design quality, design productivityMeasurement and quantification of design quality, design productivity

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Concrete OutcomesConcrete Outcomes Task 1: Living Roadmap (from applications through ITRS technologies)Task 1: Living Roadmap (from applications through ITRS technologies)

Cost-awareCost-aware Gaps Gaps research + tool needs research + tool needs

Manufacturing handoff, die-package interface, variability, global signaling, Manufacturing handoff, die-package interface, variability, global signaling, synchronization, power delivery, robustness, …synchronization, power delivery, robustness, …

GTX grows into a system-level analysis tool that is validated with design driversGTX grows into a system-level analysis tool that is validated with design drivers Task 2A: Develop SiP implementation platformsTask 2A: Develop SiP implementation platforms

Platform-specific tools and roadmappingPlatform-specific tools and roadmapping Task 2B: High-End (“Radar on a Chip”) DriverTask 2B: High-End (“Radar on a Chip”) Driver

Demonstration vehicle for overall GSRC methodology and CLC SiP-specific toolsDemonstration vehicle for overall GSRC methodology and CLC SiP-specific tools Driver scaling + extrapolationDriver scaling + extrapolation Integration paths for GSRC’s and other design methodologiesIntegration paths for GSRC’s and other design methodologies

Task 3: Design process infrastructureTask 3: Design process infrastructure Design data models and interfaces Design data models and interfaces current enablers, future standards current enablers, future standards Reusable, composable solvers Reusable, composable solvers rapid flow synthesis/optimization rapid flow synthesis/optimization Concrete realizations of GSRC and other methodologiesConcrete realizations of GSRC and other methodologies

with metrics and automated evaluators (bX)with metrics and automated evaluators (bX)

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Working SessionsWorking Sessions GoalsGoals

Drivers: Which ones? How they unify GSRC activities? Key research gaps? Drivers: Which ones? How they unify GSRC activities? Key research gaps? Roadmaps of functional requirements, technology showstoppersRoadmaps of functional requirements, technology showstoppers

Roadmapping: PED and ReliabilityRoadmapping: PED and Reliability Design Infrastructure: OpenAccess data model and extensions; mini-flows and Design Infrastructure: OpenAccess data model and extensions; mini-flows and

benchmarking (placement focus)benchmarking (placement focus) Today 10:30 – noonToday 10:30 – noon (joint with PED and Reliability) (joint with PED and Reliability)

CLC SIP and MSP, Radar-on-Chip Driver (Dai)CLC SIP and MSP, Radar-on-Chip Driver (Dai) PicoRadio (PicoNode) Driver (Rabaey)PicoRadio (PicoNode) Driver (Rabaey)

Today 1:00 – 2:30 pmToday 1:00 – 2:30 pm Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming sessionHome Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session

Today 3:00 – 4:00 pmToday 3:00 – 4:00 pm Roles of Drivers in new GSRCRoles of Drivers in new GSRC

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Driver DiscussionsDriver Discussions Which ones? Which ones? How do they unify GSRC activities? How do they unify GSRC activities? Key research gaps? Key research gaps? Roadmaps of functional requirements, technology showstoppersRoadmaps of functional requirements, technology showstoppers Today 10:30 – noonToday 10:30 – noon (joint with PED and Reliability) (joint with PED and Reliability)

CLC SIP and MSP, Radar-on-Chip Driver (Dai)CLC SIP and MSP, Radar-on-Chip Driver (Dai) PicoRadio (PicoNode) Driver (Rabaey)PicoRadio (PicoNode) Driver (Rabaey) MicroLab (alternative space) (Gupta)MicroLab (alternative space) (Gupta)

Today 1:00 – 2:30 pmToday 1:00 – 2:30 pm Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming sessionHome Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session

Today 3:00 – 4:00 pmToday 3:00 – 4:00 pm Roles of Drivers in new GSRCRoles of Drivers in new GSRC

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Driver DiscussionsDriver Discussions A DRIVER IS:A DRIVER IS:

A concrete design for a specific applicationA concrete design for a specific application (Lots of $, very few papers (Lots of $, very few papers ) )

WHAT (D&T) PROBLEM IS THE DRIVER TRYING TO GET US TO WHAT (D&T) PROBLEM IS THE DRIVER TRYING TO GET US TO SOLVE?SOLVE? Continuation of the Moore’s Law for Continuation of the Moore’s Law for COSTCOST ScalabilityScalability of design or its infrastructure of design or its infrastructure ConceptualizationConceptualization (modeling, representation, validation) of systems (modeling, representation, validation) of systems UnreliabilityUnreliability and and UnpredictabilityUnpredictability at component level at component level (Validation should be on this list, but how exactly are the drivers such as Radar-(Validation should be on this list, but how exactly are the drivers such as Radar-

On-Chip driving validation?)On-Chip driving validation?) (Should Power be a first-class citizen?)(Should Power be a first-class citizen?) (N.B.: “Mixed-*” is mostly implicit in Conceptualization)(N.B.: “Mixed-*” is mostly implicit in Conceptualization)

WHAT ARE DELIVERABLES ASSOCIATED WITH A DRIVER?WHAT ARE DELIVERABLES ASSOCIATED WITH A DRIVER? Design data (spec, arch, netlist, implementation, simulation, verification) and Design data (spec, arch, netlist, implementation, simulation, verification) and

hardwarehardware ToolsTools

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Driver DiscussionsDriver Discussions Axes for Drivers:Axes for Drivers:

Metrics: heterogeneity, performance, power, size, reliability/RAS, costMetrics: heterogeneity, performance, power, size, reliability/RAS, cost Impact: Impact: intrinsic value, interestintrinsic value, interest (DARPA? HP/IBM/? Or Bechtel/PGE/?), (DARPA? HP/IBM/? Or Bechtel/PGE/?),

technology leading edgetechnology leading edge Synergy: semiconductor technologies, bridges within GSRC, package, systemSynergy: semiconductor technologies, bridges within GSRC, package, system

System-Level vs. Fabric/Block LevelSystem-Level vs. Fabric/Block Level Application-level vs. implementation-level challengesApplication-level vs. implementation-level challenges Bottom-up super-components (= top-down subsystems) that enable system: are Bottom-up super-components (= top-down subsystems) that enable system: are

these created by GSRC or C2S2?these created by GSRC or C2S2? CandidatesCandidates

BatterylessBatteryless Ambient embedded networked sensing (= proxy for “next-gen”)Ambient embedded networked sensing (= proxy for “next-gen”) PicoNode, LabOnChip, MICA, SmartDustPicoNode, LabOnChip, MICA, SmartDust

High-performance computingHigh-performance computing SIP / stacking: Radar On Chip: STAP DSP + Memory integration, CLC-SIP physical SIP / stacking: Radar On Chip: STAP DSP + Memory integration, CLC-SIP physical

platformplatform General-purpose computing (500 5GHz MIPS cores on chip)General-purpose computing (500 5GHz MIPS cores on chip) Utility computing (data centerUtility computing (data center

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Driver DiscussionsDriver Discussions Drivers + Infrastructure = third dimensionDrivers + Infrastructure = third dimension

Are we picking drivers as a minimum-size cover, or are we picking drivers as Are we picking drivers as a minimum-size cover, or are we picking drivers as “impactful”? Need to bound the goals, scope, … of this discussion“impactful”? Need to bound the goals, scope, … of this discussion

Communication-based, soft systemsCommunication-based, soft systems DFX: Test, Verification, Power, Reliability, … DFX: Test, Verification, Power, Reliability, …

OtherOther LogisticsLogistics

Leveraging (“how we do it now”), not building (rather, “hypothesis testing”)Leveraging (“how we do it now”), not building (rather, “hypothesis testing”) Common access Common access

Need a driver taxonomy + metrics: access/interfacing, heterogeneity, etc.Need a driver taxonomy + metrics: access/interfacing, heterogeneity, etc. Links: OpenGIS.org, Security (SEC Disaster Recovery + Business Continuance), Links: OpenGIS.org, Security (SEC Disaster Recovery + Business Continuance),

Recover-Oriented Computing, …Recover-Oriented Computing, … Home Gateway: How does drive VLSI and IC design?Home Gateway: How does drive VLSI and IC design? What criticality is being overcome by spending $$$ on this driver?What criticality is being overcome by spending $$$ on this driver?

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PD Open Problems (Payman and Amir)PD Open Problems (Payman and Amir) IncrementalIncremental Combined Placement and FloorplanningCombined Placement and Floorplanning

<Clustering cells; Floorplanning clusters+blocks; Placing cells> locks solution <Clustering cells; Floorplanning clusters+blocks; Placing cells> locks solution into a bad subspaceinto a bad subspace

Timing is a constraint (not an objective); WL is an objectiveTiming is a constraint (not an objective); WL is an objective Problem = lack of understanding of interrelationships between different objectives, Problem = lack of understanding of interrelationships between different objectives,

e.g., timing, area (fixed-die) and congestione.g., timing, area (fixed-die) and congestion N.B.: WL may not really be an objective: it is a proxy for congestion (area)N.B.: WL may not really be an objective: it is a proxy for congestion (area)

Issue of capturing timing in top-down partitioning-based placement (partitioning is Issue of capturing timing in top-down partitioning-based placement (partitioning is net-based; timing is path-based)net-based; timing is path-based)

How is SI solved at placement?How is SI solved at placement? IR drop placement? IR drop has impact on timing and reliability and IR drop placement? IR drop has impact on timing and reliability and

hence importanthence important Variability-aware placement?Variability-aware placement?

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PD Open Problems (Payman and Amir)PD Open Problems (Payman and Amir) Thermal placement (not just dynamic power minimization)Thermal placement (not just dynamic power minimization)

Given activities of all gates, find a placement to minimize a linear combination of Given activities of all gates, find a placement to minimize a linear combination of dynamic power and maximum thermal variationdynamic power and maximum thermal variation

Hierarchy?Hierarchy? Probably moving to Probably moving to

Datapath-based (timing-constrained) placementDatapath-based (timing-constrained) placement People have tried but have not achieved notably better resultsPeople have tried but have not achieved notably better results 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism, 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism,

Odawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extractionOdawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extraction

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PD Open Problems (Payman and Amir)PD Open Problems (Payman and Amir) Power implications (voltage islands)Power implications (voltage islands)

Chuck also mentions thisChuck also mentions this Clock gatingClock gating Multi-Vdd islands: granularity of several hundred cells (?) – 1-2 rows min in V, stripe pitch min in HMulti-Vdd islands: granularity of several hundred cells (?) – 1-2 rows min in V, stripe pitch min in H Ground islands (shutdown of blocks keeping memory partially powered up)Ground islands (shutdown of blocks keeping memory partially powered up) Cf. Amir’s work at Northwestern ~1995Cf. Amir’s work at Northwestern ~1995

Placement for BIST (check with Tim Cheng et al.)Placement for BIST (check with Tim Cheng et al.) Signal Integrity Issues (crosstalk handling at floorplan and placement)Signal Integrity Issues (crosstalk handling at floorplan and placement) Clock distributionClock distribution Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE

HEROES !!! (PhasePhirst!, SCAAM, etc. == next-generation lithography proposals, all of which HEROES !!! (PhasePhirst!, SCAAM, etc. == next-generation lithography proposals, all of which depend on “hyper-resolution” (“2-beam imaging”) depend on “hyper-resolution” (“2-beam imaging”) basically, only one direction and one basically, only one direction and one pitch will print (the layout is a subset of a grating). Goal: C.A.D. people should prove a one-pitch will print (the layout is a subset of a grating). Goal: C.A.D. people should prove a one-time, bounded hit on Moore’s Law (e.g., 30% density) but then scalability of SP&R thereafter.time, bounded hit on Moore’s Law (e.g., 30% density) but then scalability of SP&R thereafter.

X, Y Architectures March 5X, Y Architectures March 5thth EE Design ? EE Design ? Design for VariabilityDesign for Variability Backend Process Optimization Backend Process Optimization

Complex objective: Complex objective: marketingmarketing, methodology, integration, methodology, integration Marketing: BEOL should be optimized for many designs (derivatives, etc.) – range of size, frequency, Marketing: BEOL should be optimized for many designs (derivatives, etc.) – range of size, frequency,

etc.etc. Methodology: Crosstalk, IR drop, routing density, etc. Methodology: Crosstalk, IR drop, routing density, etc.

Statistical information : %WL per layer, %designs having X #gates, Y MHz, Statistical information : %WL per layer, %designs having X #gates, Y MHz, Integration: cost of fabrication (e.g., AR limits, low metal-layer count, #layers, thickness (mfg Integration: cost of fabrication (e.g., AR limits, low metal-layer count, #layers, thickness (mfg

throughput, pitch LBs from AR limits, …))throughput, pitch LBs from AR limits, …))

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Working SessionsWorking Sessions FridayFriday parallel session #1: Roadmapping parallel session #1: Roadmapping

9:00 – 11:00am (joint with PED and Reliability)9:00 – 11:00am (joint with PED and Reliability) Background (Energy, Reliability, Variability)Background (Energy, Reliability, Variability) Panel: PED Roadmapping Needs and Research GapsPanel: PED Roadmapping Needs and Research Gaps 11:00am – noon11:00am – noon Roadmapping of Process Variability, Cost OptimizationsRoadmapping of Process Variability, Cost Optimizations

FridayFriday parallel session #2: Infrastructure, Benchmarking parallel session #2: Infrastructure, Benchmarking 9:00 – 10:00am9:00 – 10:00am BX and Benchmarking StatusBX and Benchmarking Status 10:00am – 11:00am10:00am – 11:00am Placement-Centered Directions (Mini-Flows, New Problems)Placement-Centered Directions (Mini-Flows, New Problems) 11:00am – noon11:00am – noon Concrete steps with OpenAccessConcrete steps with OpenAccess

Friday 1:30 – 2:30pmFriday 1:30 – 2:30pm Discussion of C.A.D. Roles in the “New GSRC”: collaborations, projects, Discussion of C.A.D. Roles in the “New GSRC”: collaborations, projects,

milestonesmilestones