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12/04/20133 Delay Chip Features (1/3) –QFN48 Package. –4 DLL Channels (12 sub-channels). –Jitter: 4 ps. –DNL: 18 ps. –Delay Range: ~ ns. –~280 mW power consumption. –70 mW per DLL Channel. –INT/T&H DLL: 27 mW. –ADC DLL: 13 mW. –3 LVDS Drivers: 30 mW.
Citation preview
09/02/2012 1
Delay Chip Prototype&
Delay Chip Test Board
Joan Mauricio – Xavier Ondoño
La Salle (URL)
12/04/2013
12/04/2013 2
Delay Chip Overview
SPI Slave
ResetBlock
Mux
VCDL+Mux
Phase Comp +
Charge PumpConfig Status
VCDL+MuxConfig
rst
nRst
coarse
coarse vControl
clkRef
clkINT<3:0>
clkT&H<3:0>
clkADC<3:0>
vControl<3:0>
Analog Config.
Digital Config.
Diff. LVDS Clock
Diff.CMOS Clock
Slow Control
!en, clk din, dout
nRst
nRst
powRstIn
powRstOut(externally shorted)
vRef···
12/04/2013 3
Delay Chip Features (1/3)
– QFN48 Package.
– 4 DLL Channels (12 sub-channels).– Jitter: 4 ps.– DNL: 18 ps.– Delay Range: 17.45 ~ 39.88 ns.
– ~280 mW power consumption.– 70 mW per DLL Channel.
– INT/T&H DLL: 27 mW.– ADC DLL: 13 mW.– 3 LVDS Drivers: 30 mW.
12/04/2013 4
Delay Chip Features (2/3)
– Each DLL channel contains:– 1 x LVDS to CMOS driver.– 2 x VCDLs.– 3 x Multiplexors.– 1 x Phase Comparator.– 1 x Charge Pump.– 2 x Configuration Registers.– 1 x Status Register– 3 x CMOS to LVDS driver.
12/04/2013 5
Delay Chip Features (3/3)
– SPI Slave:– Interfaces with SPI Master (Mode 1).– Works fine @ 20 Mbps.– Up to 32 Configuration registers and 32 Status Registers.– Also implements a software reset (used to clear the charge pumps).
– Serial Registers:– 16 Bits R/W TMR Registers (Configuration).– 8 Bits RO (Status). No memory.
– Reset:– Power Reset signal (1-ms-wide, active high) is generated.– Power Reset can be inhibited by not shorting pins 47 and 48.– Glitch supressor ensures that SETs do not accidentally reset the chip (up to
8-ns-wide glitch).
12/04/2013 6
Power Reset & Glitch Supressor
12/04/2013 7
SPI Slave Addressing Scheme
ADDR ICECAL Ch Width (bits) Description0x00 0 16 Integrator / Track&Hold Clock Configuration Register.0x01 0 16 ADC Clock Configuration Register.0x02 1 16 Integrator / Track&Hold Clock Configuration Register.0x03 1 16 ADC Clock Configuration Register.···0x10 2 16 Integrator / Track&Hold Clock Configuration Register.0x11 2 16 ADC Clock Configuration Register.0x12 3 16 Integrator / Track&Hold Clock Configuration Register.0x13 3 16 ADC Clock Configuration Register.···0x40 Any - Software Reset of the Charge Pumps.···0xA0 0 8 Status Register.0xA1 1 8 Status Register.0xB0 2 8 Status Register.0xB1 3 8 Status Register.···0xFF - - SDI / SDO Bypass. For testing purposes.
b7 b6 b5 b4 b3 b2 b1 b0
R/!W Pump Rst Status/!Conf RSEL4 RSEL3 RSEL2 RSEL1 RSEL0
– Integrator / Track & Hold Clock Configuration Registers (default 0x9E00):
– ADC Clock Configuration Registers (default 0x9E00):
– CE : LVDS Output Clock Enable. If 0, outputs are tri-stated (default = ‘1’).– ϕT&H : Track & Hold Clock phase. MSB = b13 (default = 0xF).
– ϕINT : Integrator Clock phase. MSB = b8 (default = 0x0).
– ϕADC : ADC Clock phase. MSB = b13 (default = 0xF).
– VCE : Enables Voltage Control monitors 0~3 (default = ‘0’).– DEB : Internal pads Output Enable (default = ‘0’). *Only available in SPI @ = 2. – LOCUS: LVDS Output Current Selector (default = ‘00’).
‘00’: 3.0 mA. ‘10’: 2.3 mA. ’01’: 1.4 mA. ‘11’: .35 mA.
12/04/2013 8
SPI Slave Configuration Data Frames
b15 b14 b13..9 b8..4 b3 b2 b1..0
CE - ϕT&H ϕINT VCE DEB* LOCUS
b15 b14 b13..9 b8..4 b3 b2 b1..0
CE - ϕADC - - - LOCUS
– DLL Status Registers:
– ESLOW : Error: VCDL is too slow. DNL > 0.– LOCKED : DLL is locked.
– WFAST : Warning: VCNTi is near to cut VCDL NMOS transistors.
12/04/2013 9
SPI Slave Status Data Frame
b7 b6 b5 b4..0
ESLOW LOCKED WFAST 00000
TEST BOARD…
09/02/2012
– Main features:– Mechanically compatible with the analog mezzanine.– Clock signals will be tested with probes.– Requires 5 FPGA wires (2 SPI Masters).– It also can work in standalone mode (USB SPI).– Coarse voltage:
– Resistive Voltage Divider.– Low cost SPI DAC.
12/04/2013 11
Delay Chip Test Board Schematics
BACKUP…
09/02/2012
12/04/2013 13
Delay Chip Pinout (1/3)
CK
T&H
<0>
QFN-48
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
35
34
13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 3747 46 45
SP
IDIN
SP
ICLK
SP
IEN
SP
IDO
UT
VS
S
VD
D
VD
D
CK
INT<
3>
CK
INT<
3>
CK
T&H
<3>
CK
T&H
<3>
PW
RS
TO
PW
RS
TI
RS
T
CO
AR
SE
VS
S
VD
D
VS
S
CK
T&H
<0>
CK
INT<
0>
CK
INT<
0>
CKT&H<1>
CKINT<1>
CKINT<1>
VCNT<1>
VDD
VSS
VCNT<2>
CKINT<2>
CKINT<2>
CKT&H<2>
CKT&H<2>1223 24
36 CKT&H<1>48
VC
NT<
0>
VC
NT<
3>
CKADC<0>
CKADC<0>
CKADC<1>
CKADC<1>
VSS
VDD
CLKREF
CKADC<2>
CKADC<2>
CKADC<3>
CKADC<3>
CLKREF
Control Voltages
Power / Ground
LVDS Clocks
Slow Control (SPI)
15/02/2013 14
Delay Chip Pinout (2/3)
Pin No. Mnemonic Description1 CKADC<0> Positive LVDS Clock Output pin to Channel 0 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
2 CKADC<0> Negative LVDS Clock Output pin to Channel 0 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
3 CKADC<1> Negative LVDS Clock Output pin to Channel 1 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
4 CKADC<1> Positive LVDS Clock Output pin to Channel 1 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
5 CLKREF Positive LVDS Clock Input pin. VCM = 1.2 V. VDIFF = 400 mV (rT = 100Ω).
6 VSS Ground.
7 VDD Supply Voltage (3.3 V).
8 CLKREF Negative LVDS Clock Input pin. VCM = 1.2 V. VDIFF = 400 mV (rT = 100Ω).
9 CKADC<2> Positive LVDS Clock Output pin to Channel 2 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
10 CKADC<2> Negative LVDS Clock Output pin to Channel 2 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
11 CKADC<3> Negative LVDS Clock Output pin to Channel 3 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
12 CKADC<3> Positive LVDS Clock Output pin to Channel 3 ADC. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
13 SPIDIN SPI Data Input.
14 SPICLK SPI Clock.
15 SPIEN SPI Enable. Active low.
16 SPIDOUT SPI Data Out. Open drain.
17 VCNT<3> DLL Channel 3 Control Voltage monitor.
18 VSS Ground.
19 VDD Supply Voltage (3.3 V).
20 VDD Supply Voltage (3.3 V).
21 CKINT<3> Positive LVDS Clock Output pin to Channel 3 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
22 CKINT<3> Negative LVDS Clock Output pin to Channel 3 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
23 CKT&H<3> Positive LVDS Clock Output pin to Channel 3 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
24 CKT&H<3> Negative LVDS Clock Output pin to Channel 3 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
15/02/2013 15
Delay Chip Pinout (3/3)
Pin No. Mnemonic Description25 CKT&H<2> Positive LVDS Clock Output pin to Channel 2 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
26 CKT&H<2> Negative LVDS Clock Output pin to Channel 2 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
27 CKINT<2> Positive LVDS Clock Output pin to Channel 2 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
28 CKINT<2> Negative LVDS Clock Output pin to Channel 2 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
29 VCNT<2> DLL Channel 2 Control Voltage monitor.
30 VSS Ground.
31 VDD Supply Voltage (3.3 V).
32 VCNT<1> DLL Channel 1 Control Voltage monitor.
33 CKINT<1> Negative LVDS Clock Output pin to Channel 1 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
34 CKINT<1> Positive LVDS Clock Output pin to Channel 1 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
35 CKT&H<1> Negative LVDS Clock Output pin to Channel 1 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
36 CKT&H<1> Positive LVDS Clock Output pin to Channel 1 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
37 CKINT<0> Negative LVDS Clock Output pin to Channel 0 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
38 CKINT<0> Positive LVDS Clock Output pin to Channel 0 Integrator block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
39 CKT&H<0> Negative LVDS Clock Output pin to Channel 0 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
40 CKT&H<0> Positive LVDS Clock Output pin to Channel 0 Track & Hold block. VCM = 1.2 V. VDIFF = 300 mV (rT = 100Ω).
41 VCNT<0> DLL Channel 0 Control Voltage monitor.
42 VSS Ground.
43 VDD Supply Voltage (3.3 V).
44 VSS Ground.
45 COARSE DLL Channel 0~3 external Voltage adjust.
46 RST SPI Slave Reset and Memory Preset.
47 PWRSTI Power Reset Input.
48 PWRSTO Power Reset (1.2 ms wide) Output.
• USB RS232:
• RS232 SPI (PIC):
12/04/2013 16
Delay Chip Test Board Schematics
• Coarse (DAC):