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1
Solder Defects for Advanced SMT Manufacturing – Formation
Mechanisms and Troubleshooting
Dr. Ning-Cheng LeeIndium Corporation of America
2
Part 1
Head-In-Pillow and Graping
3
Unwetted SAC387 BGA Joints
4
Head-in-Pillow Types
• Type 1: Excessive Oxide on Ball– The oxide film on solder ball is too thick for solder paste
to break through to coalesce.• Type 2: Excessive Warpage
– Solder solidified already when the BGA ball is brought back in contact with solder dome on pad
• Type 3: Warpage + Excessive Oxidation– Solder still in molten state when solder ball was brought
in contact with solder dome on pad. However, the oxide film prevent the coalescence of two solder bodies.
5
Type 1: Excessive Oxide on Ball
• Symptom A:– The head-in-pillow joints sporadically present among the package
joints. No regular pattern in location can be discerned.• Cause:
– For many ball mounting equipment, the ball was pick up randomly for placement. In the mean time, all balls were constantly shaked and shuffled, hence being oxidized with time.
– Some balls were picked up after a long time on the ball mountingmachine, therefore were excessively oxidized.
– Some solder balls are more prone to oxidize, due to lack of protection from oxidation. The protection may be surface coating or alloy doping.
6
Type 1: Excessive Oxide on Ball
• Cure:– Process
• Change the ball mounting process to first-in-first-out mechanism• Use nitrogen reflow atmosphere to avoid adding more oxide to problem• Reduce preheat/soaking/dwell time & temperature• Print more paste to provide greater flux capacity
– Material• Use ball with more oxidation resistance
– Protective coating on balls– Add dopants in alloy
• Use flux with greater flux capacity• Use flux with greater oxidation barrier capability so that flux self-
consumption by oxidized powder can be minimized (hence more fluxavailable to clean up ball oxide)
7
Type 1: Excessive Oxide on Ball
• Symptom B:– Massive joints showed HIP phenomenon.
• Cause:– Oxidation of solder balls of the components during shipping/storage/handling. – Presence of heavy flux residue can aggravate oxide issue, particularly that of no-
clean flux residue which is to be assembled with WS paste or flux.• Cure:
– Process• Improve shipping/storage/handling condition to minimize oxidation• Introduce flux dipping for BGA prior to placing BGA onto the paste printed.• Use nitrogen reflow atmosphere to avoid adding more oxide to problem• Reduce preheat/soaking/dwell time & temperature• Print more paste volume to provide greater flux capacity
– Material• Avoid to use WS flux to assemble NC-ball mounted BGA• Use flux with greater flux capacity (may suffer tradeoff)• Use flux with greater oxidation barrier capability so that flux self-consumption by
oxidized powder can be minimized (hence more flux available to clean up ball oxide)
8
Vacuum-Transfer Ball Attachment
9
Gravity-Dispensing Ball Attachment
10
Type 2: Excessive Warpage
• Symptom:– HIP joints present at either center or edge of component– Symptom can not be affected by reflow profile or
atmosphere• Cause:
– Some package exhibit excessive warpage at reflow– Solder solidified already when the BGA ball is brought
back in contact with solder dome on pad– Since phase change is the main driver, the symptom
hardly improve when oxidation of solders is lessened by reducing reflow atmosphere oxygen concentration or reflow preheating time
11
Oxygen & Warpage Gap Effect
• Small warp (Nitrogen) – Good joints
• Small warp (Air)– Some opens (oxygen effect)
• Large warp (Air)– All opens (oxygen + gap effect)
12
Type 2: Excessive Warpage
• Cure:– Process
• Reduce the temperature of warped component– Reduce reflow temperature setting– Add heat shield to the specific component (particularly when the
BGA is not a relatively large component on the board)
• Print more paste volume – Allow higher solder dome to reach ball on package after reflow
– Design• Stiffen the package, such as adding more Cu layer in substrate
13
Type 3: Warpage + Excessive Oxidation
• Symptom:– HIP joints present at either center or edge of component– Symptom can be affected by reflow profile or atmosphere
• Cause:– Solder still in molten state when solder ball was brought in
contact with solder dome on pad. However, the oxide film prevent the coalescence of two solder bodies.
– The oxide film may be present on ball or dome. Oxidative environment (time/oxygen concentration/temperature) can aggravate the symptom.
– Symptom & cause similar to HIP at SMT assembly
PCB
leadsolder
14
Type 3: Warpage + Excessive Oxidation
• Cure:– Warpage
• Approaches used for Type 2 to reduce the impact of warpage – Oxidation
• Process:– Use reducing atmosphere (reduce oxygen concentration)– Reduce preheat/soaking/dwell time & temperature– Dip BGA balls in tacky flux prior to placement– Print more paste volume
• Material:– Use solder alloy with more oxidation resistance– Use flux with greater oxidation barrier capability– Use flux with greater resistance against burn-off – Use flux with greater flux capacity
15
Soldering Performance vs Oxidation Barrier Capability vs Oxygen Partial Pressure
(for solder paste for a typical SMT print deposit)
0
0.2
0.4
0.6
0.8
1
0.00001 0.0001 0.001 0.01 0.1 1
P (Oxygen Patrial Pressure)
S (S
olde
ring
Perf
orm
ance
)
Air
K=0.5
K=1
K=2
K=5
K=25
S = 1/ (1 + K x P)
K = B0 / BwhereB0 is oxidation barrier capability of a typical RMA flux, B is that of a given flux
P = oxygen partial pressure
Either use nitrogen, or use flux with higher oxidation barrier (for a typical SMT paste print deposit)
oxidation barrier capability
high
low
P. Jaeger and N.-C. Lee, “A Model Study of Low Residue No-Clean Solder Paste”, in Proceeding of Nepcon West, Anaheim, CA, 1992.
16
Flux Fraction Burn-Off and Flux Volume(reflow profile with a peak temperature of 230�C)
y = -0.0707Ln(x) + 0.8191R2 = 0.9892
0.5
0.6
0.7
0.8
0.9
1
0.1 1 10 100
Flux Quantity (mg)
Flux
Fra
ctio
n B
urn-
Off
TGA Study
Heating profile
17
Flux with High Oxidation Barrier Capability
• Prevent problems caused by oxides– HIP– Graping– Non-wetting– Voiding
• Allow manufacture of – Miniaturized devices– Large or thick boards
• Methods for assessing oxidation barrier capability– Tiny Dot Paste Method
• Deposit tiny dot paste, reflow under long, hot soaking profile under air, check for graping
– Ball Onto Paste Method• Use rework machine to assemble BGA, but hold BGA in air while both BGA & paste
going through long hot soaking profile. After solder become molten, place BGA at every 20 sec interval until solder reaching solidification. Check each case for HIP.
• The BGA used in above method can be replaced with a single solder ball. Check for complete coalescence.
– To facilitate handling, the balls can first go through reflow profile alone on a ceramic coupon to build up oxide. The post reflowed ball is then placed on molten solder paste on pad at specified intervals.
18
Oxidation Barrier Capability Assessment(Tiny Dot Paste Method)
• Test pattern design– Circular pads with the following NSMD OSP pad/pitch dimension
• 245 � / 600 �• 325 � / 800 �• 406 � /1000 �
– Stencil with 127 � thickness, and opening the same as pad dimension
• Test Procedure– Print solder paste onto pads– Reflow through SS (short soaking) and LS (long soaking) profiles under air (see
next slide)– Examine under microscope for graping performance
• LS profile with smaller deposit is more vulnerable toward graping/HIP• The graping symptom of pastes can be ranked accordingly. • The one with least graping is also the one most resistant
toward HIP
19
Reflow Profiles for Oxidation Barrier Capability Test(Tiny Dot Paste Method)
Short Soaking
Long Soaking
240C@ 3.3 min
260C@ 5.0 min
2020
Oxidation Barrier Capability Examples
A B C D 8.9 family (8.9HF here)
E F G H J
21
Oxidation Barrier Capability Assessment (Ball Onto Paste Method)
22
Part 2
Voiding in SMT
23
Voiding Mechanism
• Voiding is mainly attributable to the flux outgassing within the solder joints when the solder is at molten state– vaporization or thermal decomposition of
flux ingredients– reaction products formed due to fluxing
reaction. • During reflow, the outgassing forms
"bubbles" in the molten solder. The bubbles intermittently form and then pop open when the bubbles either grow too large or migrate to the edge of joint. Upon solidification, those remaining bubbles are frozen as voids.
• Increase in void content is accompanied by an increase in fraction of large voids.
• Caused by materials, processes, and designs
24
Materials - Fluxes
• Outgassing– Low outgassing rate at temperature > melting
temperature of solder critical, not the accumulated outgassing quantity
– Epoxy flux attractive
25
Materials - Fluxes
• Flux Activity– Entrapped flux cause
trouble– High flux activity or better
solderability prevent flux from being entrapped
– For Pb-free soldering, flux activity override outgassing factor
26
Materials - Solders
• Location of Voids in BGA Joints– Occur at interface at either bottom or
top
– Due to minimizing bubble surface area molten solder
anchoredbubble
floatingbubble
BGA substrate
substrate/bubble interface
BGA
X
27
Materials - Solders
• Solder Reaction with Base Metal– Solder which is prone to react with base
metal and forming intermetallics accelerates mixing between base metal and solder at atomic level.
– This facilitates solder wetting and consequently reduces voiding.
28
Materials - Solders
• Surface Tension– Primary factor - low surface tension of solder & flux allow
solder spread easier, hence cause less voiding
– Secondary factor – low solder surface tension allow development of larger void
y = 387.51x - 192.14R2 = 0.9563
0
10
20
30
40
0.5 0.52 0.54 0.56 0.58 0.6
Surface Tension (N/m)
Void
ing
(are
a %
)
(overridden by primary factor)
29
Materials - Solders
• Melting Sequence– Lower melting at top cause more voiding, due to
gravity effect
30
Materials - Solders
• Oxides– Immobilized oxides (on solid base) cause more
voiding than mobilized oxides due to flux anchored on spots
– Therefore, oxides on pads, components, and high melting solder bumps are more prone to cause voiding.
31
Materials - Solders
• Solder Paste Metal Load– The void content increases with increasing metal content of solder paste – Partly due to an increase in solder powder oxide, partly due to an
increasing difficulty for flux to escape due to tighter powder packing and the formation of a greater amount of high viscosity metal salt.
• Solder Powder Size– Voiding increases with decreasing powder size– Due to the increasing oxide content of the powder associated with
decreasing powder size.
0.00%
0.20%
0.40%
-200
/+3
25
-325
/+5
00
-400
/+5
00
-500
Powder Size (mesh)Vo
id C
onte
nt (%
)
32
Materials - Solders
• Flux Print Thickness– A thicker flux print deposition results in less voiding– Since thicker print provides a higher flux capacity to
eliminate the oxides and a higher joint standoff easier for bubbles to escape, and consequently results in less voiding
0.00%
0.02%
0.04%
6 8 10
Flux Deposition Thickness (mil)
Void
(%)
33
Materials – Surface Finishes
• Wettability– The effect of surface finish on voiding is mainly related to
the wettability, with better wettability resultant in less voiding.
– In general, the voiding behavior of surface finishes can be roughly ranked as below: OSP (worst) < non-noble metal < noble metal (best).
– Improvement in wettability is more effective in reducing voiding than increase in flux activity
34
Materials – Surface Finishes
• Intermetallics– Voiding can also be formed if excessive intermetallics is developed
at reflow. The large quantity of intermetallics particles may bescattered within the liquid solder during reflow. This will result in a viscous liquid, and consequently cause severe voiding due to a sluggish flow of liquid solder.
35
Materials – Surface Finishes
• Outgassing of Immersion Ag
– When soldering onto immersion Ag, occasionally many small voids may be seen on top of intermetallics layer.
– The immersion Ag may have organic inclusion up to around 30% by volume. When the immersion Ag is plated properly as a thin layer of about 0.2 micron in thickness, Ag leached into solder in fraction of second, and no organic can remain within solder joints.
– However, if the immersion Ag layer is thick, it may not dissolve into solder completely, and the organic inclusion in the remaining Ag layer will thermally decompose and outgas during soldering and cause micro-voiding.
0.0
20.0
40.0
60.0
80.0
100.0
0.4 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
microinches
Ato
mic
%
Silver
Organic
Copper
36
Materials – Parts
• Outgassing of Parts– Voiding can also be caused by the outgassing of components or
boards. – For instance, if the BGA pad is a solder mask defined pad,
outgassing from components or boards may emit volatiles into the liquid solder joint through the interface between solder mask and pad.
– Also, if the through-hole via is not plated properly, pin-holes may exist on the copper barrel, and the volatile from board may emit into the liquid solder through the pin-holes and cause voiding.
37
Designs – Large Coverage Area• Voiding increases with increasing
coverage area under the lead of the joint - due to the difficulty in venting the outgas.
• Designing an efficient venting channel within the solder paste layer or solder layer most effective way of preventing voiding.
• Dividing the large pad into multiple small quadrants. If not possible, adding solder mask dividing lines on top of the large pad will also help.
• Dividing aperture into small quadrants can also be helpful, although less effective.
38
Designs – NSMD Pad
• A solder mask defined pad has a greater potential to form voiding caused by outgassing of parts. Changing the pad design to non-solder mask defined pad will help in reducing the voiding.
39
Designs – Microvia
• Microvia poses challenge in voiding control, due to the presence of dead corner in the via. Flux entrapped in the dead corner often causes serious voiding by outgassing.
40
Designs – Microvia• Size
– Void size at microvia increase with increasing inner diameter of microvia – due to the presence of more dead corner
• Shape– Select the adequate microvia technology to avoid the
pocket-shaped microvia.
6-mil Microvia (Vendor B)4-mil Microvia (Vendor B)
41
Designs – Microvia
• Location– By moving the microvia away from the center
of pad, the voiding declines rapidly.
42
Designs – Microvia
• Plug– Since dead corner is the root cause of voiding at microvia, it
is logical to eliminate this dead corner by plugging the hole. Several requirement for this plugging approach: (1) the plug has to be solderable, (2) no outgassing source get buried under the plug, if the plug is to melt at soldering.
– Although conductive adhesive may be an option, copper plating is actually a better choice, since it can be integrated into the microvia manufacturing process.
43
Process – Reflow Profile
• Reducing the outgassing or improving the wetting or both.
• Outgassing Control – (1) short, cool peak desired, (2) high/long soak temp & low peak temp desired
44
Process – Reflow Profile
• Hot soak temp desired.
VOIDING DATA FOR VARIOUS REFLOW PROFILES ON CENTERED M ICROVIAS
8.9%
27.1%
57.7%
8.2%
24.4%
42.0%
0%
10%
20%
30%
40%
50%
60%
70%
80%
HOT SOAK RTP PROFILE (REF) COOL SOAK
TOTA
L N
UM
BER
OF
VOID
S A
BOVE
3 M
ILS
(%) 0.5mm CSP 0.8mm CSP
45
Process – Reflow Profile
• Short and low peak temp desired.
VOIDING OBSERVED FOR VARIOUS REFLOW PROFILES WITH CENTERED MICROVIAS
17.0%
28.6% 27.1%
35.7%
64.3%
9.4% 9.6%
24.4%
18.8%
57.2%
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
205C PEAK, 30SEC 205C PEAK, 60SEC 215C PEAK, 60SEC (REF) 215C PEAK, 90SEC 225C PEAK, 90SEC
TOTA
L N
UM
BER
OF
VOID
S A
BOVE
3 M
ILS
(%)
0.5mm CSP 0.8mm CSP
46
Process – Reflow Profile
• Wetting Control– In general, wetting improves with increasing fluxing reaction, which in turn
increases with increasing temperature and time.– Profile with a high temperature and a long time will be desirable.
0
1
2
3
4
0.0018 0.002 0.0022 0.0024
1/T (deg K)
Ln S
(sec
onds
)
F1
F2
F3
F4
240C210C
180C150C
47
Process – Reflow Profile
• Wetting Control– However, flux ingredients
normally gradually dry out with increasing heat input.
– Oxidation also increases with increasing temperature and time.
– Optimal profile should be a balanced one based on both considerations.
48 INDIUM CORPORATION CONFIDENTIAL
Part 3
Voiding of QFN
Background (1)
• Patterned solder paste common approach– Multiple opens– 50-80% coverage– 0.15-0.3 mm spacing– But, still has voiding issue
• Permanent venting channel desired– Higher discontinuity may be acceptable, since
50% voiding acceptable– Controlled even distribution of discontinuity
better
49 INDIUM CORPORATION CONFIDENTIAL
50 INDIUM CORPORATION CONFIDENTIAL
Background (2)
• QFN prevailing due to (1) small size & light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology.
• Voiding is issue at SMT assembly due to the large coverage area, large number of thermal via, and low standoff.
• Both design and process were studied for minimizing and controlling the voiding.
Parameters Studied
Parameter Sub parameter Layers
Thermal Pad on PCB
Thermal via number 0, 16, 32, 36Peripheral venting for full thermal pad
With and without
Dividing method Solder mask, venting channel (0.22 & 0.33 mm)
Thermal sub-pad shape Square, triangleThermal sub-pad number 1, 4, 8, 9
Stencil Aperture 85%, 100%
Heat HistoryReflow profile Short, long cool, long, long
hotOther heat treatment Prebake, 1 reflow, 2 reflow
51 INDIUM CORPORATION CONFIDENTIAL
QFN with 68 pads, 10mm x 10mm, 0.5mm pitch, daisy-chained, Sn surface finish.
Design of Thermal Pads on Test Board
52 INDIUM CORPORATION CONFIDENTIAL
Voiding Examples
53 INDIUM CORPORATION CONFIDENTIAL
0.22 mm
0.33 mm
The drastic difference in voiding behavior between the two sets demonstrates the tremendous impact of design and process conditions.
Definition of 3 Voiding Properties
54 INDIUM CORPORATION CONFIDENTIAL
Property DefinitionDiscontinuity Percentage of area under the
QFN thermal pad where the vertical metal continuity from QFN to PCB surface is interrupted
Void Average Average of multiple QFNs for void area percentage within the metallic pad of QFN
Largest Void The largest void measured for a category of QFN joints
Individual Voiding Data Set
55 INDIUM CORPORATION CONFIDENTIAL
Dividing the thermal pads into sub-units results in an abrupt drop in the largest void but an increase in discontinuity.
Net effect: a reduction in the uncontrollable, harmful large voids, replacing it with a controlled, even distribution of discontinuity.
Dividing Desired for High Via No.
56 INDIUM CORPORATION CONFIDENTIAL
When the thermal via number is high, the discontinuity of a full pad becomes comparable with that of a divided pad, and the sporadic occurrence of largevoids becomes a distinct disadvantage of the full pad design
36 363636
Thermal Via Aggravate Voiding
57 INDIUM CORPORATION CONFIDENTIAL
Propensity of voids at the via locations is particularly high for full pad solder joints
Thus, voiding increase w increasing via no.
If high via no. is needed, plugging the via is the best option.
Divided Pads with Peripheral Via Not Sensitive to Via No. on Voiding
58 INDIUM CORPORATION CONFIDENTIAL
The number of thermal via bears no relation with voiding for divided pads. This is attributed to the peripheral location of thermal via for those divided pads. If plugging the thermal via is not an option, design the thermal via at peripheral locations whenever possible.
16 36
16 36
16 36
16 36
Increase Channel Width Has No Effect on Void Ave, but Increase Channel Area & Discontinuity
59 INDIUM CORPORATION CONFIDENTIAL
Calculated Venting Accessability of Thermal Pad Designs
Thermal pad design
Venting accessability
Full pad 4Square 4 8Triangle 4 9.66Square 9 12Triangle 8 13.66
60 INDIUM CORPORATION CONFIDENTIAL
Venting Accessability: Perimeter length per unit area of metal pad
Venting Accessability Effect on Largest Void & Void Average
61 INDIUM CORPORATION CONFIDENTIAL
With increasing venting accessability, the void average and largest void decrease readily.
Divided Thermal Pads- SMD vs Channel (NSMD)
62 INDIUM CORPORATION CONFIDENTIAL
The higher voiding of channel system (NSMD) is attributed to (1) thinner solder joint, (2) FR4 outgassing
Effect of Profile on Voiding
63 INDIUM CORPORATION CONFIDENTIAL
The short profile is preferred for a low void average, while the long hot profile is better for reducing the largest void
Conclusion (1)
• Plugging is most effective in reducing voiding. • For unplugged via situations, a full thermal pad is desired
for a low no. of via. • For a high no. of thermal via, a divided thermal pad is
preferred, due to better venting capability. • Placement of thermal via at the perimeter lessens voiding
caused by via. • A wider venting channel has a negligible effect on voiding,
but reduces joint continuity. • For a divided thermal pad, a SMD system is more favorable
than a channel (NSMD) system, with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing.
64 INDIUM CORPORATION CONFIDENTIAL
Conclusion (2)
• Performance of a divided thermal pad is dictated by venting accessability, not by the shape.
• Voiding decreases with increasing venting accessability, although the introduction of a channel area compromises the continuity of the solder joint.
• Reduced solder paste volume causes more voiding.• A short profile and a long hot profile are most promising in
reducing the voiding. • Voiding behavior of the QFN is similar to typical SMT voiding
and increases with pad oxidation and further reflow.
65 INDIUM CORPORATION CONFIDENTIAL
66
Part 4
Microvoiding on ImAg
67
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
Four (4) different LF PCB lots with increasing amounts of planar microvoidsthat reduce the number of temperature cycles the solder joint can survive.
Shows OM top views of PCB Cu surface after shearing ball (L) and an x-sectional view (R) of samples processed without ImAg and exhibited planar microvoid phenomena direct from a Cu (oxide) surface.
68
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
Cross-sectional view at a location where ImAg remained after SMT assembly, because it was not covered with solder paste and did not dissolve during SMT. Cu erosion was observed near the soldermask edge in the form of cavities or “caves.” under ImAg.
Shows an SEM image of a FIB prepared x-section (L), which clearly outlines PCB cave and ImAg roof features as compared to a conventionally prepared metallographic cross-section on the same sample (R).
69
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
Shows a X-sectional illustration of the mechanism from Cu-oxide corrosion of Cu “caves” in the PCB (L) to planar microvoid formation during SMT reflow (R).
70
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
SEM X-sectional image (L) and EDS elemental analysis spectra (R) characterizing the PCB Cu cave feature with an Ag roof and Cu in an oxidized condition prior to SMT assembly.
Shows that an increased cave density (linear density cave length-�m/ length inspected-�m) was found in pre-SMT samples corresponding to increased microvoid (%) found in-parallel to SMT assembled X-sectioned samples.
71
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
72
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
SEM cross section image of a bare PCB with ImAg prior to SMT assembly. Cu cave observed near the soldermask edge, demonstrating the crevice “path” galvanic corrosion mechanism with Cu oxide detected on the cave floor and relatively thin Ag near SM edge.
73
Issues of ImAg
- Etchant Chemistry & Plating Condition Effect
74
Muffadal Mukadam, Norman Armendariz*, Raiyo Aspandiar, Mike Witkowski, Victor Alvarez, Andrew Tong, Betty Phillips, and Gary Long (Intel Corporation), " PLANAR MICROVOIDING IN LEAD-FREE SECOND-LEVEL INTERCONNECT SOLDER JOINTS", SMTAI, September, 2006, Chicago, IL
Peroxide showed microvids. Persulfate no voids.
75Ref: John Swanson and Donald Cullen, " VERIFYING MICROVOID ELIMINATION AND PREVENTION VIA AN OPTIMIZED IMMERSION SILVER PROCESS", APEX, S18-01, Feb. 20-22, 2007, Los Angeles, CA
76
Overplate Ag cause problem - Cu circuit is broken when plating 3 min and more
Ref: Jing Li FANG, Daniel K. Chan, "The Advantages of Mildly Alkaline Immersion Silver as a Final Finish for Solderability", APEX,S23-02, Feb. 20-22, 2007, Los Angeles, CA
Solder mask
Solder mask
77
But, Underplate Ag also cause problem- Cu is found on bottom of blind via after 1 min immersion
Ref: Jing Li FANG, Daniel K. Chan, "The Advantages of Mildly Alkaline Immersion Silver as a Final Finish for Solderability", APEX,S23-02, Feb. 20-22, 2007, Los Angeles, CA
78
Effect of Plating Condition, Etchant Type, Plating Time, PCB Supplier on Microvoiding for (A) Small Microvoids, (B) Large Microvoids, (C) % Solder Joints Inspected with At Least One Microvoid
Ref: Yung-Herng Yau, Karl Wengenroth and Joseph Abys, " A STUDY OF PLANAR MICROVOIDING IN Pb-FREE SOLDER JOINTS“, APEX, S18-02, Feb. 20-22, 2007, Los Angeles, CA
The fast deposition rate from the low pH/high silver concentration bath results in higher microvoid densities, however, these densities can still be well within the desired limits.
79
Part 5
Insufficient Filling of Through-Hole Joints
80Ref: Bala Nandagopal, Sue Teng and Doug Watson, "Effect of OSP Chemistry on the Hole Fill Performance During Pb-free Wave Soldering“, APEX, S08-01, Feb. 20-22, 2007, Los Angeles, CA
Overall, the results indicated that the regular OSP chemistry in Pb-free wave soldering failed to meet the 50% hole fill required per IPC-A-610, for all the conditions studied. The 125mil thick PCB using Pb-free OSP chemistry also failed to meet the IPC requirements for all the conditions evaluated. However, the 93mil thick PCB using Pb-free OSP chemistry was able to meet this 50% hole fill requirement (although not meeting the general 75% minimum requirement needed for class 2 & 3), except when the hole diameter is 16mils larger than the pin.HP Opinion
OSP at Wave Soldering- Summary
IPC-A-610. 7.5.5.1:
50% hole fill allowed for class 1, conditionally for class 2, never allowed for class 3.
For class 2, OK when PTH connected to big heat sink, and solder wetting around barrel wall and pin is even.
81Ref: Jennifer Nguyen, Robert Thalhammer, David Geiger, Harald Fockenberger and Dongkai Shangguan, " Large and Thick Board Lead-Free Wave Soldering Optimization", APEX, S34-01, Feb. 20-22, 2007, Los Angeles, CA,
Greater hole fill desire – adequate flux, more heat input (high preheat temp, long contact time, high pot temp, low belt speed), N2, chip wave on.
82Ref: Jennifer Nguyen, Robert Thalhammer, David Geiger, Harald Fockenberger and Dongkai Shangguan, " Large and Thick Board Lead-Free Wave Soldering Optimization", APEX, S34-01, Feb. 20-22, 2007, Los Angeles, CA,
Low bridging desire – low preheat temp, high contact time, low pot temp, high conveyor speed, chip wave off.
83Ref: Jennifer Nguyen, Robert Thalhammer, David Geiger, Harald Fockenberger and Dongkai Shangguan, " Large and Thick Board Lead-Free Wave Soldering Optimization", APEX, S34-01, Feb. 20-22, 2007, Los Angeles, CA,
84Ref: Jennifer Nguyen, Robert Thalhammer, David Geiger, Harald Fockenberger and Dongkai Shangguan, " Large and Thick Board Lead-Free Wave Soldering Optimization", APEX, S34-01, Feb. 20-22, 2007, Los Angeles, CA,
Low insufficiency desires chip wave on
85Ref: Jennifer Nguyen, Robert Thalhammer, David Geiger, Harald Fockenberger and Dongkai Shangguan, " Large and Thick Board Lead-Free Wave Soldering Optimization", APEX, S34-01, Feb. 20-22, 2007, Los Angeles, CA,
From the left to the right, the P/H area ratios are 0.59, 0.53, 0.46, 0.36 and 0.30 respectively. As can be seen from the picture, the P/H area ratio of 0.59 had a lot of voids, whereas almost no void was seen on the solder joints with P/H ratio of 0.3.
a pin-to-hole area ratio of 0.3-0.4 is recommended to reduce voids
Low voiding desires – small pin to hole area ratio
86
Alternative Criteria
87
Ref: Ernesto Ferrer, Elizabeth Benedetto, Gary Freedman, Francois Billaut, Helen Holder, David Gonzalez, " Reliability of Partially Filled SAC305 Through-Hole Joints", APEX, Anaheim, CA, S29-02, Feb. 5-10, 2006
Pull force governed by pin wetted length.
Alloy type or board thickness has negligible effect.
88Ref: Ernesto Ferrer, Elizabeth Benedetto, Gary Freedman, Francois Billaut, Helen Holder, David Gonzalez, " Reliability of Partially Filled SAC305 Through-Hole Joints", APEX, Anaheim, CA, S29-02, Feb. 5-10, 2006
Pull force governed by pin wetted length. Stress condition has only a minor effect.
89Ref: Ernesto Ferrer, Elizabeth Benedetto, Gary Freedman, Francois Billaut, Helen Holder, David Gonzalez, " Reliability of Partially Filled SAC305 Through-Hole Joints", APEX, Anaheim, CA, S29-02, Feb. 5-10, 2006
90Ref: Ernesto Ferrer, Elizabeth Benedetto, Gary Freedman, Francois Billaut, Helen Holder, David Gonzalez, " Reliability of Partially Filled SAC305 Through-Hole Joints", APEX, Anaheim, CA, S29-02, Feb. 5-10, 2006
91
Part 6
Fragile BGA Solder Joints
92
Simiply IMC Layer Structure Evolution of Interface with Increasing Cu Conc.
Cu suppress dissolution of Ni. Hence, Ni3(P,Sn) disappear first, followed by NiPSn. But it also promotes more IMC formation on PCB (Ni) side & nucleation of Ag3Sn plates.
Cu (die side)
Ni (PCB side)
SAC
0, 0.5
0% Cu
0.5, 2
1
(Ni,Cu)3Sn4NiPSn (500 nm)Ni3(P,Sn) (300 nm)
Ni (3.84 um)
SnAg
(Cu, Ni)6Sn5
Cu
NiSnP + Ni3(P,Sn) (250 nm) (Cu, Ni)6Sn5 (2.8 um)
(Cu, Ni)6Sn5 (2.7 um)
Cu
SAC305
Ni (4.68 um)
NiSnP (240 nm)(Cu, Ni)6Sn5
(Cu, Ni)6Sn5
Cu
SAC3010
Ni
(Cu, Ni)6Sn5
(Cu, Ni)6Sn5
Cu
SAC3020
Ni
Cu conc.
Crack location
High Cu result in more ductile failure (bulk solder) than brittle failure (IMC interface)
No Ag3Sn plates in any locations of the solder joints for the 0.0Cu and 0.5Cu at time zero
High Cu lead to flourishing growth of Cu-Sn IMCs, which promotes the growth of Ag3Sn platelets.
Ref: Henry Y. Lu, Haluk Balkan, Joan Vrtis, and K.Y. Simon Ng, " Impact of Cu Content on the Sn-Ag-Cu Interconnects", 55th ECTC, P.113-119, May 31-June 3, 2005
93
Mean values of drop test results for as-reflowed and after aging (150�C/4 weeks)
Drop Test Performance (Mean value)
0
10
20
30
40S
n1.1
Ag0
.45C
u0.1
Ge
Sn1
.1A
g0.4
7Cu0
.06N
i
Sn1
.07A
g0.4
7Cu0
.085
Mn
Sn1
.1A
g0.6
4Cu0
.13M
n
Sn1
.13A
g0.6
Cu0
.16M
n
Sn1
.1A
g0.4
5Cu0
.25M
n
Sn1
.07A
g0.5
8Cu0
.037
Ce
Sn1
.09A
g0.4
7Cu0
.12C
e
Sn1
.05A
g0.5
6Cu0
.3B
i
Sn1
.16A
g0.5
Cu0
.08Y
Sn1
.0A
g0.4
9Cu0
.17Y
Sn1
.05A
g0.7
3Cu0
.067
Ti
Sn1
.0A
g0.4
6Cu0
.3B
i0.1
Mn
Sn1
.05A
g0.4
6Cu0
.6B
i0.0
67M
n
Sn1
.19A
g0.4
9Cu0
.4B
i0.0
6Y
Sn1
.15A
g0.4
6Cu0
.8B
i0.0
8Y
Sn1
.05A
g0.6
4Cu0
.2M
n0.0
2Ce
SA
C30
5
SA
c387
SA
C10
5
Sn6
3
No.
of D
rops
to F
ailu
re
As-reflowedAfter aging
Mn
Ce
Bi YTi
Novel Alloys with Reduced Fragility
Mn, Ti, Ce, Bi, Y Improve Drop Test Performance(Indium patent pending)
94
Novel Alloys with Reduced Fragility
SAC + Al + Ni (Indium patent pending)• Addition of Al into SAC alloys reduces the number of hard Ag3Sn and Cu6Sn5 IMC particles, and forms
larger, softer non-stoichiometric AlAg and AlCu particles. This results in a significant reduction in yield strength, and also causes some moderate increase in creep rate.
• For high Ag SAC alloys, adding Al 0.1-0.6% to SAC alloys is most effective in softening, and brings the yield strength down to the level of SAC105 and SAC1505, while the creep rate is still maintained at SAC305 level.
• Addition of Ni results in formation of large (Ni,Cu)3Sn4 IMC particles and loss of Cu6Sn5 particles. This also causes softening of SAC alloys, although to a less extent than that of Al addition.
• For SAC+Al+Ni alloys, the pasty range and liquidus temperature are about 4�C less than that of SAC105 or SAC1505 if the added quantity is less than about 0.6%.
• Thus, new alloys exhibit SAC305 creep rate, SAC105 softness, & lower mp than SAC105.
A l % vs Yie ld S tre n g th (fo r S A C (n )05-X Y, w h e re n = 3 .8 -4)
0
1000
2000
3000
4000
5000
6000
7000
0 0 .5 1 1 .5 2 2 .5
A l %
Yiel
d St
reng
th (p
si)
Note : A ll Ni � 0 .05% , has no NiA t A g 3 .8 -4 .0% , Ni � 0 .05% , A l reduc es Y S mos t e f f ec tiv e ly a t 0 .1 -0 .6% .
-A ll Ni � 0 .05% , has no NiAl dominant in effect on YS (w & w/o Ni, trends comparable)
A t A g 3 .8 -4 .0% , Ni � 0 .05% , A l reduc esY S mos t e f f ec tiv e ly a t 0 .1 -0 .6% .
YS of SAC105 & 1505
YS of SAC405 & SAC305
Comparison of Various BGA Polymeric Reinforcement
Approaches
95 INDIUM CORPORATION CONFIDENTIAL
Shape After Impact
96 INDIUM CORPORATION CONFIDENTIAL
4.5 ms 7.5 ms 18 ms
Shock wave travel through the board
R. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Failure Mode at Drop Test
97 INDIUM CORPORATION CONFIDENTIAL
BGA (rigid body)
PCB
When shock wave travel through PCB, tension cause rupture.
Failure Modes Summary of BGA at Drop Test
98 INDIUM CORPORATION CONFIDENTIAL 2009
Capillary Flow Underfill
99 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Capillary Flow Underfill – Pro & Con • Pro
– Mature technology– Potential with the highest reinforcement. – Promise reduction in both joint & crater failures
• Con– Requires post reflow underfill dispense, capillary flow &
cure. Cost more time & equipment– May require prebake to avoid voiding if there is delay
prior to underfilling– Reworkability can be issue, including components around
BGA which was flooded by underfill
100 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
No Flow Underfill
101 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
No Flow Underfill – Pro & Con
• Pro– Simple dispense process, no flow needed– Cure during solder paste reflow– Significant reinforcement– Promise reduction in both joint & crater failures– Some are reworkable
• Con– Placement may introduce voids– PCB prebaking may be needed– For large BGA, open & chip drifting or lifting may be resulted due to
earlier gelling of underfill at the hotter perimeter– Solder wetting may be hampered due to premature gelling upon
alternation in reflow profile– No filler allowed
102 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Placement Voids
103 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Corner Bond
104 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Deposition of Corner Bond
105 INDIUM CORPORATION CONFIDENTIALR. Wayne Johnson, Yueli Liu, Guoyun Tian, Shyam Gale, & Pradeep Lall (Auburn University), “Assembly and Drop Test Reliability of Lead Free CSPs”, 2003.
Corner and Edge Bond Dispensing for BGAs, Saturday, September 1, 2007 | SMT Magazine Archive
Corner Bonding – Pro & Con
• Pro– Cure at solder paste reflow process. No additional curing step &
oven needed– Reinforce BGA to some extent. – Less promising for preventing crater failure.– No prebaking needed– Often reworkable
• Con– Premature curing due to altered reflow profile can result in difficulty
of BGA collapse upon reflow– Polymer wicking or smear at placement can interfere with solder
paste reflow– For precision deposition, premium dispensing equipment is needed,
& significant increase in cycle time becomes inevitable
106 INDIUM CORPORATION CONFIDENTIAL
Edge BondEpoxy Film Process
107 INDIUM CORPORATION CONFIDENTIAL107 COCOCOCOC O O COOOO
Dummypads
BGApads
Printpaste
PlaceBGA
Placeepoxyfilm
Reflow
Edge Bond Epoxy Film – Pro & Con• Pro
– No dispensing equipment needed– Cure at solder paste reflow process. No additional curing step &
oven needed– Reinforce BGA to some extent. – Less promising for preventing crater failure– No prebaking needed– Often reworkable
• Con– Need dummy pads designed in on PCB, more reserved space
required around BGA– Film placement may disturb components placed earlier & cause
defects– Epoxy wicking may interfere solder wetting
108 INDIUM CORPORATION CONFIDENTIAL
Edge BondEpoxy Liquid Process
109 INDIUM CORPORATION CONFIDENTIAL
BGApads
Printpaste
PlaceBGA
Dispenseepoxy UV cureReflow
No capillary flow
Edge BondEpoxy Liquid – Pro & Con• Pro
– Fast UV cure, no heat cure needed– Epoxy won’t interfere with soldering– Easy inspection
• Con– One more step dispensing needed. Cycle time is
unacceptable for high volume high throughput production.
– For high performance, premium dispense equipment needed.
– Less promising in preventing crater failure
110 INDIUM CORPORATION CONFIDENTIAL
Epoxy Flux• Process:
– Print SMT paste on PCB, skip CSP footprint area.– Populate SMT components except CSP– Dip CSP into epoxy flux (a special tacky flux) film at epoxy flux stage, then place onto PCB– Reflow
• Benefit:– Much enhanced reliability– Minimal added process step & time (vs underfilling dispense and flow process)– Single pass through oven (rather than additional heating step needed by underfilling)
CSP
CSP
CSPCSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
Epoxy Flux – Pro & Con
• Pro– Only one extra dipping step needed. The simplest process among all
polymer reinforcement approaches.– No solder wetting interference concern– No PCB prebaking needed, due to designed-in venting channel– Significant reinforcement. – Promising reduction in both joint & crater failures– Reworkable– Compatible with assembly of BGA & PoP, including PoP stacking– Compatible with solder paste, thus can tolerate warpage at
soldering.• Con
– Need epoxy flux bed– Larger nozzle size may be needed for pick & place at dipping step
112 INDIUM CORPORATION CONFIDENTIAL
PoP Process
• Flux, solder paste, & epoxy flux can be used for dip transfer of PoP assembly.
• Use of epoxy flux eliminate underfilling
Dip &
Dip &
0.8 mm BGA (10.5 x 13 mm) Using 650-48
• X-ray showed good wetting.• 100% yield with 7 BGA’s• Shear strength
– 650-48: 143 lbs– conventional flux: 113 lbs
• Failure happened on the board (Cu pad peeled off) and so the shear strength value is not reflecting the complete strengthening effect by EF.
• Cross-section showed good wetting and good fillet.
115 INDIUM CORPORATION CONFIDENTIAL
Cross-section: 0.4 mm BGA (10.5 x 13 mm)
• It showed good wetting (top), good fillet (left), typical bump shape (middle), and some EF void (16 out of 25 gaps)
• 650-48
Part 7
Creep Corrosion
Background
• It was discovered that lead-free (LF) products with immersion silver (ImAg) surface finish will creep corrode in high sulfur industrial environments. Thus it was a surprise to the industry when electronics in high sulfur industrial environments would fail rather quickly, some within 4 weeks of being put in service; replacement systems would do the same. Most failures would occur in 2-4 months. HDDs with high-temperature organic solder preservative (HT OSP) surface finish in the same sulfur environments did not show signs of corrosion.
• ImAg failed by dendritic growth of Ag and growth of Cu2S.
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Creep Corrosion
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
• Analysis of creep failures revealed the corrosion product to be fairly resistive, so bridging of two conductors does not cause immediate failure. This is consistent with the findings of Xu et. al. [6] who stated this corrosion product had semiconductor properties.
• It was found that many corrosion failures passed electrical testing upon arrival from the field (termed CND – cannot duplicate). Upon exposure to high humidity, the failure symptom would reoccur. Resistance measurements showed that when exposed to high humidity, the resistance of the corrosion product dropped from over 10 Mohm to below 1 Mohm.
• EDX reveals the corrosion product to be copper sulfide (Cu2S) with a small amount of silver sulfide (Ag2S). Studies have shown that high amounts of Cu2S typically indicate the presence of active sulfur compounds such as elemental sulfur, hydrogen sulfide (H2S), or organic sulfur compounds. Creep appears to begin by growth of dendrites, as shown on a HDD in an early stage of corrosion.
• This is not electric potential driven dendritic growth, as creep takes place equally in all directions and does not require the board to be powered. Rather it appears that Cu2S is being created and dissolved in a thin layer of moisture and precipitates out to form dendrites upon drying of the solution.
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
2Cu2O (s) + 2H2S � 2Cu2S + 2H2O(s)
• The rate of Cu2S growth increases exponentially with increasing relative humidity while Ag2S grows at the same rate regardless of RH
• Galvanic corrosion is the major mechanism for creep corrosion also.
• The full area of silver coverage (cathode) is much larger than the small exposed copper region (anode), thus helping to drive this aggressive galvanic corrosion in the presence of sulfur and moisture.
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Lenora Toscano and Ernest Long (MacDermid), “Creeping Corrosion of PWB Surfaces in Harsh Sulfur Containing Environments”, SMTAI, p.499-507, Orlando, Florida • August 17 -21, 2008
Presence of solder enhances galvanic corrosion. As the distance from a soldered pad to a non-soldered pad is reduced the tendency for creep corrosion to occur increases.
Soldered pads
More creep corroded pads
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
• Case 1• The untreated ImAg boards failed in 2-3 months. The spray treated ImAg boards began failing in
3-4 months. Creep corrosion was visually confirmed on the failing samples.• The OSP and LF HASL boards have been in service for over 10 months without fail.• Case 2• A system with a corrosion inhibiting emitter was included in one of the chassis. This emitter is
designed to outgas a material that deposits onto nearby surfaces and protects them from corrosion.
• Boards examined after 5 weeks, as shown above.
OK
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Corrective Actions• Conformal coating
– Not very effective, particularly under component area• Improve coverage of Ag
– Only allows Ag2S form, thus no failure– Difficult to achieve coverage under the edge of solder mask
• High temp OSP– Narrow process window for soldering & probing
• Lead-free HASL– SnCuNi acceptable on Cu dissolution & planarity. 150C Tg laminate preferred.
• ENIG– Acceptable, unless there is exposed Cu. Higher cost.
• ImSn– Sn is anodic vs Cu, & close in potential, thus no galvanic corrosion. IMC growth a
concern.• PCB design improvement
– Avoid SMD pads. Use round corner pads. Full aperture open for pads. Pads separated by > 2.5 mm.
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Dell’s Move
• Dell has discontinued use of ImAg surface finish on its motherboards for nearly all future lead-free products (changing to HT OSP or LF HASL) to reduce the chance for failure in high sulfur environments.
Randy Schueller (Dell), “CREEP CORROSION ON LEAD-FREE PRINTED CIRCUIT BOARDS IN HIGH SULFUR ENVIRONMENTS”, SMTAI, p.643-654, Orlando, FL, Oct. 7-11, 2007
Conclusion
• Thin PCB surface finishes, primarily designed to preserve surface solderability between fabrication and assembly, are at risk for creep corrosion in harsh, sulfur-bearing environments.
• The formation of creep corrosion is most severely driven by a combination of “enablers”: – an exposed copper substrate, – a bi-metal couple creating a corrosion cell, – airborne sulfur and other corrosive agents, – and the presence of moisture.
• An improved industry test is clearly needed. • A number of promising creep prevention remedies and
strategies have been demonstrated in this work. Lenora Toscano, Ernest Long, and John Swanson (MacDermid), “CREEP CORROSION ON PCB SURFACES: IMPROVEMENTS OF PREDICTIVE TEST METHODS AND DEVELOPMENTS REGARDING PREVENTION TECHNIQUES”, SMTAI, p.634-642, Orlando, FL, Oct. 7-11, 2007