07. Strategies.pdf

Soldering & Surface Mount TechnologyStrategies for improving the reliability of solder joints on power semiconductor devicesGuo-Quan Lu Xingsheng Liu Sihua Wen Jesus Noel Calata John G. Bai

Article information:To cite this document:Guo-Quan Lu Xingsheng Liu Sihua Wen Jesus Noel Calata John G. Bai, (2004),"Strategies for improving the reliability ofsolder joints on power semiconductor devices", Soldering & Surface Mount Technology, Vol. 16 Iss 2 pp. 27 - 40Permanent link to this document:http://dx.doi.org/10.1108/09540910410537309

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Strategies for improving the reliability of solder jointson power semiconductor devices

Guo-Quan LuDepartments of Materials Science and Engineering and Electrical and ComputerEngineering, Virginia Polytechnic Institute and State University, Blacksburg,Virginia, USAXingsheng LiuDepartments of Materials Science and Engineering and Electrical and ComputerEngineering, Virginia Polytechnic Institute and State University, Blacksburg,Virginia, USA (Currently with Corning Inc., Science and Technology Center,Corning, NY, USA)Sihua WenDepartment of Biochemistry and Biophysics, University of Pennsylvania,Philadelphia, Pennsylvania, USAJesus Noel CalataDepartment of Materials Science and Engineering, Virginia Polytechnic Instituteand State University, Blacksburg, Virginia, USAJohn G. BaiDepartment of Materials Science and Engineering, Virginia Polytechnic Instituteand State University, Blacksburg, Virginia, USA

Introduction

Wirebonding remains as the most widely used technology

for interconnecting power semiconductor devices because of

its known reliability and the maturity of the process and

equipment behind it. However, for high-voltage, high-

current applications, concerns have been raised on issues

such as electrical overstressing, large mutual coupling

effects, parasitic oscillations, mechanical damage during

ultrasonic bonding and limitations on heat dissipation due to

its two-dimensional structure (Lall et al., 1997; Wen and Lu,

2000; Xing, 1999). Advances in device technology have

reduced the intrinsic silicon resistance, particularly in low

power devices, down to levels that are now comparable to or

even lower than those conventional packages before a die is

placed within them. Chip-level and module-level packaging

resistances, therefore, currently account for as much as 90

percent of the overall packaged device resistance (Bindra,

2000). Efforts to further reduce resistance have, therefore,

shifted to the device packaging, resulting in the introduction

of various innovative interconnect and packaging

techniques. Some of these have been implemented in

commercial packages. Following the lead of IC

manufacturers, power device makers have begun using

variations of flip chip packaging where interconnection is

attained using solder bumps. Others have gone even further

by adopting large-area interconnections. Some of these

techniques include the Bottomless Flip Chip from Fairchild

Semiconductor (Klein, 2000), CopperStrap (Mannion, 1999)

and DirectFET (Morrison, 2002) from International

Rectifier, and PowerConnect from Vishay Siliconix (Bindra,

2000) to name a few. Interconnect technologies that were

developed at Virginia Tech include a three-dimensional

stacked solder joint interconnection (Liu et al., 2001a, b)

and dimple array interconnect (DAI) (Wen et al., 2001).

These two technologies are the subject of discussion in this

paper.

Stacked solder bump interconnection

Stacked solder bumping is an extension of the wellestablished solder bump technology. It has some importantdifferences from the conventional bumping techniquecommonly used in flip chip packages. It provides the abilityto control the joint height and shape by appropriatemodification of design parameters. It is compatible withsurface mount technology and can be adopted for volumeproduction. The major disadvantage is that it involvesadditional process steps for solder deposition and reflow.The melting temperatures of the solders, bumping processcompatibility, manufacturability and reliability are themajor factors that influence the choice of soldercompositions. Solder composition has a significant influenceon solder joint reliability. Eutectic lead-free solder(Sn-3.5Ag) has excellent characteristics with improvedreliability over eutectic lead-tin (Harada and Satoh, 1990).Because the melting points of the solder alloys vary over arange of temperatures, a temperature hierarchy must bemaintained when selecting the alloy composition for eachlayer in order to preserve the structural integrity of the jointduring each step of the process. For our research, the innercap was made of lead-free Sn-3.5Ag alloy with a meltingtemperature of 2218C. The middle bump is of Pb-10Sn alloywith a melting point of 2688C. The outer cap is eutectic lead-tin (Sn-37Pb) with a melting temperature of 1838C.The height of the triple stacked joint ranged from0.5 to 1.25mm (20-50mil). The power device was aninsulated gate bipolar transistor (IGBT) with 1mm widepads. The middle bump is actually a solder ball that isdropped into the structure during processing. The use ofa solder ball as the middle bump does not pose a technicalhurdle for volume production since solder ball mountingtechnology is mature and automated (Shimokawa et al.,1997, 1998). The composition of the solder ball is also animportant consideration in determining the required reflowtemperatures due to potential alloy reactions that can affectthe standoff height and shape. Compared with lower-power

The Emerald Research Register for this journal is available at The current issue and full text archive of this journal is available at

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KeywordsSoldering, Joining processes,

Stress (materials),

Semiconductor devices

AbstractIn this paper, some strategies

taken to improve the reliability of

solder joints on power devices in

single device and multi-chip

packages are presented. A

strategy for improving solder joint

reliability by adjusting solder joint

geometry, underfilling and

utilization of flexible substrates is

discussed with emphasis on triple-

stacked solder joints that

resemble the shape of an

hourglass. The hourglass shape

relocates the highest inelastic

strain away from the weaker

interface with the chip to the bulk

region of the joint, while the

underfill provides a load transfer

from the joints. Thermal cycling

data show significant

improvements in reliability when

these techniques are used. The

design, testing and finite-element

analyses of an interconnection

structure, termed the Dimple-

Array Interconnect, for improving

the solder joint reliability is also

presented.

Received: 12 September 2003Revised: 13 January 2004

Soldering & Surface MountTechnology16/2 [2004] 2740

q Emerald Group PublishingLimited[ISSN 0954-0911][DOI: 10.1108/09540910410537309]

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devices such as computer microprocessors, the interconnectstructures are large and far smaller in number because theprimary aim is to form reliable large-area interconnects withhigh current-carrying capacity to accommodate the largepower requirements for such devices. In principle, only threeinterconnections (source, drain, gate) are necessary but verywide interconnect areas tend to pose reliability problems,primarily because of the coefficient of thermal expansion(CTE) mismatch between the interconnected structures;hence, a greater number of connections is typically used.

Bumping processThe stacked solder bumping technique consists of threebasic processes: stencil printing, solder ball placement andreflow. In the stencil-printing process, Sn-3.5Ag solder pasteis deposited on the bonding pads by stencil printing.The paste is pre-baked in order to retain its shape for the nextprocess. In the solder ball placement process, a stencil withwindows corresponding to the bond pads is placed on top ofthe chip and high-lead solder balls are dropped through thewindows. Finally, the solder paste is reflowed at a peaktemperature of 2508C, which is above the melting point ofthe paste alloy, but below that of the solder ball. The reflowis done in a nitrogen-hydrogen atmosphere to minimizeoxidation that may cause defects at the interfaces. A devicewith solder bumpsmade by this process is shown in Figure 1.The under bump metallization is Ti/Ni/Ag.

Flip chip assembly processThe triple-stacked solder joint fabrication is completed inthe flip chip assembly process. A photoimageable soldermask is applied to a pre-patterned substrate by screen-printing. The solder mask is then exposed to UV light tocreate openings on the substrate corresponding to thebumped pads on the chip and alignment marks for themounting process. Solder paste (Sn-37Pb) is stencil-printedon the bond pads on the substrate and the bumped die isflipped over and attached to the substrate. The assembly isthen heated to melt the outer solder and form a metallurgicalbond with the bond pad. The reflow is carried out at a peaktemperature of 2108C. The maximum temperature isdictated by the melting point of the solder paste alloy(1838C) and the need to maintain the temperature hierarchyto preserve the structure. After flip chip bonding andcleaning, electrical testing was performed prior tounderfilling of the gap with a high-performance epoxyunderfill. Devices mounted on the substrate by this flip chipprocess prior to underfilling are shown in Figure 2. A cross-sectional view of the triple-stack solder joint obtained with ascanning electron microscope (SEM) is shown in Figure 3.

Reliability testsThe reliability of the solder joints was evaluated using anadhesion test and an accelerated temperature cycling test.A destructive tensile test was performed on both processedand temperature cycled samples to determine the adhesionstrength of different solder joint configurations and to studythe effect of temperature cycling on the adhesion strengthand fracture behavior of the joints. During the acceleratedtemperature cycling test, in situ electrical resistancemeasurements and periodic observations by scanningacoustic microscopy and optical microscopy wereconducted to monitor the condition of the solder joints.The electrical resistance of the solder joints was measuredusing a four-point probe method and was used as the failurecriterion. A 20 percent increase in electrical resistance wasused as the criterion for failure.

The three solder joint configurations in the test samplesare shown in Figure 4. They are single bump barrel-shapedsolder joints, triple-stack barrel-shaped solder joints andtriple-stack hourglass-shaped solder joints. The single bumpsolder joint is made of eutectic lead-tin solder (Sn-37Pb).

Temperature cycling was performed on the samples toassess the resistance and robustness of the package structureto extreme temperatures and to determine the effect of

alternating exposures to these temperatures. The tests wereconducted in an Envirotronics thermal cycling chamber.The test samples were periodically removed from thechamber and tested for integrity using electrical resistancemeasurements.

As shown in Figure 5(a), there are seven solder joints ineach device and each chip was attached to a test vehicle asshown in Figure 5(b). For each type of joint, three sampleswere tested for a total of 21 joints each. The test sampleswere not underfilled. The temperature cycling was carriedout between 240 and 1258C. Heating and cooling rates forboth were 6.68C/min and dwell time was 5min.

Electrical resistance measurementsThe normalized electrical resistance curves for the threetypes of joints are shown in Figures 6-8. The curves can bedivided into three regions, each corresponding to one of thethree fatigue degradation phases, namely crack initiation,crack propagation and catastrophic failure. The crackinitiation phase is characterized by a period of very littleincrease in electrical resistance (,5 percent), while in thecrack propagation phase the electrical resistance increases ata higher rate. The electrical resistance dramaticallyincreases in the catastrophic failure stage. Using a 20percent increase in electrical resistance as the failurecriterion, the fatigue life of a single bump barrel-shapedjoint is approximately 2,200 cycles, while that of a triple-stack barrel-shaped joint is about 3,000 cycles. The average

Figure 1(a) Stacked solder joints on IGBT pads and (b) close-up imageof a stacked solder joint

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Guo-Quan Lu, Xingsheng Liu,Sihua Wen, Jesus Noel Calata andJohn G. BaiStrategies for improving thereliability of solder joints on powersemiconductor devices


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fatigue life of the stacked hourglass-shaped joint is around3,500 cycles which is longer than any of the barrel-shapedjoints. The crack initiation time for the stacked barrel-shaped joints, is roughly the same as that of the single bumpbarrel-shaped joints but the crack propagation time is similarto that of the stacked hourglass-shaped joints.

Imperfections arising from the hand assembly of thesamples and probe traces are to be expected, resulting inminor discrepancies in the measured resistances of some ofthe joints as exhibited by curves in Figures 6 and 7 that seemto be contradictory. However, the average of themeasurements follows the trend discussed above.

The important differences in the three sets of curves areshown in Figure 9. By using stacked hourglass-shapedjoints, the crack initiation time is extended by 30-40 percentover that of barrel-shaped joints, which is a significantimprovement. By using stacked high-standoff solder joints,the crack propagation time is increased by about 100percent. Overall, the average fatigue life of the stackedhourglass joint is longer by about 60 percent over that of thesingle bump barrel joint. The longer fatigue life of thestacked hourglass joint over that of the stacked barrel jointcan be traced to the longer crack initiation time. This in turnis the result of a more favorable shape or geometry. Thus, acombination of high standoff height and hourglass geometrycan significantly improve the reliability of solder joints.Underfilling of the structures resulted in improved reliabilityfor each type of joint. However, the amount of improvementvaried with the type of joint, with the barrel-shaped jointbenefiting the most (Liu, 2001). In the case of the high-standoff stacked hourglass joint, it is already reliable enoughthat the limiting factor is the die-attach layer that tends tofail earlier, thus showing little improvement withunderfilling. On the other hand, the barrel-shaped joints canfail earlier than the die-attach layer such that underfillingcan provide a significant improvement in the joint reliability.

Failure analysis and characterizationWhile the electrical resistance measurements provide thegeneral trends for the effects of joint geometry and height, itdoes not provide a picture of the location, mode andprogression of the joint failure. To monitor the state of thejoints during the course of the temperature cycling tests,scanning acoustic microscopy images of the joints wereobtained. A 75MHz transducer was used for imaging.The series of images obtained at the interface of a singlebump barrel-shaped joint and die (Figure 10) clearly showthe progression of the crack area during the course of the

temperature cycling tests. The dark areas indicateintact bonds while the light areas are cracked or debondedregions. Images were also obtained on the other typesof joints for analysis. As the images show, the crack usually

Figure 4Solder joint configurations used in the test samples: (a) single-bump barrel shape, (b) triple-stack barrel-shape and (c) triple-stack hourglass shape

Figure 3SEM image of a cross-section of a triple-stack solder joint

Figure 2Flip chip on substrate assembly before underfilling of the gap (Note the high standoff height attainable)



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initiates at the corners and edges away from the centre ofthe die, a result that is to be expected when considering thestresses arising from CTE mismatch. A comparison ofthe crack area propagation of the single bump barrel andstacked hourglass joints is shown in Figure 11. The resultsclearly show a faster propagation rate for the single bumpbarrel joint.

Figure 12 shows typical cross sections of joints that failed bythermal fatigue. The majority of the joints failed at thesolder joint-chip pad interface. Only a small fraction of thejoints developed cracks at the corners of the solder joint-substrate interface.

Microcracks occur at points of high localized stress andgradually spread by fracture of the material at the edges of

Figure 5

(a) Dimensions (in mm) and solder joint locations on test chips, and (b) temperature cycling vehicle

Figure 6Electrical resistance vs number of cycles for single-bump barrel-shaped solder joints



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the crack where there is a stress concentration. The timeneeded for microcracks to grow could be affected by thelocal stress, which may help explain why the joint shape isthe dominant factor in determining crack initiation time.Generally, fatigue failure occurs first at the interfacesbetween the solder and die and the solder and substrate dueto high thermal stress concentrations, especially at the

corners (Ho et al., 1995; Lau, 1996; Yu et al., 1998). Finiteelement modeling also showed that an hourglass-shapedjoint will have significantly lower stress at the joint corners(Ho et al., 1995; Su et al., 1998; Yu et al., 1998).Analytically, the stress and strain field near the bond contactedges show singular behavior, which can induceconsiderably larger stress than the nominal stress. It has beenshown that the singularity increases and becomes moresignificant with increasing contact angle (Body, 1952;Williams and Pasadena, 1971). The smaller contact angle ofthe hourglass joint reduces the order of the singularity andmay help explain the longer crack initiation time. Thereduced cross section in the middle of the hourglass-shapedjoints may also induce a greater portion of the deformationto take place, away from the brittle interfaces with the dieand substrate.

The experimental results also point to the standoff heightas the determining factor in the crack propagation time. Thiscan probably be explained by the laws governing the fatiguecrack propagation for stage II growth in a metal. Stage IIgrowth is related to the total strain by a single power lawexpression extending from the elastic to the plastic regime(Dieter, 1976). The effective strain in the solder joint can beexpressed as (Hwang, 1996):

1eff bDaDTah

1where b is the effective factor, Da is the difference in CTE,DT is the temperature change, a is the distance from theneutral expansion point and h is the joint height. Thus, a highjoint standoff height will reduce the effective strain and inturn lower the crack propagation rate.

Effect of flexible substrates on reliabilityThe effect of substrate flexibility on joint reliability wasinvestigated by substituting a flex substrate for the rigidprinted circuit board (PCB) in the fabrication of flip chip testsamples. The solder material for the joint was eutectic lead-tin. Two thermal cycling conditions were used for this partof the study:1 0-1008C, and2 240-1258C.

A comparison of the fatigue life of flip chip on flex (FCOF)and flip chip on PCB board (FCOB) is shown in Figure 13.The results show a significant improvement in the fatiguelife if a flexible substrate is used. Thermo mechanicalanalysis (TMA) of the structure indicate that the flexsubstrate buckles during temperature cycling toaccommodate the displacements brought about by themismatches in CTEs between the various materials. Thus,by providing a mechanism for accommodating temperature-induced distortions, the solder joint deformation is reducedresulting in improved reliability. The situation is similar tothe effect of underfill encapsulant on the flip chip assembly.The underfill forces the substrate (including rigid ones)to bend and thus, reduce the thermal strain on the joints(Lau, 1994).

FE modeling of solder jointsFE modeling of the solder joints was performed in order toshow the effect of solder contact angle on the stressdistribution in the joint structure. The modeling wasconducted using ANSYS. The results shown in Figure 14were obtained using a two-dimensional model representingthe plane passing through the centre of the joints. The jointheight was kept constant for all values of contact angle.The von Mises stress and the resultant shear stress show anincreasing trend with increasing contact angle, i.e. as theshape of the solder joint contact with the die and substratetransitions from the hourglass structure to that of a barrel-shaped joint. The maximum stress occurs at the solder-dieinterface as shown in the inset. A barrel-shaped joint with a458 outer angle will experience a stress roughly 50 percenthigher than an hourglass-shaped joint with a 458 internalangle.

Figure 7Electrical resistance vs number of cycles for stacked barrel-shaped solder joints

Figure 8Electrical resistance vs number of cycles for stacked hourglass-shaped solder joints

Figure 9Average fatigue life of the different solder joint configurations broken down into crack initiation,crack propagation and catastrophic failure component stages



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DAI

The conventional controlled collapse bonding (CCB)process produces barrel-shaped solder joints in which stress/strain concentration is localized at the other edge of thesilicon/solder or substrate/solder interface. Under large CTE

mismatches such as that between copper and silicon inpower modules, the solder joints are prone to early fatiguecracking at the silicon/solder interface. The DAI techniqueprovides the capability of achieving lower switching loss,higher efficiency and better heat dissipation in a three-dimensional structure than the wirebonding technique.Additionally, it can provide improved thermal reliability andperformance over the conventional CCB power devicepackaging method. The DAI technique establishes electricalconnections on the power devices by solder bumps formedbetween the device electrodes and arrays of dimples pre-formed on a metal sheet. The result is a simple, low-profileplanar interconnection suitable for multi layer integrationwith other circuit components. A detailed schematic thestructure of a dimple connection is shown in Figure 15.The connecting solder layer takes the shape of an hourglass,which exhibits a better reliability than a barrel structure.With the exception of the fabrication of the dimpled copper,assembly of the DAI structure follows the typical solderjoint interconnection processes. A detailed description of theassembly procedure can be found elsewhere (Wen, 2002).

Copper is the preferred material in power electronicsbecause of its excellent electrical, physical and mechanicalproperties. However, as a first-level interconnect, the largeCTE mismatch with silicon presents a reliability issue.A first-order estimate of the shear stress (t) and strain (g) inthe solder undergoing a 1008C temperature excursion usingtypical property values are about 153MPa and 0.013,

Figure 10Scanning acoustic microscopy images of the interface between single-bump barrel-shaped joints and die at (a) 1,400 cycles,(b) 1,700 cycles, (c) 2,200 cycles, and (d) 2,400 cycles

Figure 11Average crack area increase during temperature cycling for single-bump barrel-shaped solder jointsand stacked hourglass-shaped solder joints



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respectively. For the Sn-Pb eutectic solder, which yieldsaround 43MPa, tmax is only 21.5MPa. In CCB joints, thesituation is aggravated by the stress concentration at thestructural singularity in the solder joint with the silicon.A stress distribution analysis done as early as 1969 by IBMresearchers (Goldmann, 1969) shows that when the solderjoint is distorted due to CTEmismatch between the substrateand chip, shear stresses are imposed at both ends, togetherwith normal stresses at the corners which must be present formomentum balance to occur. In DAI, the solder is preventedfrom collapsing by the copper dimple and eliminates thestructural singularity at the solder/silicon interface found inCCB joints, thus alleviating the stress concentration andprolonging crack initiation time. Generally, improvementsin area array solder joints can be achieved by increasing theflexibility of the interconnect sheet, increasing the solderjoint height and underfilling the gap. These methods alsoapply to DAI.

Thermal cycling test samples with either DAI or CCBinterconnections were fabricated on a silicon wafer bycreating a solderable UBM pattern. Such samples workperfectly well in simulating actual power devices, since thesamples are not powered up. Dimpled copper sheetsmeasuring 8 10mm with 2 3 dimple-arrays were used toconnect to the conductive traces forming the DAI structure.The joints formed were roughly 1mm in diameter. CCBjoints were created by using plain copper sheets, with thesolder balls forming contacts defined by a solder mask.For power cycling tests, samples were fabricated usingfunctioning power diodes (IXYS DWEP 35-06) measuring6 6mm with solderable UBM on both sides. A squarepattern with a centre joint (total of five joints) were createdon the devices and capped with either dimpled or plaincopper sheets. The details of the test structures, apparatusand test procedures can be found elsewhere (Wen, 2002).

Thermal cycling test resultsThe normalized resistance of the individual solder joints wasused to compare the thermal cycling capability of the CCBand DAI solder joints. The normalized resistance is obtainedby dividing the measured resistance, R, by the zero-cycleresistance, R0. Typical normalized resistance curves areshown in Figure 16 for CCB and dimple interconnections.Most of the CCB joints displayed a drastic resistanceincrease only after 35 cycles from 255 to 1258C whereasthe dimple joints show a much slower rate. In addition, morethan 20 percent of the CCB joints were found to have highzero-cycle resistance although no open joints were found.The results differ significantly from those of conventional(IC) BGA board-level and flip chip interconnections. Failurein those structures occurs after hundreds of cycles. The maincause is the large CTE mismatch between the silicon deviceand the copper interconnect (,13 ppm/K) as opposed to thesmaller CTE mismatch in the BGA (ceramic substrate toPCB board is about 7 ppm/K) or the flip chip package(silicon to ceramic substrate is ,5 ppm/K).

Figure 17 shows a cumulative failure plot, based on afailure criteria of a 20 percent change in resistance, for bothtypes of interconnection. The dimple-array solder joints canbe seen to have a significantly longer lifetime than thecorresponding CCB joints. If this criterion is taken as thetime-to-crack initiation, then the mean time for fatigue crackinitiation for dimple-array solder joints is about 110 cyclesfor this particular test condition, while that for the CCBjoints is around 8 cycles. About 30 percent of the CCB jointsexperienced an open circuit condition after 135 cycles, whileroughly 40 percent of the dimple solder joints experiencedan open circuit after 345 cycles.

FEM modeling of thermal fatigueIn order to correlate FEM modeling with the reliability tests,two cases were studied by FEA modeling: power andtemperature cycling conditions. The details of the modelingprocedure and materials properties used are describedelsewhere (Wen, 2002). Solder materials are complicated to

Figure 12Typical cross sections of thermal fatigue-failed. (a) single-bump barrel shaped solder joints and (b) stacked hourglassshaped solder joints

Figure 13A comparison of the average fatigue life of FCOF and FCOB assemblies during thermal cycling



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model because of their temperature and time-dependentviscoplastic behavior. The field temperature of solder jointsis in the range 0.5-0.8 Tm (melting temperature) such thatcreep is significant and cannot be ignored. The temperaturedependency of the plasticity of solder alloys furthercomplicates the problem. In this study, a constitutive theorydeveloped by Hong and Burrell (Hong, 1998) was used tomodel the solder material. According to this theory, the totalstrain in the solder joint is assumed to be the sum of the

elastic, plastic, creep and thermal strains. The Prandtl-Reussequations are used to describe the elastic-plastic behavior ofsolder. During the course of the study, only the steady-statecreep can be modeled using ABAQUS, for which theGarofalo hyperbolic sine law was used. For the modelingof the thermal cycling test, a uniform temperature loading of255-1258C was used, with the stress-free state selectedbeing the reflow temperature based on the assumptionthat cooling from the liquidus to room temperature tookplace within 60 s. For the modeling of the power cyclingtest, a uniform temperature load of 10-1008C was used,based on the measured temperature at the copperinterconnect.

Thermal cycling modeling resultsA comparison of the von Mises stress distribution for theCCB and dimple samples at 2558C is shown in Figure 18.The copper flex is not shown for clarity and only a quarter ofeach of the models are shown. Because the temperaturecycling samples were not underfilled, the CTE mismatchbetween the copper and the silicon was mostly loaded on thesolder joints, even though the deformation of the copper flexhelps reduce the stresses on the joints. The von Mises stressis the major driving force for the inelastic deformation and isresponsible for the change in shape and distortion of thematerial. It is found that the stresses are highest when thetemperature is at the cold extreme (2558C), which suggeststhat more damage occurs at the cold stage of the temperaturecycling test. The von Mises stress components at theweakest locations (where failures occur) are plotted inFigure 19. The normal stresses (s11, s22, s33) are fairly highfor both interconnects. However, when the normal stressesare close to each other in value, the shear stresses contributethe majority of the yielding of the joints. A comparison of thestrain components further proves this point. In Figure 20, theshear strains are found to be substantially higher inthe weakest points of the CCB joints than in the dimplejoints.

The shear stress-strain hysteresis loops are shown inFigure 21 for both CCB and dimple joints. Shear stresses arenegative for the cold extreme and positive for the hotextreme of the cycle. The shear strains are ratchetingtowards the negative direction of the strain axis with time.Because of the inelastic strain damage (creep and plasticity),the stress/strain cannot fully recover to the starting state ofthe last cycle. The ratcheting curves of the dimple solderjoint are much more stable than those of the CCB solderjoints. The smaller shear strain range of the DAI alsosuggests that temperature cycling causes less damage percycle to the DAI than to the CCB.

Figure 14

Plot of predicted maximum stresses as a function of internal contact angle in a two-dimensional

solder interconnection

Figure 15Schematic of the structure of a single dimple interconnect inthe DAI

Figure 16Normalized resistance (R/R0) vs number of thermal cycles



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Figure 18

Von Mises stress distribution in: (a) CCB model, and (b) DAI model (The chip center is on the upper left corner of the rectangle)

Figure 17

Cumulative failure based on a 20 percent increase in resistance for dimple and CCB Sn-37Pb solder joints



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Power cycling modeling resultsFigure 22 shows a contour plot of the cumulative equivalentplastic strain. After four cycles, the dimple joint(underfilled sample) has the highest accumulativeequivalent plastic strain 5:07 1023 at the centre of thejoint (A), close to the copper/solder interface. This isdifferent from the non-underfilled case where the highestequivalent plastic strain (PEEQ) occurs at the silicon/solderinterface (B). The CCB joint is the weakest at the outercorner of the solder joint (silicon/solder interface) with a

total equivalent plastic strain of 5:24 1023: Theequivalent plastic strain range (accumulation per cycle)differs dramatically between the two types of joints.The dimple joint experiences higher initial equivalentplastic strain and then stabilizes to a smaller incrementper cycle than the CCB. The same behavior applies to theequivalent creep strains. A summary of the equivalent creepand plastic strains is given in Table I. The PEEQ in theweakest location of the CCB joint is much larger than thatin the dimple solder joint.

Figure 20

Strain components at the weakest locations in the solder joints

Figure 21

Shear stress-strain hysteresis loops for the CCB and dimple solder joints

Figure 19

Stress components at the weakest locations in solder joints



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Correlation between FE modeling andexperimentThermal cycling correlationA modified Coffin-Manson equation based on conventionalcreep and plastic theory and a constitutive theory ofisotropic thermo-viscoplasticity (Hong and Burrell, 1995)was used to estimate the fatigue life of the interconnects andis obtained as:

N50 B1 D1ineq C 2

where N50 is the mean fatigue life, D1ineq is the accumulated

equivalent inelastic strain per cycle, B1 and C are materialsconstants which are 0.146 and 21.94, respectively, foreutectic solder (Mukai et al., 1997). It must be pointed outthat the material constants are highly sensitive to thepackage type, solder pad size and solder volume, and thedominant fatigue mechanism (creep vs plasticity), such thatit is not realistic to expect a perfect match between theexperimental data and the life prediction based on theseconstants. The comparison between the experimental resultsand FEM predictions is summarized in Table II. The dimplearray improved the fatigue life by a factor of 14 (for a 20percent resistance increase) and 8 (for a 50 percentresistance increase) over that of the CCB. The FE modelingpredicts an improvement of 4.6 for location A and 9.7 for location B. Discrepancies between the experimental andpredicted numbers are inevitable for a host of reasons.To begin with, the quality of the actual test structures maydeviate from the idealized structure used in the model.Assumptions and simplifications in the FEM modeling also

contribute to the discrepancies. These differences arediscussed in more detail elsewhere (Wen, 2002).

Power cycling correlationOwing to the fact that the power cycling test could notprovide a credible estimate of time-to-crack-initiation, it isimpossible to correlate FE modeling fatigue life predictionwith experiments. For the completeness of this work, theFEM-predicted crack initiation times are shown in Table III.Clearly, the dimple solder joints perform better than theCCB joint under power cycling conditions. Whilecorrelation is very difficult to establish, it is neverthelesspossible to obtain a correlation of the failure mechanisms aspredicted by FE modeling with those observed in theexperimental samples. Observed and predicted failuremodes and locations for DAI and CCB joints are shown inFigures 23 and 24. The dimple array joint in Figure 23 wascycled 12,700 times from 10 to 1008C. Cracking took placeaway from the solder/device interface. The FEM-predictedmaximum inelastic strain distribution roughly coincideswith the cracking on the experimental sample. In the case ofthe CCB joint in Figure 24, cracking initiated and grew atthe solder/device interface. The FE modeling predicted thehighest inelastic strain to be in this location and therefore, isthe likely site for crack initiation and growth.

Fatigue cycles to failure obtained from power cyclingtests are usually much larger than those obtained by thermalcycling. The discrepancy arises from the different cyclingfrequency between the two tests. A thermal cycle takesminutes, and in some case over an hour, to complete,while power cycling can be performed at a much higherfrequency. In the case of the test performed here, one cycle

Figure 22Total cumulative equivalent plastic strain for first four cycles: (a) DAI, and (b) CCB solder joint

Table IComparison of the equivalent creep, plastic and total inelastic strain per cycle

Saturated strain range Dimple, location A Dimple, location B CCB

Equivalent creep (CEEQ) 0.0041 0.00398 0.00528Equivalent plastic (PEEQ) 0.00062 0.0009 0.0035Total inelastic strain range 0.00472 0.00488 0.00878

Table IIFEM predictions and experimental results for thermal cycling

Saturated strain range Dimple, location A Dimple, location B CCB

Equivalent creep (CEEQ) 0.0617 0.0424 0.1230Equivalent plastic (PEEQ) 0.0036 0.0020 0.0207Equivalent inelastic D1ineq 0.0653 0.0444 0.1437Predicted N50 (cycles) 29 61 6.3Experimental (20 percent increase of dcresistance)

110 110 8

Experimental (50 percent increase of dcresistance)

185 185 23



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took at most 1min. The long duration per thermal cycleallows for the accumulation of significant damage in onecycle, while rapid switching during power cycling producesmuch less incremental damage per cycle. Nevertheless, bothtests should exhibit the same trend as to the relativereliability of each interconnect structure.

Conclusions

Based on the experimental and FE modeling work on thestacked solder joint interconnect and DAI, the followingconclusions can be made compared with the conventionalsolder bump interconnection. Temperature cycling testsshowed that the hourglass-shaped triple-stacked solder jointhas better reliability than a barrel-shaped stacked solderjoint, which in turn had improved reliability over that ofsingle bump barrel-shaped solder joint. The increasedreliability of the hourglass-shaped stacked solder joint canbe traced to increased crack initiation and propagation timesover that for the single bump barrel-shaped joint.

Using flexible substrates also contributes to the increasedreliability of the joint. It provides a mechanism foraccommodating the stress generated by the CTE mismatchbetween the device and substrate by buckling duringtemperature excursions.

The DAI exhibited improved reliability over that of CCBsolder joints. Part of the improvement is due to therelocation of highest stress away from the inherently weaksolder/device interface. In the FE modeling, the smallershear strain range of the DAI during temperature cyclingsuggests a smaller damage per cycle over that of CCB joints,which in turn results in prolonged lifetime. In the modelingof power cycling, the dimple joint experiences higher initialequivalent plastic and creep strains, but stabilizes to smallerincrements per cycle than the CCB, thus leading toimproved fatigue life.

While a perfect correlation between temperature cyclingand experiment and FE modeling is not realistic to attain,there is a qualitative agreement between the two in thecomparative reliability of DAI and CCB joints.A comparison of the observed failure mechanisms of bothjoints and FE modeling predictions of the highest inelastic

Figure 23(a) Optical micrograph of a DAI joint after 12,700 cycles; and (b) the FEM predicted inelastic strain distribution

Table IIIPredicted crack initiation time using FEM

Inelastic strain range Dimple, A Dimple, B CCB

Without DBC D1ineq 0.00472 0.00488 0.00878Modified D1ineq 0.00393 0.00407 0.00732Predicted N50 (cycles) 6,780 6,335 2,029



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strains under both temperature and power cycling conditionsalso showed very good agreement. In the DAI joints,cracking occurred away from the solder/device interface.In the CCB joint, cracking was observed to have taken placeat the solder/device interface.

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Figure 24

(a) SEM image of a CCB joint after 8,500 cycles; and (b) the FEM predicted inelastic strain distribution



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We are grateful to Dan Hufffor the extensive technicalassistance he provided tothe research effort.



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