370 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 9, NO. 3, JUNE 2015A 58 nW ECG ASIC With Motion-TolerantHeartbeat Timing Extraction for WearableCardiovascular MonitoringDavid Da He and Charles G. Sodini, Fellow, IEEEAbstractAn ASIC for wearable cardiovascular monitoringis implemented using a topology that takes advantage of theelectrocardiogram's (ECG) waveform to replace the traditionalECG instrumentation amplier, ADC, and signal processor witha single chip solution. The ASIC can extract heartbeat timings inthe presence of baseline drift, muscle artifact, and signal clipping.The circuit can operate with ECGs ranging from the chest locationto remote locations where the ECG magnitude is as low as 30 V.Besides heartbeat detection, a midpoint estimation method can ac-curately extract the ECG R-wave timing, enabling the calculationsof heart rate variability. With 58 nW of power consumption at0.8 V supply voltage and 0.76 mmof active die area in standard0.18 m CMOS technology, the ECG ASIC is sufciently lowpower and compact to be suitable for long term and wearablecardiovascular monitoring applications under stringent batteryand size constraints.Index TermsCardiovascular monitoring, electrocardiogram,heart rate, motion artifacts, wearable sensor.I.INTRODUCTIONCARDIOVASCULAR DISEASE (CVD) affects 37% ofthe United States population and is the leading cause ofdeath in the U.S. [1]. One type of CVD is cardiac arrhythmia,which is characterized by irregular heartbeat intervals. Themost common form of cardiac arrhythmia is atrial brillation(AF) [2]. AF occurs when the atrium exhibits rapid and irreg-ular contractions. AF is often undiagnosed, but increases therisk of stroke and heart failure by up to nine times [2]. Anotherexample of arrhythmia is premature ventricular contraction(PVC). PVC's can be the symptom of an underlying CVD suchas cardiomyopathy. Both AF and PVC can be identied usingcontinuous heartbeat timing monitoring [3].The electrocardiogram (ECG) is a non-invasive surface mea-surement of the heart's electrical potentials and is a primary toolfor the assessment of cardiac health. Traditionally, the topologyfor an ECG heartbeat detection circuit consists of a low noiseinstrumentation amplier (IA), an anti-alias lter, an ADC, andManuscript received February 23, 2014; revised May 27, 2014 and July 07,2014; accepted August 01, 2014. Date of publication September 19, 2014; dateof current version May 22, 2015. This work was supported by the MIT MedicalElectronic Device Realization Center (MEDRC). This paper was recommendedby Associate Editor P. Mercier.The authors are with the Department of Electrical Engineering and ComputerScience, Massachusetts Institute of Technology, Cambridge, MA 02139 USA(e-mail: david.he@alum.mit.edu; sodini@mit.edu).Color versions of one or more of the gures in this paper are available onlineat http://ieeexplore.ieee.org.Digital Object Identier 10.1109/TBCAS.2014.2346761Fig. 1. (a) The traditional topology for ECG heartbeat detection. (b) Theproposed topology with voltage nodes labeled.(c)An ECG waveformillustrating the QRS complex, baseline, baseline with offset, and digitaloutput.a digital processor [4][6]. This topology is shown in Fig. 1(a)along with a labeled ECG in Fig. 1(c).In this conventional topology, the IA amplies the differen-tial ECG signal with low noise op amps. The gain of the IAis set so that the amplied output is not saturated. After theanti-alias lter, the ADC uniformly quantizes the ECG signal,treating small features such as the ECG's P-wave and largefeatures such as the ECG's R-wave with equal resolution. TheADC is usually implemented with a medium resolution SARarchitecture to minimize power consumption. Finally, to detectheartbeats, the digitized ECG is processed using an algorithmto detect R-waves. Depending on the computational poweravailable, such an algorithm ranges from simple thresholdingto wavelet transforms. Even with a deep subthreshold digitalprocessor such as in [6], the digital R-wave detection algorithm1932-4545 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.HE AND SODINI: A 58 nW ECG ASIC WITH MOTION-TOLERANT HEARTBEAT TIMING EXTRACTION 371can consume three times higher power than the analog frontend.The traditional topology is necessary for clinical ECG mea-surements, where multi-lead ECGsignals are acquired with highdelity in order to diagnose arrhythmias. These recordings areusually quantized with at least 12 bits to preserve P-wave de-tails [7]. The American Heart Association recommends a sam-pling frequency of at least 150 Sa/s to capture all features, whilestating that a bandwidth of 1 Hz to 30 Hz generally produces astable ECG without artifacts [8].However, as mentioned, common arrhythmias can be de-tected with heartbeat timing monitoring where only the R-wavetiming is needed. To take advantage of this fact, a new topologyis presented that removes the need for the ADC and the signalprocessor to decrease the overall circuit's complexity, power,and area. The demonstrated ASIC receives the ECG signal asan analog input and outputs a digital heartbeat signal, whilebeing tolerant to signal interferers such as motion artifacts.This paper is organized into the following sections. Section IIexplains how the proposed topology operates. Section III dis-cusses each circuit block in detail. In Section IV, measured re-sults from both testbench and human subject tests are presented.Furthermore, a method to accurately extract R-wave timingsfrom the ASIC output is validated using clinical data.II. PROPOSED CIRCUIT TOPOLOGYThe proposed topology is based on the fact that heartbeat de-tection relies on the ECG's QRS complex, which has a higherfrequency content and a greater magnitude than the adjacentECG features. This circuit topology is shown in Fig. 1(b).In Fig. 1(b), the differential ECG signal is rst amplied bya low noise programmable gain amplier (PGA). The PGA'soutput signal is split into two paths. The rst path goes throughthe QRS Amp, which has a bandwidth that preserves the QRScomplex. The second path goes through the Baseline Amp,which has an equal gain but a lower bandwidth to preserveonly the low frequency baseline drift caused by motion arti-facts. Then, a positive inline DCoffset is added toto create an adaptive threshold . A QRS complex(or heartbeat) occurs whenever . Thiscomparison is performed by a comparator, which consequentlypulses a high when a heartbeat is detected.To correctly set , it is incremented until the period be-tween pulses is regular and is in the range of humanbeat-to-beat interval. As shown in Fig. 1(c), there is a wide rangeof valid values since can be set at any level betweenthe R-wave and the next highest amplitude feature (usually theT-wave). Because respiration causes slight baseline modulationof the ECG, we use four respiratory cycles to complete thecalibration routine, which takes 20 seconds on average. This cal-ibration is performed at the beginning of measurement by an ex-ternal microcontroller that consumes 5 A at a clock frequencyof 4 kHz, which is powered off afterwards.During measurement, may need to be recalibrated if themeasurement condition changes signicantly due to motion ar-tifacts or muscle noise. The need to recalibrate can be de-tected in real time when exceeds the human heart raterange or when becomes irregularly spaced. Once de-Fig. 2. The PGA schematic.tected, the initial calibration routine can be rerun to update .If the irregular is caused by actual irregular R-waves,then the recalibration will be unable to complete, in which casearrhythmia can be implied.There are several advantages to this topology in terms of cir-cuit design. First, no signal processor or ADCis required, whichsignicantly reduces the device's power and area. Second, a lowvoltage supply is possible because a clipped R-wave that ex-ceeds the amplier's output range still possesses heartbeat infor-mation. Third, any comparator offset is automatically compen-sated due to the calibration. Fourth, amplier linearity isunimportant because the signal path is highly nonlinear. In termsof practical usage, this topology is tolerant to motion artifactsbecause the signal is differentially compared against its ownbaseline. Furthermore, no predened subject-dependent param-eters are needed.III. CIRCUIT DESIGNA. Programmable Gain AmplierThe PGA's function is to amplify the ECG directly from theelectrodes with minimal circuit noise and power while having arange of gain to adapt to various ECG amplitudes. Fig. 2 showsthe schematic of the PGA, which consists of an op amp in thedifference conguration.Sensing a biopotential such as the ECGcreates several circuitrequirements. First, because the ECG amplitudes vary betweendifferent body locations and different subjects by up to two or-ders of magnitude, an adjustable gain is required. The gain ofthe PGA is set by , where pF and is im-plemented as a 6-bit binary weighted capacitor bank of 20 fF to1.28 pF to adjust the PGA gain from 19 dB to 56 dB.Second, the AgCl electrode's half-cell potential generates ap-proximately 200 mVof near-DCelectrode offset voltage (EOV)which would saturate the amplier if not removed. To lter thisEOV, PMOS pseudo-resistors are used [9]. The 's aregreater than 10 but only occupy 10 m , thus enablingon-die sub-Hz high pass lters and effectively removing theEOV. The large also allows the DC biasing of the ampli-er inputs while maintaining a high input impedance, whichis needed due to the capacitive . Furthermore, because theinput impedance is signicantly larger than k,any differential voltage caused by unequal and varying(such as during motion) is negligible.It should be noted that the high impedance at the PGA inputnodes leads to long start-up settling times. As a solution, resetswitches shown in Fig. 2 are added to the PGA inputs to imme-372 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 9, NO. 3, JUNE 2015diately shunt the input nodes to their nal common-mode DCvoltage during start-up.The PGA's op amp is a two-stage Miller-compensated opamp. This topology is chosen because of its compatibility withlow voltage supply, wide output swing, and self-biasing. Due tothe low frequency and bandwidth requirements of ECG signals(1 Hz25 Hz), the PGA can operate in deep subthreshold with90 nA of bias current. The low leads to a greater thermalnoise spectral density, but the thermal noise contribution is lim-ited because of the PGA's low bandwidth.At this frequency, the dominant noise source is noise.Chopper modulation at the PGA inputs is a possible methodto eliminate noise. However, chopper switches introduce acurrent path between the PGA inputs. If there is any input offsetvoltage, then an offset current would exist that can saturate thePGA through the high resistance feedback . A solution isto use a servo-loop to provide a current path, but itconsumes additional current [10]. Without chopping, the inputnoise can be designed to be within 1 (0.5 Hz50 Hz)by appropriate transistor sizing, which is acceptable for ECGsignals that are typically at 1 mV. For these reasons, choppermodulation is not used.The input-referred noise spectral density for this opamp is shown in (1), where when in sub-threshold [11](1)According to (1), several design choices are made to minimizenoise. First, PMOS input transistors are used because theyoffer lower noise coefcients than NMOS transistors:. Second, increasing and will reduce the noisecontribution of the input transistors. However, excessive inputtransistor area will introduce signicant parasitic capacitance atthe drain of M2. This decreases the frequency of the second poleand lowers the phase margin. A dimension of 864 m/1.5 m(96 ngers of 9 m/1.5 m) is chosen so that M1 and M2'snoise contributes to 40% of total input noise. Third, increasingand will reduce the noise contribution of the mirror tran-sistors. However, signal swing places an upper limit on andprocess technology places an upper limit on . A dimension of100 m/20 m (8 ngers of 12.5 m/20 m) is chosen so thatM3 and M4's noise contributes to 20% of total input noise.B. QRS and Baseline AmpliersThe PGA's output is connected to the inputs of the QRS andBaseline Amps. The function of the QRS Amp is to amplifythe ECG signal with a bandwidth that passes the QRS complex.Meanwhile, the Baseline Amp has the same gain but has a lowerbandwidth that only passes the baseline signal.In Fig. 3, both ampliers use identical two-stage Miller-com-pensated op amps in the non-inverting conguration. The onlydifference is in the compensation capacitors . The Millermultiplied and a 0.5 nA bias current create very low cornerfrequencies while being area-efcient. For the QRS Amp,fF sets the lowpass corner frequency at 25 Hz, which passesFig. 3. The QRS Amp and the Baseline Amp schematic.Fig. 4. The generator schematic.the QRS complex. For the Baseline Amp, pF sets thelow pass corner frequency at 1 Hz, which only passes the base-line drift. Pseudo-resistors are used to bias the inverting node.Both QRS and Baseline Ampshave a xed gain ofdB, thus resulting in an overall gainrange of 47 dB to 84 dB. At this overall gain range and withV, the full dynamic range can be used to measureECG signals at various wearable locations on the body wherethe ECG ranges from approximately 30 to 3 mV .C. GeneratorThe generator's function is to add to toproduce an adaptive threshold . The generatorschematic is shown in Fig. 4.is a 4-bit binary weighted capacitor bank of 15 fF to155 fF, and is a 7-bit binary weighted capacitor bank of40 fF to 5.1 pF. and values are selected during theinitial calibration by the microcontroller.Non-overlapping clock phases and are generatedon-chip at 2.0 kHz by a clock generator. The clock frequencyis chosen as a compromise between low power (favors lowerfrequency) and low charge leakage (favors higher frequency).During clock phase [Fig. 5(a)], and arerespectively reset to and ground. During the followingclock phase [Fig. 5(b)], is charged to a nal voltageof . During the fol-lowing clock phase is added to to produce, while and are again reset. ispresent to reduce voltage ripples. With the selectable rangesof and can be adjusted from 0% to 80% ofHE AND SODINI: A 58 nW ECG ASIC WITH MOTION-TOLERANT HEARTBEAT TIMING EXTRACTION 373Fig. 5. The generator in (a) clock phase and (b) clock phase .Fig. 6. The generator's internal circuit blocks. (a) can be ippedduring phase in the case of reversed electrodes. (b) The low leakage switchimplementation to prevent capacitor discharge [12].. This range covers most situations where the interfereror noise occupies up to 80% of while having a loweramplitude than the R-wave.In consideration for long term at-home usage where the ECGelectrodes are applied by the wearer, the generator has theability to generate negative if the user accidentally reversesthe electrodes. This is symbolized by the two digital blocks inFig. 4 that can ip during phase . In the case that theECG is reversed and is ipped, then the heartbeat occurswhen instead of . These digital blocksare expanded in Fig. 6(a).Because the switching frequency is only 2.0 kHz andpF, a leakage current of only 5.8 pA can reduceby 1 mV between clock cycles. To reduce switch leakage,stacked switches with a push-pull buffer are implemented basedon [12]. The switch schematic is shown in Fig. 6(b) and is usedfor all switches in Fig. 4. The two stacked switches in Fig. 6(b)exponentially reduce the subthreshold by decreasing theof the two switches. The push-pull buffer drivesto the same voltage as , thus further decreasing byreducing the of the switch closest to the capacitor. Allswitch and buffer transistors are minimally sized (PMOS:400 nm/180 nm, NMOS: 220 nm/180 nm) to reduce the effectof charge injection.Fig. 7. The dynamic latched comparator with SR latch. The comparator isbased on [13].D.ComparatorThe comparator's role is to output a digital pulse when a QRScomplex has occurred, which is when . Adynamic latched comparator based on [13] is used (Fig. 7). Thedynamic topology is chosen because it consumes power onlywhen latching. This topology offers the additional benet ofonly using a single clock signal , thus placing no requirementson timing.M11 and M12 are added to reduce short circuit currentsthrough M13M16 when and are transitioning. This isimportant because short circuit currents of several nano-ampscan be a signicant portion of the overall power.contains switching transients from the generator. How-ever, these transients are designed to occur with , which donot affect comparator accuracy because comparator latchingoccurs with .M1-M4 gate lengths are set at 1 m to reduce geometry mis-match. A Monte Carlo mismatch simulation of 100 runs pro-duces an input-referred comparator offset range of mV to16 mV. However, as mentioned in Section II, no comparatoroffset compensation is needed due to the calibration rou-tine. The nal output of the SR latch, , is a digital signalthat pulses when a heartbeat is detected.E. Peripheral CircuitsAll peripheral circuits and passive components are imple-mented on-chip. These circuits include a fast startup current ref-erence for the ampliers based on [14], a diode ladder voltagereference to generate the common-mode voltage for the PGA,and a clock generator that provides the 2.0 kHz non-overlappingclock signals for the generator and the comparator.IV. MEASUREMENT RESULTSThe ASIC is fabricated using a standard TSMC 0.18 m1P6M CMOS technology. The die area is 1.8 mm 1.8 mmwith an active area of 0.76 mmas shown in Fig. 8.374 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 9, NO. 3, JUNE 2015Fig. 8. Die micrograph of the ECG ASIC with the circuit blocks labeled.Fig. 9. The measured PGA-QRS Amp signal path's gain response and noiseresponse.A. Testbench MeasurementsThe ECG's amplication path goes through the PGAand thenthe QRS Amp. Fig. 9 shows the gain response and input-re-ferred noise response at the highest gain setting. In the gain re-sponse, the plot shows the sub-Hz high pass corner enabled bythe PGA and QRS Amp's pseudo-resistors, the low pass cornerimplemented by the QRS Amp's low and large , and the40 dB/dec falloff at higher frequencies due to the two poles fromthe PGA and the QRS Amp. In terms of noise response, the cir-cuit exhibits a characteristic below 10 Hz (or whenplotted as ).Table I compares the simulated and measured results fromthe PGA-QRS Amp signal path. Increasing the transistor biascurrents did not appreciably decrease the input-referred noise,TABLE ISIMULATED VERSUS MEASURED RESULTS FROM THEPGA-QRS AMP SIGNAL PATHTABLE IISIMULATED VERSUS MEASURED POWER CONSUMPTION OF EACH CIRCUITBLOCK AT Vwhich indicates that the in-band noise is dominated as Fig. 9indicates. Because of this, the actual PGA's bias current is low-ered compared to simulation, and the reduced low pass fre-quency of 22 Hz remains sufcient to preserve the ECG's QRScomplex. The measured input-referred noise is greater than thesimulated noise by 2.7 times, which is likely attributed to differ-ences between the transistor model's and the actual transistor'scharacteristics. The measured level of noise is compatiblewith sensing the ECG, where the QRS amplitude is typically.Table II lists the power consumption of each circuit blockat V. 87% of the total power is allocated to thePGA due to bandwidth and thermal noise considerations. Theperipheral circuits consume 8.6% of the total power. The ECGASIC's elimination of the ADC and the signal processor enablesit to reduce power consumption. Another portion of the powersaving is contributed by the PGA's low bandwidth. A furthersource of power saving is the ECG ASIC's low , which isenabled by its tolerance to signal clipping.B. ECG MeasurementsFig. 10(a) to (d) showmeasured ECGand digital outputs fromvarious wearable ECG scenarios to demonstrate the ASIC's ro-bustness in the presence of baseline drift, muscle artifacts, andattenuated signal.In Fig. 10(a), the at-rest chest ECG offers of stablesignal. Here, is set to 0.3 V so that is approx-imately half of the amplitude. However, any settingHE AND SODINI: A 58 nW ECG ASIC WITH MOTION-TOLERANT HEARTBEAT TIMING EXTRACTION 375Fig. 10. (a) Measured chest ECG at rest dB). (b) Measured chestECG with baseline drift due to motion artifacts dB). (c) Measuredchest ECGwith muscle noise and signal clipping ( dB). (d) Measuredhead ECG with high gain due to attenuated signal ( dB).between 0.1 V and 0.65 V would produce the correct digitalQRS output at .In Fig. 10(b), the chest ECGcontains signicant baseline driftdue to motion. Despite the baseline drift, the same settingas in Fig. 10(a) results in a correct . In fact, anysetting between 0.1 V0.5 V would be valid. This demonstratesthe ASIC's tolerance to motion artifacts because its adaptivethreshold tracks the baseline drift.In Fig. 10(c), pectoral muscle artifacts are present from arapid horizontal 90 arm movement. Also, an intentional highgain of 64 dB increases the amplied ECG to , whichis beyond V and is clipped. To produce the correctneeds to be increased to 0.5 V so thatrises above 's muscle artifacts and amplied T-waves. TheQRS complex's clipping does not matter because the beat infor-mation is still present. This scenario is an example of a signif-icant change of measurement condition leading to a newsetting.To test the ASIC in the presence of an attenuated ECG signal,we mount it at the head so that the ECG is measured acrossthe ear and the middle upper neck as shown in Fig. 11. TheECG at this location is in the range of 30 ,which is two orders of magnitude smaller than the standard chestECG. This attenuation is due to the pattern of the ECG eldlines at the head, which yield a very small potential differencewhen projected onto the lead. Because of this attenuation, thehead ECG has a poor signal-to-noise ratio and only R-wavesare immediately visible [15].Due to the attenuation, the gain is increased to 84 dB to sensethe 30 of ear ECG. At this high gain, a signicant portionof the amplied output is noise and R-wave clipping is present,leading to an SNR of only 2.7 dB. However, with the identicalsetting as in Fig. 10(a) and (b), is able to riseabove the noise and correctly capture the heartbeats as shownby in Fig. 10(d).Fig. 11. The wearable ASIC board at the head with wireless data transmissionto a computer.Fig. 12. Estimation of the R-wave timing using the midpoint timing of .C. Recovering the ECG R-Wave Timing FromWhile provides an approximate timing of the ECGR-wave, an accurate ECG R-wave timing is necessary for sev-eral cardiovascular monitoring applications such as the calcula-tion of heart rate variability for disease prediction.Although the R-wave's peak is clipped in , the orig-inal R-wave timing can still be recovered with minimal error.As shown by Fig. 12, the R-wave timing can be estimated fromthe midpoint timing of pulses. This method is testedon normal chest ECG records from ten subjects totaling 2,304heartbeats from the MIT-BIH PhysioNet database and from ourMIT clinical test (MIT IRB approval #1104004449). Midpointestimated R-wave timings are compared with manually anno-tated timings, the results of which are summarized in Table III.In all ten subjects, the standard deviation of R-wave timingerror is less than the sampling period. This demonstrates that theR-wave midpoint estimation method can accurately recover theECG peak timing information from . This enables the useof the ECG ASIC for applications beyond heartbeat detection,such as heart rate variability analysis, where accurate R-wavetiming is necessary.V.CONCLUSIONAn ECG ASIC for wearable heart monitoring is presentedthat takes advantage of the ECG's characteristics to extractheartbeat timings in the presence of motion artifacts, muscle376 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 9, NO. 3, JUNE 2015TABLE IIICOMPARISON BETWEEN MIDPOINT-ESTIMATED R-WAVE TIMINGS ANDMANUALLY ANNOTATED R-WAVE TIMINGS FROM TEN SUBJECTSnoise, signal clipping, and attenuated ECG signals as lowas 30 V. Besides heartbeat detection, the R-wave timing isextracted using a midpoint estimation method. R-wave timingscan be used for the calculation of predictive cardiovascularparameters such as heart rate variability.Implemented using a standard 0.18 m 1P6M CMOS tech-nology, the ASIC consumes 58 nW of power at 0.8 V supplyand occupies 0.76 mmof active die area. The ECG ASIC hassufciently low energy consumption for one year of continuousoperation from a 0.7 mAh thin-lm battery, making it ideal forminiaturized and long term heartbeat monitoring in extremelybattery constrained applications such as implantable pace-makers and debrillators. Furthermore, the ECG ASIC's powerconsumption is in range of energy harvesting power sources,thus making batteryless heartbeat monitoring a possibility.ACKNOWLEDGMENTThe authors would like to thank Prof. H.-S. Lee (MIT),T. O'Dwyer (Analog Devices), and Dr. M. Coln (Analog De-vices) for their valuable assistance. The chip fabrication wasgenerously provided by TSMC.REFERENCES[1] P. Heidenreich et al., Forecasting the future of cardiovascular diseasein the United States: A policy statement from the American Heart As-sociation, Circulation, vol. 123, pp. 933944, 2011.[2] J. Waktare, Atrial brillation, Circulation, vol. 106, no. 1, pp. 1416,2002.[3] J. Chong, D. D. McManus, and K. H. Chon, Arrhythmia discrimina-tion using a smart phone, in Proc. IEEE Body Sensor Networks Conf.,2013, pp. 223226.[4] R. Yazicioglu et al., A 30 W analog signal processor ASIC forbiomedical signal monitoring, in Proc. IEEE Int. Solid-State CircuitsConf., Dig. Tech. Papers, 2010, pp. 124125.[5] S. Jocke et al., A 2.6 W sub-threshold mixed-signal ECG SoC, inProc. Symp. VLSI Circuits, 2009, pp. 6061.[6] D. Jeon et al., An implantable 64 nW ECG-monitoring mixed-signalSoC for arrhythmia diagnosis, in Proc. IEEE Int. Solid-State CircuitsConf., Dig. Tech. Papers, 2014, pp. 416417.[7] F. Censi et al., On the resolution of ECG acquisition systems for thereliable analysis of the P-wave, Phys. Meas., vol. 33, p. 11, 2012.[8] J. Mason, E. Hancock, and L. Gettes, Recommendations for thestandardization and interpretation of the electrocardiogram. Part I:The electrocardiogram and its technology., Circulation, vol. 115, pp.13061324, 2007.[9] R. Harrison and C. Charles, A low-power low-noise CMOS amplierfor neural recording applications, IEEE J. Solid-State Circuits, vol.38, no. 6, pp. 958965, 2003.[10] N. Verma et al., A micro-power EEG acquisition SoC with integratedfeature extraction processor for a chronic seizure detection system,IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 804816, 2010.[11] D. Johns and K. Martin, Analog Integrated Circuit Design. NewYork, NY, USA: Wiley, 1996.[12] D. Daly and A. Chandrakasan, A 6-bit, 0.2 V to 0.9 V highly digitalash ADC with comparator redundancy, IEEE J. Solid-State Circuits,vol. 44, no. 11, pp. 30303038, 2009.[13] M. Miyahara et al., A low-noise self-calibrating dynamic comparatorfor high-speed ADCs, in Proc. IEEE Asian Solid-State Circuits Conf.,2008, pp. 269272.[14] S. Mandal, S. Arn, and R. Sarpeshkar, Fast startup CMOS currentreferences, in Proc. IEEE Int. Symp. Circuits and Systems, 2006, p. 4.[15] D. He, E. Winokur, and C. Sodini, The ear as a location for wearablevital signs monitoring, in Proc. IEEE Engineering in Medicine andBiology Conf., 2010, pp. 63896392.David Da He received the B.A.Sc. degree in elec-trical engineering from the University of Toronto,Toronto, ON, Canada, and the S.M. and the Ph.D.degrees in electrical engineering from the Massa-chusetts Institute of Technology, Cambridge, MA,USA, in 2005, 2008, and 2013, respectively.He has worked on a variety of sensors, includinga wearable vital signs monitor, an organic thin-lmtransistor temperature sensor, and industrial wirelesscondition monitoring sensors. Currently, he is a co-founder and the Chief Scientic Ofcer of Quanttus,Cambridge, MA, USA, where he works on new ways for wearable sensors, al-gorithms, and data insights to transform how we view personal health.Dr. He has served on the technical committee of the IEEE International Con-ference on Body Sensor Networks.Charles G.Sodini(M'82SM'90F'95) receivedthe B.S.E.E. degree from Purdue University, WestLafayette, IN, USA, and the M.S.E.E. and Ph.D.degrees from the University of California, Berkeley,CA, USA, in 1974, 1981, and 1982, respectively.He was a member of the technical staff at Hewlett-Packard Laboratories from 1974 to 1982, where heworked on the design of MOS memory. He joined thefaculty of the Massachusetts Institute of Technology,in 1983, where he is currently the LeBel Professorof Electrical Engineering. His research interests arefocused on medical electronic systems for monitoring and imaging. These sys-tems require state-of-the-art mixed signal integrated circuit and systems with ex-tremely low energy dissipation. He is the cofounder of the Medical ElectronicDevice Realization Center at MIT. Along with Prof. Roger T. Howe, he is acoauthor of an undergraduate text on integrated circuits and devices entitled Mi-croelectronics: An Integrated Approach. He also studied the Hong Kong/SouthChina electronics industry in 19961997 and has continued to study the global-ization of the electronics industry. He was a cofounder of SMaL Camera Tech-nologies, a leader in imaging technology for consumer digital still cameras andmachine vision cameras for automotive applications.Dr. Sodini has served on a variety of IEEE Conference Committees, includingthe International Electron Device Meeting, where he was the 1989 GeneralChairman. He has served on the IEEE Electron Device Society AdministrativeCommittee and was President of the IEEE Solid-State Circuits Society from20022004. He is currently the Chair of the Executive Committee for the VLSISymposia.