06175116

272 IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 17, NO. 2, APRIL 2013

FPGA Implementation of an EvolutionaryAlgorithm for Autonomous Unmanned Aerial

Vehicle On-Board Path PlanningJonathan Kok, Luis Felipe Gonzalez, and Neil Kelson

Abstract—In this paper, a hardware-based path planningarchitecture for unmanned aerial vehicle (UAV) adaptation isproposed. The architecture aims to provide UAVs with higherautonomy using an application-specific evolutionary algorithm(EA) implemented entirely on a field-programmable gate array(FPGA) chip. The physical attributes of an FPGA chip, beingcompact in size and low in power consumption, makes it an idealplatform for UAV applications. The design, which is implementedentirely in hardware, consists of EA modules, population storageresources, and 3-D terrain information necessary to the pathplanning process, subject to constraints accounted for separatelyvia UAV, environment, and mission profiles. The architecture hasbeen successfully synthesized for a target Xilinx Virtex-4 FPGAplatform with 32% logic slice utilization. Results obtained fromcase studies for a small UAV helicopter with environment derivedfrom light-detection and ranging data verify the effectivenessof the proposed FPGA-based pathplanner, and demonstrateconvergence at rates above the typical 10 Hz update frequencyof an autopilot system.

Index Terms—Evolutionary algorithm (EA), field-programmable gate array (FPGA), path planning, unmannedaerial vehicle (UAV).

I. Introduction

UNMANNED aerial vehicles (UAVs) are on an upsurgeand on track to becoming the preeminent platform for

some military [2] and civilian aerial applications [3]. In a5-year period, from 2010 to 2015, the U.S. UAV marketalone is forecasted to generate $62 billion in revenues [4].Potential advantages of UAV deployment on both civilian andmilitary missions include decreased risk of fatality and reducedworkload of human operators which in turn can increaseefficiency and reduce mission costs.

The advancement of UAV technology and applications hasbeen assisted by research aimed at improving levels of auton-omy while being bounded by flight constraints. These include

Manuscript received July 2, 2011; revised October 22, 2011, December 31,2011 and February 23, 2012; accepted March 12, 2012. Date of publicationApril 3, 2012; date of current version March 27, 2013. This paper is anextension of earlier work that appeared in [1]. The review of this paper wascoordinated by A. Tyrrell.

J. Kok and L. F. Gonzalez are with the Australian Research Cen-tre for Aerospace Automation, Queensland 4009, Australia (e-mail:[email protected]; [email protected]).

N. Kelson is with the High Performance Computing and Research SupportGroup, Division of TILS, Queensland University of Technology, Brisbane4001, Australia (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TEVC.2012.2192124

power consumption, physical space, and weight limitations,along with limited on-board telecommunication, computation,and other resources. One aspect of the research effort isto investigate the feasibility of more autonomous on-boardpath planning as an alternative to the current UAV pathplanning performed remotely by human operators. This isnot straightforward, as solving the path planning problem forautonomous UAV navigation is an NP-hard problem [5]. Fur-thermore, the overall path planning process involves complexdesign issues, as there exists strong couplings between theenvironment representation, type of path planning algorithm,and the application-specific task [6].

To date, UAV path planning algorithms have been primarilydeveloped via personal computer software-based implementa-tion, which may not explicitly take into account some requiredreal-time flight constraints appropriate for UAVs operatingautonomously in the field [7]. In contrast, reconfigurablefield-programmable gate arrays (FPGAs) are relatively smalland light, making them suitable for flight-constrained UAVapplications, where, e.g., the size and weight of the payloadis greatly restricted.

In light of the above, our paper considers an entirely on-board hardware-based path planning system in the contextof an overall constrained process, where profiles that defineconstraints relating to the environment, the mission, and theindividual characteristics of the UAV are specified. A pathplanning architecture is proposed and implemented directlyon an FPGA platform based on the use of evolutionary algo-rithms (EAs). Regarding algorithm choice, EAs are consideredviable search algorithms for real-time UAV path planning[8]–[13].

The EA-based pathplanner developed in this paper is basedon a modified genetic algorithm (GA) [14] capable of findingglobal solutions, albeit at significant computational expense[15]. To address this issue, a GA-based pathplanner is devel-oped with all modules of the proposed architecture entirelyimplemented and run on a single FPGA for computationalefficiency. Compared to prior work, this paper is the only oneknown to the authors that attempts to implement all of therelevant functionalities of the GA-based pathplanner entirelyon reconfigurable FPGA hardware. Conceptually, we elaborateon earlier design proposals by explicitly accounting for awider range of flight constraints via the inclusion of segregatedUAV, environment, and mission profiles within corresponding

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KOK et al.: FPGA IMPLEMENTATION OF AN EVOLUTIONARY ALGORITHM 273

separate hardware modules. Additionally, 3-D terrain data isstored on the FPGA, via the hardware module correspondingto the environment profile. The approach taken is intendedto be more modular and extensible than prior proposals andshould permit greater UAV autonomy.

To the authors’ knowledge, optimal in-hardware implemen-tation of various GA functions and modules has also not beenaddressed in detail by earlier studies. In contrast, we insteadexplore hardware-based implementation of both the overallarchitecture and the various functional modules within it so asto exploit the parallel processing capability of the FPGA. Forexample, our design incorporates a 6-to-1 multiplexer (MUX)memory interface that is resource efficient as compared topassing the entire GA population from module to module. Asshown via three case studies, a hardware-based implementa-tion of the proposed architecture that exploits the processingcapability of the FPGA can achieve convergence at rates abovethe typical 10 Hz update frequency of an autopilot system.

This paper is organized as follows. Section II gives furtherdetails of related work and highlights the main difference inour approach. Section III presents our proposed FPGA-basedUAV path planning system, including descriptions of the archi-tecture, system operation, execution flow, and communication.Section IV provides hardware implementation details for atarget Xilinx Virtex-4 FPGA development platform (availableat the High Performance Computing Department, QueenslandUniversity of Technology). Choices for GA population char-acteristics and other parameters appropriate to the availableresources on the target FPGA are presented, along with detailsof in-hardware implementations of various pathplanner mod-ules. Section V presents the results of empirical case studies toverify the effectiveness of the proposed FPGA-based pathplan-ner for a specific UAV over a sample 3-D terrain. The chosenUAV is an unmanned 1 m length helicopter with a limited 5 kgpayload capacity [available at the Australian Research Centrefor Aerospace Automation (ARCAA)], while the terrain is a512 m3 environment derived from light-detection and ranging(LIDAR) data. Section VI concludes with a brief summary ofthe applicability and current research direction.

II. Background and Related Work

A. UAV Path Planning

Path planning can be defined as the framework employed todetermine flight plans for UAVs traversing from one locationto another [7].

B. Previous FPGA Implementations for Path Planning

FPGAs are and have been used for a range of engineeringapplications [16]; however, their influence in path planningapplications is recent and limited [15], [17]–[23].

Alliare et al. [15] demonstrated that the possibility ofincreased UAV navigation autonomy can be achieved byinstantaneous on-the-fly replanning via the implementation ofa path planning GA on an FPGA for algorithm acceleration.They argue that GAs produce higher-quality solutions ascompared to deterministic algorithms but are at a disadvantage

due to their extensive computational overhead that is inevitablyinherited by the GA’s population-based metaheuristics opti-mization approach. Their path planning GA implementationdetails were partially set according to the work done byCocaud in [14] involving a customized GA specifically forUAV task allocation and path generation. Their results indicatethat some mechanisms of the GA running on an FPGA can besped up by factors of thousands. However, their research waslimited to cosimulation between a CPU and an FPGA runningsimultaneously and exchanging information in a collaborativemanner.

Vacariu et al. [17] proposed an FPGA implementation ofa simple breadth-first search (BFS) algorithm [24] applied onstatic 2-D discrete environment. The BFS technique, whichhas two degrees of freedom, is based on maintaining a queueof all accessible neighbors, whereby a sequence of directionsleading to the goal point is acquired. This search algorithm iscomplete, that is to say it will find a solution if one exists, butdoes not guarantee any level of optimality or feasibility. Theirresults show execution times sped up by factors of hundreds.

Girau et al. used an FPGA to compute approximated har-monic control functions [25] for making robot navigation de-cisions. The use of harmonic functions ensures that generatedtrajectories avoid local optima in cluttered and concaved envi-ronments [26]. They argued that the main advantage of theirwork was not the speedup, as real-time computational speedcan be easily reached by software-coded harmonic controlfunctions. Instead, they highlighted the potential of embeddingFPGAs for online processing needs on low-powered mobilerobots.

Sudha and Mohan [19] designed an FPGA-acceleratedpathplanner based on the Euclidean distance transform [27]of a captured image from an overhead camera. Priya et al.[20] customized FPGA architecture for path planning basedon revised simplex method [28] applied on a preconstructedvisibility graph [29]. Sudha and Mohan argued that their pathplanning solution is process complete versus the work ofPriya et al., as a raw binary image of environment is directlyprocessed in the hardware rather than a metamodeled nodes-and-edges visibility graph. On the other hand, results fromPriya et al. were in factors of microsecond as compared tomillisecond from Sudha and Mohan; the former was interestedin ballistic missiles application, whereas the latter was directedtoward ground-based robot navigation.

Hachour [21] proposed an FPGA-based path planning GAmethod for ground-based mobile robots. However, the pathplanning GA concept and the actual hardware implementationwere not described in any detail, and the results and validatedfunctionality were not reported.

Huang et al. [22] proposed a hardware–software codesignedparallel elite genetic algorithm (PEGA) for ground mobilerobot path planning in a static environment. Their FPGA-basedPEGA architecture consisted of two path planning GA [30]of which the evolutionary-influenced selection, crossover, andmutation modules operate concurrently. Elitism is preservedvia a migration module that periodically exchanges the corre-sponding two best members into the selection pool after a pre-defined number of generations. However, the computationally


TABLE I

Existing Literature on FPGA Implementations of Path Planning Algorithms

Work Path Planning Algorithm Environment Sampling Method Platform Model[15] Modified GA [14] Hybrid octree knowledge base [14] Xilinx Virtex-II Pro XC2VP30[17] BFS algorithm [24] Sukharev grid [33] Xilinx Virtex-II Pro[18] Harmonic potential trajectory control [25] Sukharev grid [33] Xilinx Virtex-II XC2V6000[19] Euclidean distance transform [27] Euclidean distance mapping [34] Xilinx Spartan-3 XC3S1500L[20] Revised simplex method [28] Visibility graph [29] Xilinx Virtex-II XC2V6000[21] Motion-based GA [21] – Xilinx XC4000[22] Modified GA [30] Sukharev grid [33] Altera Stratix EP1S10F780C6[23] MP [31] Skeleton map [32] Xilinx Virtex-5 XC5VLX110TProposed Modified GA Sukharev grid [33] Xilinx Virtex-4 XC4VLX200

dominant fitness-evaluation function was executed sequentiallyon an embedded processor.

Schmidt and Fey [23] implemented marching pixels (MPs)[31] applied on a skeleton map [32] on an FPGA for pathplanning. MP is akin to artificial ants behaving as modeledby cellular automata, where one pixel of an image is rep-resented by a 2-D coordinate on the map. Their results showcomputational effectiveness in factors of millisecond for imageresolutions up to 1024×800. However, their approach inheritsthe two main disadvantages from the nature of SM sampling:the resulting path solution is nonoptimal and the sharp turningedges are probable.

Although the above research works summarized in Table Ihave established the concept of FPGA implementations forspeeding up different computationally intensive path planningalgorithms, this paper instead aims to contribute a completelyembedded UAV path planning system inclusive of constraintsvia UAV, environment, and mission profiles. Note that for thispaper, the UAV was the designated robotic platform but this isnot expected to be restrictive. Furthermore, unlike prior worksthat were limited to a 2-D model, except for [15], our paperconsiders the real-world aspects of a 3-D model.

III. Proposed FPGA-Based Path Planning System

A. Path Planning Constraints and Execution

Here we consider path planning in the context of an overallconstrained process. A diagram illustrating our approach isshown in Fig. 1. Flight constraints are segregated and handledseparately with the aim of making the overall path planningarchitecture more easily generalizable and adaptable for dif-ferent UAV, environment, or mission configurations.

The environment profile proposed here contains terrain-specific information by which the path planning algorithm isconstrained. Note that no restriction on the source of datacontained therein is intended for this or the other profiles.Similarly, in-flight data refresh of one or more profiles is notexcluded. For example, static data for FPGA upload could betransmitted from the base station, while dynamic data could begenerated by on-board cameras, sensors, or auxiliary UAVs.

The UAV profile defines the aircraft performance constraintsof the targeted UAV platform, such as minimum and maximumvelocity, maximum fuel capacity, and turning radius. Similarly,the mission profile includes all desired mission characteristics,

Fig. 1. Constraints associated with a typical UAV path planning process.

such as starting and ending coordinates, flight boundaries,elevation deviation, and maximum allowed mission time.

Fig. 1 also illustrates a basic difference between autonomousand nonautonomous UAV flights. In nonautonomous opera-tion, a human operator would verify the feasibility of thegenerated path solution and approve its execution. The pro-posed FPGA-based architecture instead aims to provide real-time solutions of practical utility for increasing the levelof autonomy and confidence of the system, hence reducingor even eliminating the need for intervention by a humanoperator. This is useful in tedious missions (such as samplingand inspection).

B. Architecture

The architecture for the proposed FPGA-based path plan-ning design is based on an application-specific GA charac-teristic recommended by Cocaud [14] for flight path plan-ning. Briefly, the GA is a stochastic optimization methodthat iteratively generates improving candidate solutions usingadaption techniques inspired by natural evolution, such asnatural selection, recombination or crossover, mutation andinheritance, fitness evaluation, and so forth [35], [36]. Elitismis included to prevent the loss of beneficial solutions duringthe evolutionary cycle. Note also that here the usual GAiterative process has been modified to reinitialize parts of thepopulation diversity, if necessary, to counteract any tendencytoward premature convergence. Pseudocode of the modified


Fig. 2. Pseudocode of modified GA for the pathplanner.

GA used here is shown in Fig. 2. The various evolutionaryoperations are customized specifically for a path planning task,details of which will be elaborated below.

A schematic of the proposed FPGA-based path planningarchitecture is illustrated in Fig. 3. The design is intended tofit into a single FPGA and includes modules correspondingto typical GA tasks, where the functionality of each modulecan be set according to the algorithmic requirements of thespecific GA under consideration.

C. Overall System Operation

Overall, the driving component of the FPGA-based pathplanning system shown in Fig. 3 is the control unit (CU)that monitors the evolutionary process throughout the entireoperation. Random number generators modeled by cellularautomata technique [37] are used for generating a sequenceof pseudorandom numbers. Block random-access memories(RAMs) in the FPGA are used for storing the parent andoffspring populations, as well as the UAV, environment, andmission profiles. The initial and subsequent populations arethen evolved based on this information.

Population of chromosomes are stored in the parent andoffspring memories. Each chromosome is made up of onepossible path solution and its associated fitness (i.e., collisionand distance costs for the UAV to traverse the given environ-ment between designated start and end waypoints). An on-module memory interface is provided by the 6-to-1 MUX forallowing all modules to read and write the parent and offspringmemories.

The decoder is used for converting the bitstream format ofthe best chromosome into a meaningful representation for theexternal output interface. Two inputs that drive the FPGA-based planner are the clock signal and the activate signal. Theclock signal is connected to the embedded global clock of theFPGA and the activate signal is connected to an input externalto the FPGA. The best chromosome within the parent memoryis connected to the output allowing a best path solution to beconstantly available.

The initial population module (IPM) is used for generatinga population of candidate solutions based on the output fromthe random number generator. The selection module (SM) isused for applying selection pressure on the parent populationto populate a mating pool of useful chromosomes. The geneticoperation module (GOM) is used for adaptively altering thechromosomes in the mating pool. The evaluation module

(EM) is used for evaluating the altered chromosomes. Thepopulation update module (PUM) is used for updating thenext generation of parent population with useful chromosomesamong the parent population and the newly generated offspringpopulation. The premature convergence module (PCM) is usedfor monitoring the gene diversity of the parent population andsignifies a possible premature convergence when diversity islost early in the generational cycle.

D. Iterative Execution Flow and Communication

The flow of execution and communication between theindividual units of the FPGA-based pathplanner is now de-scribed. Note that during the evolution phases, processes ineach module are handled concurrently.

To begin the FPGA-based path planning process, an activatesignal is received, initiating the IPM to generate, influencedby flight parameters, such as minimum and maximum UAVelevation and a set of random path solutions that are evaluatedinternally and stored in the parent memory. This completes theinitial setup of the FPGA-based planner.

To commence the next iteration of the EA process, theIPM notifies the CU that the FPGA-based planner is readyto begin execution. The SM exercises a selection process onthe parent memory and populates the offspring memory witha mating pool of elected chromosomes. The GOM, whichconsists of the genetic crossover and mutation operations,starts genetic operation on the offspring memory, creatingnew chromosomes. Once completed, the genetically alteredchromosomes are updated back into the offspring memory. TheEM evaluates the feasibility and fitness of new chromosomesgenerated by the GOM. Upon completion, the EM updatesthe fitness information within each chromosome and sendsthe evaluated chromosomes back into the offspring memory.The PUM sorts and updates the parent memory for the nextgeneration with elites from among the parent and the offspringmemory. The PCM monitors the parent memory for prematureconvergence and triggers a reinitialize signal, if necessary.Finally, the CU excludes the IPM in the next evolution cyclesuntil the reinitialize signal is activated.

The above iterative steps are repeated endlessly. An in-dependent decoder transmits out the optimized flight pathsolution at every clock cycle, this being the best chromosomedecided through the fitness sorting PUM. The GA run is neverceasing, hence it is always trying to improve its current bestpath. The system only restarts when the activate signal istriggered again. Such a scenario may occur, e.g., when theUAV has reached the end waypoint or new environment ormission profiles are uploaded. Effectively, the planning of alonger journey across a dynamic environment would be carriedout in a stepwise manner.

IV. Hardware Implementation Details

To explore the feasibility of the proposed design archi-tecture, an implementation of the proposed FPGA-basedpathplanner in synthesizable very-high-speed integrated-circuithardware description language (VHDL) was undertaken tar-geting an available development platform containing a Xilinx


Fig. 3. Schematic of the FPGA-based pathplanner architecture.

Fig. 4. State diagram of the CU.

Virtex-4 LX200 (XC4VLX200-11FF1513) FPGA processor.This platform was used to explore implementation issues suchas the population characteristics and extent of parallelismpossible within the design, subject to various FPGA hardware-specific constraints including the programmable logic re-sources available on the device. The implementation of theFPGA-based planner requires application of the GA pop-ulation characteristics and operations specifically for pathplanning. As shown in Fig. 3, selection, genetic operation,evaluation, and update operation are involved and requirespecification in the iterative GA process. Implementation de-tails of the various modular elements and the GA populationcharacteristics are briefly described below.

A. Implementation-Specific Design

1) Encoding of GA Parameters: One of the first designdecisions is determining the encoding of the parameters asthis will directly affect, for instance, usage of available re-

TABLE II

Encoding of Each Chromosome for the Pathplanner

Parameter No. of Bits Integer Range

Transitional waypoint 1.X 9 [0, 29 − 1]

Transitional waypoint 1.Y 9 [0, 29 − 1]

Transitional waypoint 1.Z 9 [0, 29 − 1]










Evaluation cost 32 [0, 232 − 1]Total no. of bits 140

sources on the target Virtex-4 FPGA and also enhance orhinder the computational time. In view of this, populationchromosomes were chosen here to correspond to single-pathsolutions comprising four transitional waypoints, excludingthe start and end waypoints that are initialized and storedseparately in the mission profile module. Each transitionalwaypoint is characterized by its three spatial coordinates X,Y , and Z. The latter were chosen to be 9 bit wide forthe chromosomes and for the 3-D terrain map data storedseparately in the environment profile module. The parent oroffspring size and the number of transitional waypoints for allpath solutions are not subjected to change during the entireevolutionary process. It was found through experimentationthat a path solution with around three to six transitionalwaypoints provided good solutions. The bits encoding for theparameters of each chromosome and associated cost function(computed in the EM) is given in Table II.


Fig. 5. General case for the crossover operation.

Fig. 6. General case for the global perturb operation.

2) FSM-Based Approach: The sequential iterative processof the GA is mapped onto a parallel executed digital logicsystem by constituting sequential logic circuits through theuse of finite-state machines (FSMs). The FSM is establishedas the backbone of all the modules except the memory blocks.The state diagram of the CU is shown in Fig. 4; the rest ofthe modules are built on this principle.

3) 6-to-1 MUX: The 6-to-1 MUX interface to the parentand offspring memories allows for all the modules to readthe entire list of path solutions and overwrite the originalcontents of the underlying block RAM with the list of updatedpath solutions. As compared to passing the entire populationfrom module to module, the memory interface does requiremore clock cycles to retrieve population information. However,handling the population through a memory interface reducesthe amount of resource utilization. The tradeoff for additionalclock cycle as to high resource utilization was preferred.

4) Parent and Offspring Memories: The parent and off-spring memories are implemented using the available FPGAblock RAM. As such, there is no shared memory externalto the FPGA-based path planning system. As a compromisebetween available FPGA resources and model complexity,each of the parent and offspring memories was fixed to store32 population chromosomes (i.e., path solutions).

5) Control Unit: The CU operates as an FSM that monitorsthe evolutionary process throughout the entire operation. Thestates and conditions are illustrated in Fig. 4.

6) Initial Population Module: Initially, the IPM generates32 path solutions using randomly generated 9-bit binary stringsto initialize each of the transitional waypoint componentslisted in Table II. Subsequently, when the reinitialize condition

Fig. 7. General case for the local perturb operation.

Fig. 8. General case for the delete operation.

Fig. 9. General case for the swap operation.

is met, the IPM then preserves the current best chromosomeand regenerates 31 random path solutions. Note that therandomly generated initial population is generally zigzaggedand overlapping in nature.

7) Selection Module: Selection involves the identificationof chromosomes from the parent memory to undergo crossover


and mutation. Tournament selection pressure is instituted withthe fitter of two randomly chosen chromosomes flagged as thetournament winner. For this paper, the SM is composed of 32identical processing units that exploits the parallel processingcapabilities of the FPGA by operating in parallel. Each unitrandomly selects two chromosomes from the parent memoryfor tournament selection where the winner is sent to theoffspring memory.

8) Genetic Operation Module: The genetic operationconsists of two types of operators: crossover and mutation.For crossover, all transitional waypoints after a randomlychosen splitting point of the path are truncated and swappedbetween two randomly selected path solutions. This opera-tion encourages exploitation of useful information from twochromosomes. The operation is illustrated in Fig. 5 for thepresent implementation involving four intermediate waypoints.For mutation, randomly selected path solutions are subjectedto global perturb mutation, local perturb mutation, deletemutation, and swap mutation to promote exploitation of thesearch space with the expectation of speeding-up convergenceto a global optimum (as represented in Figs. 6–9). The globaland local perturb mutation are designed to induce smallperturbation in a chromosome. Since the number of transitionalwaypoints is fixed at four, the delete mutation simply shiftsa selected point spatially to the middle of a straight lineconnecting the preceding and following points. The swapmutation randomly picks two points and swaps their position.

For this paper, the GOM is internally configured withcrossover and mutation operations to be performed on all chro-mosomes of the offspring memory. The GOM is composedof 24 identical crossover units (i.e., 75% of the offspringsize) and eight mutation units (i.e., 25% of the offspringsize). The eight mutation units consists of two global perturbmutation units, two local perturb mutation units, two deletemutation units, and two swap mutation units. Notably, allcrossover and mutation operations for a single generation areconducted in parallel. The GOM generates a variety of parentalcombinations to produce 32 candidate path solutions.

9) Evaluation Module: The fitness of each chromosomeof the offspring is assessed based on constraints defined inthe profiles such as feasibility and shortest distance. The EMevaluates the feasibility of the 32 new candidate path solutionsand generates a new evaluation cost value for each one ofthem. The evaluation operations for a single generation areconducted in parallel. Additional constraint functions, such asvehicle kinematics, can be modularly included here into theEM. The inclusion of problem-specific constraints relating tothe UAV, environment, and mission profiles will be addressedin the case studies in Section V.

10) Population Update Module: The population is updatedusing an elitist approach, where the selection of the best pathsolutions from the parent and offspring memories are retainedand the remaining more inferior chromosomes are overwrittenby the next generation.

The PUM concatenates the parent and offspring memoriesand sort them based on their fitness. Thereby, the new parentmemory that is ready for subsequent evolutionary cyclesconsists of a mix of surviving chromosomes from previous

parent memory and those which are benefited from the geneticoperations.

11) Premature Convergence Module: The PCM is madeof comparators that monitor the parent memory for prematureconvergence and triggers a reinitialize signal, if necessary.Premature convergence occurs when there is a loss of ge-netic diversity within the population, causing the evolutionarysearch algorithm to get trapped in local optima in the earlystages of the evolutionary process. The reinitializing of theparent memory encourages the evolutionary process to recoverwith the reintroduction of new randomly generated population.

B. Synthesis Details

The design was synthesized using the Xilinx ISE softwarewith the Xilinx Virtex-4 LX200 as the target device and thedesign goal was set to balanced. A balanced design impliesthat no optimization for speed or utilization of FPGA resourceswas considered. Once the design was synthesized successfully,it was then compiled and built for implementation. Thisprocess consists of translating, mapping, placing, and routingof the signals. For the design implementation process, nopartition was specified and the design was translated andmapped successfully. All signals were placed and routedsuccessfully as well, and all timing constraints were met.Thirty-two percent of the logic slices on the device wereutilized. The overall FPGA design had a maximum operatingfrequency of 83 MHz.

V. Case Study Experiments and Results

A. Experiments

Three case studies were performed to verify the effective-ness of the proposed FPGA-based path planning system. Thefirst case study is on an empty environment profile, which teststhe basics of the algorithm with the expectancy of a straight-line prediction for the optimal path between the start and endwaypoints. To further test and verify the predictive capabilitiesof the algorithm, the second and third case studies were on asimulation environment 512 m high×512 m long×512 m wide.The second case study did not set any maximum elevation inthe mission profile, whereas the third constrained the UAVto a maximum elevation of 5 m below the highest peak. Fivesimulation runs are executed for each case study. A typicalautopilot system has an update frequency of 10 Hz [38].Therefore, it is essential for the time of convergence to befaster than the 100 ms threshold. For all three case studies,the start and end waypoints are kept to be identical. Theseexamples are illustrative of an air-sampling biosecurity missionor a remote-sensing mission [39], [40].

The targeted UAV platform for the case studies was anautonomous helicopter measuring 0.5 m high and 1 m long(available from the ARCAA). The UAV profile was set to arotary wing UAV so that kinematic constraints were assumedto be negligible.

The process used for generating the map data for use in theenvironment profile module is as follows. LIDAR technologyprovided the 3-D elevation map that was constructed into a


TABLE III

Encoding of Associated Cost

Parameter No. of Bits Integer Range

Collision cost 8 [0, 28 − 1]

Distance Cost 24 [0, 224 − 1]Total no. of bits 32

Fig. 10. Case study one.

lookup table (LUT) representation through the Sukharev grid[33] sampling theorem. The LUT can be seen as an X-by-Y matrix, with the referenced element corresponding to theelevation Z at that specific coordinate. The size of the LUT is2.25 MB. The map data is within 1 m resolution, thereby eachpixel is able to accommodate the rotary wing UAV withoutrequiring any rescaling.

For these case studies, a simple fitness function was usedthat incorporated only a collision cost and distance cost (seeTable III). The former relates to the number of collision pointsalong the path solution. The latter relates to the Euclideandistance of the path solution inclusive of the start and endwaypoints. The cost returned by the fitness function wasevaluated by concatenating the binary 8-bit representation ofthe collision cost before the 24-bit distance cost to arrive at aresultant 32-bit score.

B. Results

Fig. 10 shows the results for case study one with theexpected results of a straight line. It took 18 generations forthe algorithm to reach an absolute convergence, after whichno better path solutions were found. Fig. 11 shows the resultsfor case study two with the path initially climbing over thefirst mountainous region and subsequently curving toward theend waypoint. For this case study, the algorithm took 282generations for convergence. Fig. 12 shows the results forcase study three with maximum elevation included into themission profile. The path solution now deviates around themountainous region and continues toward the end waypoint.Convergence was achieved at 527 generations.

Table IV shows the results of the average computationaltime required for convergence. From the results, it can be seenthat the algorithm takes longer to converge as the complexityof the task increases. Note that the output of the path planningarchitecture, a series of transitional waypoints, is intended tobe coupled to an autopilot system via an appropriate data

Fig. 11. Case study two.

Fig. 12. Case study three.

TABLE IV

Computational Time Results for the Case Studies

Generation AverageCase Study At Convergence Convergence TimeCase study one 18 2.7 msCase study two 282 21 msCase study three 527 47 ms

transformation, although that has not been implemented here.A typical autopilot has an update frequency of 10 Hz; thus, itis essential that the results from the path planning module inall case studies must be output under 100 ms. All case studiesare able to meet the 100 ms threshold.

VI. Conclusion

In this paper, an autonomous GA-based UAV pathplannerwas developed with all modules of the proposed architectureentirely implemented on a single FPGA. In addition, all theterrain data and flight constraints were stored on the FPGA inseparate UAV, environment, and mission profiles. The designarchitecture, operation, execution flow, and communicationas well as implementation issues arising from the choiceof FPGA configurable hardware, were described in detail.Implementation targeting a Xilinx Virtex-4 FPGA develop-ment platform was achieved for a population size of 32,where each chromosome corresponds to a single path solutionwith four transitional waypoints between the start and endwaypoints. Results of case studies for a small 1 m long UAVhelicopter with a 512 m3 environment derived from LIDAR


data demonstrated the ability of the FPGA-based pathplannerto generate feasible solutions with performance that can meetthe 10 Hz update frequency of a typical autopilot system. Thispaper supported the use of an FPGA as a suitable platformfor flight-constrained autonomous UAVs. Although this paperfocused on autonomous UAV applications, our approach mayhave the potential to be more widely applicable in hardwaresystems that also require on-board, real-time optimizationtechniques.

Future work will involve testing the limitations and bound-aries by, e.g., increasing the complexity of the UAV andmission profiles (e.g., fixed-wing UAV kinematics, airspacerestriction, and number of transitional waypoints), so thatthe whole FPGA-based UAV path planning algorithm canbe verified as suitable for real-world applications. Also forconsideration in future work is an examination of the reconfig-uration capabilities of the FPGA, which could allow inclusionof other functions required for fully autonomous operationwithout compromising on-board path planning capabilities.

Acknowledgment

The authors would like to thank the High PerformanceComputing and Research Support Group, Division of TILS,Queensland University of Technology, Brisbane, Australia, forproviding the computational resources and services used inthis paper. The authors would also like to acknowledge theCooperative Research Centre for Spatial Information, Carlton,Australia, for their help with the LIDAR data used in this paperand also the Cooperative Research Centre for National PlantBiosecurity, University of Canberra, Bruce, Australia, for itssupport.

References

[1] J. Kok, L. F. Gonzalez, R. Walker, N. Kelson, and T. Gurnett, “Asynthesizable hardware evolutionary algorithm design for unmannedaerial system real-time path planning,” in Proc. Australasian Conf.Robot. Automat., Dec. 2010, pp. 1–8.

[2] “U.S. army roadmap for unmanned aircraft systems 2010-2035,” Armyand Land Forces News, U.S. ARMY, Apr. 20, 2010.

[3] T. Cox, C. J. Nagy, M. A. Skoog, and I. A. Somers, Civil UAV CapabilityAssessment, version 1.1. Washington D.C.: NASA, Dec. 2004.

[4] U.S. Military Unmanned Aerial Vehicles (UAV) Market Forecast 2013–2018, Tabular Analysis, Feb. 2012.

[5] H. Shi, X. Sun, C. Sun, D. Chen, and Y. An, “Research of thepath planning complexity for autonomous mobile robot under dynamicenvironments,” in Proc. 6th Int. Conf. ISDA, vol. 3. Oct. 2006, pp. 216–219.

[6] J. Leal, “Stochastic environment representation,” Ph.D. dissertation,Australian Centre Field Robot., Univ. Sydney, Sydney, Australia, 2003.

[7] I. A. McManus, “A multidisciplinary approach to highly autonomousUAV mission planning and piloting for civilian airspace,” Ph.D. disser-tation, Cooper. Res. Centre Satellite Syst., Queensland Univ. Technol.,Brisbane, Australia, 2005.

[8] B. J. Capozzi, “Evolution-based path planning and management for au-tonomous vehicles,” Ph.D. dissertation, Dept. Aeronautics Astronautics,Univ. Washington, Seattle, WA, 2001.

[9] I. K. Nikolos, K. P. Valavanis, N. C. Tsourveloudis, and A. N. Kostaras,“Evolutionary algorithm based offline/online path planner for UAVnavigation,” IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 33, no. 6,pp. 898–912, Dec. 2003.

[10] C. Zheng, L. Li, F. Xu, F. Sun, and M. Ding, “Evolutionary route plannerfor unmanned air vehicles,” IEEE Trans. Robot., vol. 21, no. 4, pp. 609–620, Aug. 2005.

[11] C. W. Zheng, M. Y. Ding, and C. P. Zhou, “Real-time route planningfor unmanned air vehicle with an evolutionary algorithm,” Int. J. Patt.Recog. Artif. Intell., vol. 17, no. 1, pp. 63–81, Feb. 2003.

[12] D. Jia and J. Vagners, “Parallel evolutionary algorithms for UAV pathplanning,” in Proc. AIAA 1st Intell. Syst. Tech. Conf., Sep. 2004, pp.1–12.

[13] G. Erinc and S. Carpin, “A genetic algorithm for nonholonomic motionplanning,” in Proc. IEEE Int. Conf. Robot. Automat., Apr. 2007, pp.1843–1849.

[14] C. Cocaud, “Autonomous tasks allocation and path generation ofUAV’s,” M.S. thesis, Dept. Mech. Eng., Univ. Ottawa, Ottawa, ON,Canada, 2006.

[15] F. C. J. Allaire, M. Tarbouchi, G. Labonte, and G. Fusina, “FPGAimplementation of genetic algorithm for UAV real-time path plan-ning,” J. Intell. Robot. Syst., vol. 54, no. 1–3, pp. 495–510, Mar.2009.

[16] P. H. W. Leong, “Recent trends in FPGA architectures and applications,”in Proc. 4th IEEE Int. Symp. Electron. Des., Test Applicat., Jan. 2008,pp. 137–141.

[17] L. Vacariu, F. Roman, M. Timar, T. Stanciu, R. Banabic, and O. Cret,“Mobile robot path planning implementation in software and hardware,”in Proc. 6th WSEAS Int. Conf. Signal Process., Robot. Automat., 2007,pp. 1–6.

[18] B. Girau and A. Boumaza, “Embedded harmonic control for dynamictrajectory planning on FPGA,” in Proc. IASTED Int. Conf. Artif. Intell.Applicat., 2007, pp. 244–249.

[19] N. Sudha and A. R. Mohan, “Design of a hardware accelerator forpath planning on the Euclidean distance transform,” J. Syst. Architect.,vol. 54, no. 1–2, pp. 253–264, 2008.

[20] T. K. Priya, P. R. Kumar, and K. Sridharan, “A hardware-efficientscheme and FPGA realization for computation of single pair shortestpath for a mobile automaton,” Microprocessors Microsyst., vol. 30, no.7, pp. 413–424, Nov. 2006.

[21] O. Hachour, “A genetic−FPGA algorithm path planning of anautonomous mobile robot,” in Proc. 10th WSEAS Int. Conf. Math.Methods, Computat. Tech. Intell. Syst., 2008, pp. 66–71.

[22] H.-C. Huang, C.-C. Tsai, and S.-C. Lin, “SoPC-based parallelelite genetic algorithm for global path planning of an autonomousomnidirectional mobile robot,” in Proc. IEEE Int. Conf. SMC, Oct.2009, pp. 1959–1964.

[23] M. Schmidt and D. Fey, “An optimized FPGA implementation for aparallel path planning algorithm based on marching pixels,” in Proc.Int. Conf. Reconfigurable Comput. FPGAs (ReConFig), Dec. 2010, pp.442–447.

[24] T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction toAlgorithms. New York: MIT Press, 1990.

[25] S. Akishita, S. Kawamura, and K. Hayashi, “Laplace potential for mov-ing obstacle avoidance and approach of a mobile robot,” in Proc. Japan-USA Symp. Flexible Automat., Pacific Rim Conf., 1990, pp. 139–142.

[26] J. O. Kim and P. K. Khosla, “Real-time obstacle avoidance usingharmonic potential functions,” IEEE Trans. Robot. Automat., vol. 8, no.3, pp. 338–349, Jun. 1992.

[27] N. Sudha, S. Nandi, and K. Sridharan, “Cellular architecture forEuclidean distance transformation,” Comput. Digital Tech., vol. 147,no. 5, pp. 335–342, Oct. 2000.

[28] S. Morgan, “A comparison of simplex method algorithms,” M.S. thesis,Graduate School, Dept. Comput. Inform. Sci. Eng., Univ. Florida,Gainesville, FL, 1997.

[29] T. Lozano-Perez and M. A. Wesley, “An algorithm for planningcollision-free paths among polyhedral obstacles,” Commun. ACM,vol. 22, pp. 560–570, Oct. 1979.

[30] I. Al-Taharwa, A. Sheta, and M. Al-Weshah, “A mobile robot pathplanning using genetic algorithm in static environment,” J. Comput.Sci., vol. 4, no. 4, pp. 341–344, 2008.

[31] D. Fey and D. Schmidt, “Marching pixels: A new organic computingprinciple for high speed CMOS camera chip,” in Proc. ACM, 2005, pp.1–9.

[32] J. Barraquand, B. Langlois, and J. C. Latombe, “Numerical potentialfield techniques for robot path planning,” IEEE Trans. Syst., ManCybern., vol. 22, no. 2, pp. 224–241, Mar.–Apr. 1992.

[33] A. G. Sukharev, “Optimal strategies of the search for an extremum,”U.S.S.R. Computat. Math. Mathemat. Phys., vol. 11, no. 4, pp. 910–924,1971.

[34] P. E. Danielssona, “Euclidean distance mapping,” Comput. GraphicsImage Process., vol. 14, pp. 227–248, Feb. 1980.

[35] Z. Michalewicz, Genetic Algorithms + Data Structures = EvolutionPrograms, 3rd ed. New York: Springer-Verlag, 1996.


[36] D. E. Goldberg, Genetic Algorithms in Search, Optimization, andMachine Learning. Boston, MA: Addison-Wesley, 1989.

[37] M. Serra, T. Slater, J. C. Muzio, and D. M. Miller, “The analysis ofone-dimensional linear cellular automata and their aliasing properties,”IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 7,pp. 767–778, Jul. 1990.

[38] Y. Kang and J. Hedrick, “Linear tracking for a fixed-wing UAV usingnonlinear model predictive control,” IEEE Trans. Contr. Syst. Technol.,vol. 17, no. 5, pp. 1202–1210, Sep. 2009.

[39] L. F. Gonzalez, D.-S. Lee, and R. A. Walker, “Optimal mission pathplanning (MPP) for an air sampling unmanned aerial system,” in Proc.Australasian Conf. Robot. Automat., 2009, pp. 1–9.

[40] F. Gonzalez, P. P. Narayan, M. P. Castro, and L. Zeller, “Developmentof an autonomous unmanned aerial system to collect time-stampedsamples from the atmosphere and localize potential pathogen sources,”J. Field Robot. Special Issue: Safety, Security, Rescue Robot., vol. 28,no. 6, pp. 961–976, Oct. 2011.

Jonathan Kok received the B.E. (Hons.) degree inelectrical engineering from the Queensland Univer-sity of Technology, Brisbane, Australia, in 2010. Heis currently pursuing the Ph.D. degree with the Aus-tralian Research Centre for Aerospace Automationand the School of Engineering Systems, QueenslandUniversity of Technology.

His current research interests include optimizationproblems and algorithms, specifically involving evo-lutionary algorithms and field-programmable gatearrays.

Luis Felipe Gonzalez received the B.Sc. degree inmechanical engineering from Universidad PontificiaBolivariana, Medellin, Colombia, in 1997, and thePh.D. degree in multidisciplinary design optimiza-tion methods for unmanned aerial vehicle (UAV)systems from the University of Sydney, Sydney,Australia, in 2006.

He is currently a Lecturer with the QueenslandUniversity of Technology and the Australian Re-search Centre for Aerospace Automation (ARCAA),Brisbane, Australia. After he joined ARCAA in

2006, he directed his attention to enabling technologies for flight control andoptimization of civilian UAV systems. He has developed six operational UAVsand has written 18 journal papers and more than 35 peer-reviewed papers onevolutionary algorithms and optimization.

Neil Kelson received the B.Math. (Hons.) degreefrom the University of Newcastle, Newcastle uponTyne, U.K., in 1984, the GradDipEd degree fromthe University of Queensland, Brisbane, Australia,in 1997, and the Ph.D. and MinfTech degrees, bothfrom the Queensland University of Technology, Bris-bane, in 2001 and 2007, respectively.

He is currently a User Services Manager with theHigh Performance Computing and Research SupportGroup, Queensland University of Technology, wherehe is involved in extensive consultation or collabo-

ration with researchers and research groups regarding effective utilization ofadvanced computing tools and technologies. His current research interestsinclude engineering computational fluid dynamics, code optimization, andparallelization, and the use of field-programmable gate arrays for high-performance embedded and supercomputing applications.

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