Calculation of Cycle Lengths In Higher-Order MASH DDSMs with
Constant Inputs
Brian Fitzgibbon and Michael Peter Kennedy Department of
Microelectronic Engineering and Tyndall National Institute
University College Cork, Cork, Ireland Email:
[email protected]@ucc.ie
Abstract-A mathematical analysis is performed to investigate the
periodic behavior of Multi stAge noise SHaping (MASH) Digital
Delta-Sigma Modulators (DDSMs). The analysis is performed on
fourth- and fifth-order MASH DDSMs with an odd initial condition on
the first stage and all other states initially zeroed. We prove
that the maximum cycle length for the fourth- and fifth-order MASH
DDSM is 2N+2 where N is the wordlength of the modulator. In the
case of fourth-order modulators, the maximum cycle length can be
achieved when odd digital inputs are plied. In the case of
fifth-order modulators, the cycle length is 2 +2 for all digital
inputs.
I. INTRODUCTION A DDSM is a discrete-time system whose function
is to re
quantize a discrete-amplitude input signal coarsely to produce a
lower resolution output signal. This requantization process takes
place within a negative feedback loop such that the power of the
resulting quantization noise is suppressed within some signal band
of interest [1]. Ideally the quantization noise introduced by the
DDSM is white and uncorrelated with the DDSM's input sequence. In
practice, however, the quantization error often forms short and
repeating patterns, giving rise to spurious tones in the output
spectrum.
Two classes of techniques have been developed to whiten the
quantization noise: stochastic and deterministic. Stochastic
techniques include the use of LSB dithering [2]-[4] and timevarying
noise transfer functions [5]. Their goal is to make the
quantization noise asymptotically white and indpendent of the
modulator's input, thereby eliminating spurious tones in the output
spectrum. Deterministic techniques include the setting of
predefined initial conditions [6]-[8], using prime modulus
quantizers [9] and architectural modification [10], [11]. The goal
of these methods is to maximize the cycle length of the
quantization error signal, thereby causing the quantization power
per tone to be minimized.
In this work, we focus on a deterministic technique, namely
setting predefined initial conditions. It has been proven that an
irrational initial condition imposed on the first accumulator of a
third or higher order MASH DDSM driven by a rational DC input
guarantees a spur-free output spectrum [6]. In the case of a
fixed-point digital implementation, the authors of [6] suggested
the use of an odd number as an approximation to an irrational
initial condition. The authors of [7] performed extensive
simulations on various orders of MASH DDSMs and error feedback
modulators (EFMs) to extract an empirical design methodology based
on setting predefined initial
978-1-4244-8157 -6/1 0/$26.00 20 10 IEEE 479
conditions. They showed that an odd initial condition in the
first stage of an EFM or MASH DDSM maximises the cycle length. This
result was proven in [8] for second- and thirdorder MASH DDSMs. In
this work, we complete the proof for fourth- and fifth-order MASH
DDSMs.
II. MASH DDSM ARCHITECTURE
The basic building block of the MASH DDSM is the firstorder
error feedback modulator (EFMI) shown in Fig. 1. The input to the
modulator is a digital word with N bits. When v[n] is greater than
M (2N), the quantizer overflows and the output signal y[n] will be
1. On the other hand, when v[n] is less than M, the quantizer does
not overflow and y[n] will be o. Mathematically, we write:
x[n]
N
y[n] = { 0, 1, v[n]
Noise Cancellation Network where
x[nJ
a = 4 n + 10 b = 6n2 + 30n + 35 C = 4 n3 + 30n2 + 70n + 50 d =
3n + 6 e = 3n2 + 12n + 11.
(8)
(9)
(10) (11)
(12)
We examine the periodicity of (7) with the condition that Fig.
2. Block diagram of an zth order MASH DDSM incorporating a cascade
11 is odd. We show using two-dimensional induction that of EFMls
the numerator of the second term is divisible by 3 and
consequently that the minimum length solution for N4 must be 2M
to ensure that the second term is an integer. We rewrite
terms of the input and initial conditions as [8] the numerator
as
n kl-1 -ez[n] = (Iz + L IZ_1 + L IZ_2
kl_1=O kl-2=O k2 ) + . . . + L h + (k1 + I)X mod M,
k1=O (3)
where Iz denotes the initial condition imposed on the register
of the lth stage and X is the constant DC input. In this work, we
focus on MASH DDSMs where all initial conditions except for the
first stage are set to zero. Consequently, we can rewrite (3)
as
modM
(4)
III. FOURTH-ORDER MASH DDSM
Expanding (4) for a fourth-order MASH DDSM, we can write
-e4[n] = ( t f: f: h + (k1 + I)X) mod M (5) k3=O k2=O kl=O
Simplifying this equation yields
-e4[n] = ( (n + 1)(n + 2)(n + 3)(n + 4 ) X 2 4
(n+l)(n+2)(n+3)
I ) dM + 6 1 mo . (6) In order to find the period N4 of the
fourth-order MASH DDSM, we impose the condition -ern] = -ern + N4]
on Eq. (6), obtaining
N (Nl+aNl+bN4+cx 4 24 Nl + dN4 + e
I ) - d M + 6 1 = 0 mo , (7)
480
f(m, n) = 22m + (3n + 6)2m + 3n2 + 12n + 11, (13)
where N4 = 2m. Consider the case f(l, 1) = 4 8, which is
divisible by 3. We assume that f(k, 1) is divisible by 3 for some
positive integer k, i.e.
31(22k + 9 2k + 26), (14)
where xly denotes that x divides y. Examining f(k + 1, 1), we
obtain
f(k + 1,1) = 22k+2 + 9 2k+1 + 26
= 4 22k + 18 2k + 26
= 22k + 9 . 2k + 26 + 3 22k + 9 2k , (15)
which is divisible by 3. Next, we assume that f(h, k) is
divisible by 3 for some positive integers hand k, i.e
31(22h + (3k + 6)2h + 3k2 + 12k + 11).
Examining f(h, k + 1), we obtain
f(h, k + 1) = 22h + (3(k + 1) + 6)2h + 3(k + 1)2 +12(k+l)+11
= 22h + (3k + 9))2h + 3(k2 + 2k + 1) +12(k+l)+11
= 22h + (3k + 6)2h + 3k2 + 12k + 11
(16)
+322h+3(2k+l)+12, (17)
which is divisible by 3. It follows that f(m, n) is divisible by
3 for all positive integers m and n, and consequently that the
minimum length solution for N4 is 2M. Using a similar argument, it
can be shown that the numerator of the first term in (7) is
divisible by 6. Consequently, when the input X is odd, the minimum
length solution for N4 such that the first term is an integer is
4M.
The minimum and maximum cycle lengths for an 18-bit fourth order
MASH DDSM are illustrated using the autocorrelation function in
Figs. 3 and 4, respectively. In the case of a periodic signal, the
autocorrelation function contains peaks that are separated by the
period of the signal. The cycle length is determined by the index
with the same autocorrelation value as at index o. When the input
is even, a cycle length of
