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Novel, Four-Switch, Z-Source Three-Phase Inverter

Rbert Antal1, Nicolae Muntean1, Ion Boldea1, Frede Blaabjerg21Politehnica University of Timisoara/Department of Electrical Engineering, Timisoara, Romania

2Institute of Energy Technology, Aalborg University, DK 9220 Aalborg East, Denmarke-mail:aroberrr@yahoo.com;

Abstract-This paper presents a new z-source three phase in-

verter topology. The proposed topology combines the advan-

tages of a traditional four-switch three-phase inverter with the

advantages of the z impedance network (one front-end diode,

two inductors and two X connected capacitors). This new topol-

ogy, besides the self-boost property, has low switch count and it

can operate as a buck-boost inverter. In contrast to standard

four-switch three-phase inverter which operates at half dc input

voltage the proposed four-switch z-source inverter, by self boost-

ing, brings the output voltage at same (or higher) value as in six

switch standard three-phase inverter. The article presents the

derivation of the equations describing the operation of the con-

verter based on space vector analysis, validation through digital

simulations in PSIM and preliminary experimental results on a

laboratory setup with a dsPIC30F3011 digital signal processor.

Index Terms-z-source three-phase inverter, four switch in-

verter, shoot-through time ST, space voltage vector

I. INTRODUCTIONZ-source three-phase converters (Fig. 1) with six power

switches have been proposed recently [1] with different con-

trol strategies [3-6].

In essence they are self-boosting unidirectional dc-ac con-

verters with only six power switches (unless used in multi-level topologies [7]), which are used with some PWM strate-

gies to short-circuit (Fig. 2b) the z-source and thus produce dc

voltage boosting. In between short-circuits the same six

power switches produce the required output voltage wave-

forms.

It can be seen in Fig. 2a that during the shoot-through in-

terval the dc-link voltage 0=inV . The average dc-link volt-age is equal with the voltage across the capacitors in the z

impedance network [1]

s

STST

ST

STCCCin

T

tD

D

DVVVV =

==== ;

21

121 (1)

where DST is the shoot through duty ratio and Ts is the

switching frequency.

The self-boosting attribute of Z converters is paid for by

some voltage and current over rating. On the other hand

lower count four switch three-phase inverters with split dc-

link capacitor are characterized by half dc input voltage used

for output voltage PWM and thus a 2/1 current overrating of

switches is necessary. To alleviate this situation, while bring-

ing back full dc-link voltage utilization, a novel, four-switch

three-phase z-source converter topology is proposed in this

paper. This way the over current rating in comparison with

the six switches three-phase inverter is small, though some

notable voltage over rating remains. However this demerit

should be justified by the additional voltage buck-boosting

attributes that can be indispensable for voltage sags handling

in safety critical applications.

Among applications we enumerate here renewable dc-ac

interfacing of photovoltaic panels, fuel cells, batteries and

electric drive with frequent voltage sags. This proposed novel

inverter topology can be also used for small (1...10kW) off-

grid wind energy-electrical energy generation systems withpermanent magnet synchronous generators.

The paper is organized as follows: first the equations de-

scribing the operation of the inverter are derived, after that the

shoot-through time generation and the gating signals are pre-

sented and finally digital simulations and preliminary experi-

mental results validate the theory.

Fig. 1. Z-source three-phase inverter with six switches.

a)

b)

Fig. 2. Equivalent circuits of the Z-source network in (a) shoot through state

(b) non shoot-through state.

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II. THE PROPOSED FOUR-SWITCH Z-SOURCE THREE-PHASEINVERTER

As we could see in case of a z-source inverter with six

switches Fig. 1, 2 the voltage across the inverter bridge is

zero when the voltage boost is applied by short-circuiting at

least one of the three inverter legs. So the shoot-through state

of the inverter limits the available maximum output voltage of

the inverter [6]. Hence to fully utilize the voltage boost andto limit the voltage and current stresses of the inverter bridge

without affecting the output voltage, the placing of shoot-

through states during the zero voltage vector time intervals

(no voltage seen by the load) seems to be a practical solution

[4,6].

A. Principle of Operation

Fig. 3. Four-switch z-source three-phase inverter.

The proposed four-switch z-source three-phase inverter is

shown in fig. 3.

In essence, the novel topology shows that one of the ca-

pacitors in the Z network is split into two and the middle

point is connected to one phase of the load.This 50% voltage drawback of conventional four-switch

three-phase inverter is eliminated by the proposed four-switch

Z-source inverter because the shoot-through state produces

not only the voltage boost but it produces also an active volt-

age vector, thus generating non-zero output voltage Fig 4.

The equivalent scheme of the shoot-through state of the

proposed inverter (when all four transistor are conducting) in

Fig. 4 clearly shows that during the shoot-through state the

voltage seen by the load is equal with the voltage across ca-

pacitor C2.

Fig. 4. Shoot-through state equivalent circuit of the 4-switch z-source three-

phase inverter.

Fig. 5. Phase terminal voltages referenced to ground 0.

TABLE1SWITCHING PATTERN

T1 T2 T3 T4

V1 0 1 0 1

V2 1 0 0 1

V3 1 0 1 0

V4 0 1 1 0

VST 1 1 1 1

By averaging the voltage across one inductor during one

switching period in steady state the same relationship can be

obtained between the input dc voltage VDCand the average dc-

link voltage Vinas in (1). The average dc-link voltage is equal

with the voltage across C1or across C2and C3as for a three-

phase z-source inverter with six switches.

Before we step further into the analysis of the proposed to-

pology we make the following assumptions:

The average voltages across C2 and C3 are equalwith each other.

The front-end diode D1 is always conductingwhen the converter is in the non-shoot through

state, thus the pseudo-active state is avoided [4].

B. The Space Voltage Vectors of the Four-Switch Z-SourceThree-Phase Inverter

For the three-phase load in Fig. 3 the voltage space vector

can be defined as follows

++=

WN

j

VN

j

UNs vevevv3

4

3

2

3

2

(2)

where vUN, vVNand vWNare the instantaneous phase voltages.

With the four switches in Fig. 3 five voltage vectors can be

obtained, as in Table 1.

All voltage vectors are active voltage vectors as we will see

in the following section. Although two more shoot-through

states can be obtained by turning on T1and T2or T3and T4in

the same time, these states were neglected because the maxi-

mum current flowing through the inverter bridge would only

flow through one leg of the inverter bridge which would lead

to a bigger kVA transistor bridge. The wye connected three-

phase load terminal voltages referenced to ground are shown,

with respect to the switching pattern in Table 1, in Fig. 5.

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In order to derive the phase voltages we will consider

2; 321

CCCCC

VVVVV === (3)

where 1CV , 2CV and 3CV are the average voltages across C1,

C2 and C3 capacitors. For a symmetrical balanced wye con-nected three-phase load (Fig. 3) the phase voltages can bewritten as

( )

( )

( )000

000

000

3

1

3

2

3

1

3

2

3

1

3

2

VUWWN

UWVVN

WVUUN

vvvv

vvvv

vvvv

+=

+=

+=

(4)

Substituting 0Uu , 0Vu and 0Wu , from fig. 5, into (4) and

using the expression of the space voltage vector (2) the fivevoltage vectors can be derived as

CST

DCC

C

DCC

DCC

VV

VjVjV

VV

VjVjV

VVV

3

1

3

3

3

1

3

32

3

1

3

1

3

3

3

1

3

32

3

1

3

2

4

3

2

1

=

++

=

=

+

+=

=

(5)

The relationship between the average capacitor voltage

CV and the input dc voltage DCV can be expressed as

DCC VkV = (6)

1;21

1>

= k

D

Dk

ST

ST (7)

Rewriting (5) using (7) the voltage vectors can be derived as

( ) ( )

( ) ( )

DCST

DC

DC

DC

DC

kVV

VkjkV

kVV

VkjkV

VkV

3

1

123

31

3

1

3

1

123

31

3

1

3

2

4

3

2

1

=

++=

=

+=

=

(8)

Fig. 6. Locations of the voltage vectors in the complex plane.

Notice that in (8) the boost factor k influences the ampli-

tude as well the direction of the six voltage vectors.For k=2 the six voltage vectors in the complex plane are il-

lustrated in fig. 6.

The voltage vector generated by the shoot-through state VST

has the same amplitude and direction as the V3voltage vector.

The voltage space vector expressed in (2) can be rewritten

in the complex plane as

sss jvvv += (9)

The average voltage space vector over one switching cycle

should be equal with the sum of the five average voltage

space vectors (V1V4and VST) over one switching cycle Ts

( ) sSTSTs TVtVtVtVtVtv /44332211 ++++= (10)

where

sST Tttttt =++++ 4321 (11)

To obtain the expressions of sv and sv (9) the expres-

sions of the five voltage vectors (8) are introduced in (10)

( ) ( )( ) ( )[ ]

( )( )123

3

1233

42

3421

=

+++=

kttT

Vv

kttkttktT

Vv

s

DC

s

STs

DCs

(12)

Given (1)-(12) in this section it is possible to derive severalalgorithms that can be implemented in a digital signal proces-sor which, for a prescribed input space voltage vector,

+= sss jvvv (13)

calculate the duty ratios for the four transistors and generates

the four gating pulses.

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III. SHOOT-THROUGH PULSE IMPLEMENTATION AND PWMSIGNAL GENERATION

One easy way to generate the gating signals for the four

transistors is to use three synchronized PWM units in com-

plementary mode of a DSP with some additional circuitry.

Fig. 7. Block diagram of the PWM signal generation implementation.

Two of the three PWM generation units yield the two com-

plementary signals for the two phase legs of the inverter

bridge based on the prescribed duty ratios DV and DW. The

third PWM unit generates the ST signal from DST. The four

outputs from the two units are ORed with the ST signal thus

obtaining the PWM signals for T1T4.

Fig. 8. PWM signal waveform generation for T1, T2, T3& T4.

IV. SIMULATION RESULTSIn the first step of the validation, the proposed four-switch

z-source three-phase inverter was simulated in PSIM. The

circuit parameters were as follows

kHzf

HzfkVv

RRFCC

uFCmHLLVV

s

s

LL

DC

10

50;2;60

9.0;470

;235;4.6;90

2132

121

=

===

====

====

A three-phase wye connected RL load was used with the

following parameters

mH7.17L;mH4.18L;mH1.20L

;2.10R;6.10R;5.10R

WVU

WVU

===

===

Only open loop performance with imposed output voltage

vector amplitude, to derive commutation sequences and the

required shoot-through time for the dc-link voltage boost, was

investigated both in simulations and experiments.The simulated waveforms are shown in Fig. 9-Fig. 13.

0 0.1 0.2 0.3 0.4 0.5-4

-3

-2

-1

0

1

2

3

4

Time [s]

Current[A]

Fig. 9.Simulated load currents at start-up.

0.24 0.25 0.26 0.27 0.28 0.29 0.3 0.31-5

-4

-3

-2

-1

0

1

2

3

4

5

Time [s]

C

urrent[A]

IV

IU

IW

Fig. 10. Simulated load currents (zoom).

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0 0.1 0.2 0.3 0.4 0.520

40

60

80

100

120

140

160

180

200

Time [s]

Voltage[V]

VC1

VC3

VC2

VDC

Fig. 11. Simulated voltage waveforms across C1, C2, C3and the input dc volt-

age at start-up.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.55

5.5

6

6.5

7

Time [s]

Current[A]

IL1

IL2

Fig. 12. Simulated z-impedance inductor current waveforms IL1and IL2.

0 0.1 0.2 0.3 0.4 0.50

50

100

150

200

250

300

Time [s]

Voltage[V]

Fig. 13. Simulated instantaneous dc-link voltage Vi.

The shoot-through time was linearly increased from 0 to its

nominal value in 0.120s to avoid the high inrush current Fig.

11. In Fig. 10 it can be seen that the load currents are not

perfectly symmetrical due to the connection of phase U to the

common node of capacitors C2and C3which causes the volt-

age potential at this terminal to vary around 2CV Fig. 11.

The simulated inductor currents (which flow through both

inverter legs during shoot-through states) are shown in Fig.

12, and they are less than 150% the peak load currents (Fig.

10). The boost dc-link voltage is shown in Fig. 13 (input dc

voltage is 90V dc).

V. EXPERIMENTAL WORKA laboratory setup was built to experimentally validate the

proposed four-switch Z-source three-phase inverter. The con-

trol algorithm based on equations (1)-(12) was implementedon a dsPIC30f3010 digital signal processor from Microchip

with a clock frequency of 120MHz. The experimental wave-

forms are shown in. Fig. 14-Fig.18.

The laboratory setup data are the same as for the digital

simulations.

The experimental load currents in Fig. 14 are close to those

from digital simulations (in Fig. 10) though a bit more asym-

metric. The inverter starting experimental transients of Fig.

15-17 are similar to those obtained for same transients by

digital simulations in Fig. 11 and 9 respectively.

The test and simulation load phase current transients (Fig.

17 and Fig. 9) fit rather well; the same observation is valid for

VC2, VC3 which pulsate around input dc voltage of 90V dc.The dc-link (boosted) voltage VC1 in experiments (Fig. 15)

pulsates around 160V while in simulation is around 180V dc,

while the experimental inductor currents (Fig. 18) are smaller

than the digital simulations (Fig. 12). These discrepancies

require further insight.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07-5

-4

-3

-2

-1

0

1

2

3

4

5

Time [s]

Cur

rent[A]

IW

IV

IU

Fig 14. Experimental load currents.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.350

102030405060708090

100110120130140

150160170180190200

Time [s]

Voltage[V]

VC3

VC1

Fig. 15. Experimental voltages across C1 and C3 capacitors at start-up.

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0 0.05 0.1 0.15 0.2 0.25 0.3 0.350

10

2030

40

50

60

70

80

90

100

Time [s]

Voltage[V]

VC2

VC3

Fig. 16. Experimental voltages across C2 and C3 capacitors at start-up.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-4

-3

-2

-1

0

1

2

3

4

Time [s]

Current

[A]

IPhaseU

Fig. 17. Experimental current waveform through phase U at start-up.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

Time [s]

Current[A] IL1

IL2

Fig. 18. Experimental Z-impedance inductor current waveforms IL1and IL2.

VI. CONCLUSIONSThis paper has proposed a novel four switch z-source three

-phase inverter topology which links together the advantages

of a four switch inverter (low switch count) and a z-source

inverter (self-boost ability). The shoot-through state not only

boosts the input dc voltage but also produces an active volt-

age as well, while in case of the z-source inverter with six

switches the shoot-through state only boosts the input dc volt-age. By voltage-boost, the new four-switch z-source three-

phase inverter eliminates the need to redesign the electric

motor in terms of terminal voltage, as needed for conven-

tional four-switch split capacitor three-phase inverters. The

equations of the new converter were derived and the theory

was verified through digital simulations and experiments.

ACKNOWLEDGEMENT

This work was partially supported by the European Eco-

nomic Area (EEA) project RO 018 Improvement of the

Structures and Efficiency of Small Horizontal Axis Wind

Generators with Non-Regulated Blades.

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[3] Boldea Ion, Robert Antal, Muntean Nicolae Modified Z-Source Sin-gle-Phase Inverter with Two Switches,Proc. ISIE 2008, pp.257-263.

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