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ISDRS 2009, December 9-11, 2009, College Park, MD, USA
ISDRS 2009 http://www.ece.umd.edu/ISDRS2009
Graphene Nanoelectronics
Chun-Yung Sung
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598,
U.S.A.
Graphene, a two-dimensional (2D) material with the highest
intrinsic carrier mobility andmany desirable physical properties at
room temperature, is considered a promising material forultrahigh
speed and low power applications. [1-3] Ultra-thin body enables the
ultimately scaled-down device feasibility. (Fig. 1) Here we report
the graphene nanoelectronics progress insynthesizing wafer-scale
monolayer-controlled graphene and fabricating high-speed
grapheneFETs (GFET) with the highest value reported cut-off
frequency (fT) approaching 100 GHz.
Epitaxial growth is investigated to produce wafer-scale,
high-quality graphene. [4-5] IBMhas implemented a
decomposition-based technique with in-situ monolayer control
capabilityusing a high temperature UHV growth chamber, equipped
with low-energy electron diffractionmicroscopy (LEEM). (Fig. 2) The
in-situ LEEM provides real-time electron reflection imagesfrom the
graphene surface, allowing graphene formation via Si desorption
from the SiC surface atelevated temperature to be studied and
controlled. The system is capable of monolayer thickness
precision and 5nm lateral resolution enabling graphene synthesis
optimization. [5] A sequence ofmorphological transformations takes
place on the SiC surface cleaned by exposure to Si at 900C.Upon
further heating (1300oC), the graphene nucleates at SiC surface
steps. (Fig. 3) However,graphene epitaxial growth on SiC usually
suffers from the presence of thermal etch pits, roughmorphology and
small graphene domain sizes. We discover raising phase transition
temperaturesover wide ranges (250oC) by establishing thermodynamic
equilibrium between SiC and externalSi (disilane) vapor pressure
(10-7 Torr), dramatically improves graphene surface morphology
(Fig.4), eliminates thermal pitting and achieves large atomically
smooth terraces other than theintrinsic miscut steps, allowing
growth of 3 thick (1-2 layers) graphene uniformly across 2
SiCwafers with only monolayer variation, as confirmed by electron
diffraction, Raman spectroscopyand AFM. (Fig. 5) It is an important
advance in SiC-based large scale graphene epitaxy.
Single-layer exfoliated GFETs are fabricated to study intrinsic
transport properties. Theadhesive noncovalent interfacial layer
NO2-TMA or polymer, which was deposited onto thechemically inert
graphene surface prior to forming uniform ALD Al2O3 gate oxide
(10nm) andPd/Au top-gate, helps to minimize mobility degradation by
the suppression of extrinsic surface
phonons and screening of charged impurities. Being able to
preserve GFET mobility is a
significant improvement for advancing graphene device
technology. (Fig. 6) [7] Despite the smallon/off ratio (~10), GFETs
are ambipolar devices where the conductance minimum is denoted
asthe Dirac point. GFETs exhibit linear ID-VD without current
saturation due to the zero-bandgap.Bandgaps can be introduced by
the single-layer graphene nanoribbon (GNR) fabrication or
byapplying an electric field perpendicular to the plane of a
double-gated bilayer grapheme. (Fig. 7,8) [7-10] The gm rises
linearly with increasing VD which indicates that the GFET
cut-offfrequency can be described as fT=gm/(2C) like conventional
MOSFETs. The de-embeddedcurrent gain h21 follows an ideal -20dB/dec
slope, validating the devices FET behavior. Becauseof device
operating in the triode regime, the maximum fT increases as gate
length decreases witha 1/LG
2 dependence, rather than the conventional 1/LG scaling. (Fig.
9) [11-12]A 350-nm-gate exfloited GFET yields the highest cut-off
frequency value reported
(approaching 100 GHz) for any graphene devices to date (Fig. 10
a).Devices on high qualityepitaxially-grown graphene (1-2 layers)
also exhibit the room temperature Hall mobilities up to
1450 (gated) and 1575 (ungated) cm2 V-1s-1 and the record high
epitaxial GFET fT = 24GHz withLG=500nm. (Fig. 10b) IBM has
demonstrated GFET performance well above Si MOSFET fT-Lgtrend shown
in 2008 International Roadmap for Semiconductors (ITRS). [13]
Refererence: [1] M. Y. O. Han, et al., Phys. Rev. Lett., vol.
98, p. 206805, 2007. [2] C. Doan, et al., IEEE Journal of
Solid-StateCircuits, vol. 40, pp. 144-155, Jan. 2005. [3] Y. Zheng,
et al., " Nature, vol. 438, p. 201,2005. [4]. C. Berger, et al.,
J.Phys. Chem B,vol. 108, p. 19912, 2004. [5]. J. Hannon, et al.,
Phys. Rev. Lett., vol. 96, p. 246103, 2006. [6] Z. Chen, et
al.,Physica E, vol., 2007.[7] D. Farmer, et al., Nano Letters, vol.
6, p. 699, 2006. [8] D. Singh, et al., Electronics Letters, vol.
41,pp. 280-282, March 3 2005.[9] E. McCann et al., PRB 74,161403R
(2004). [10] Ohta et al, Science 313, 591 (2006). [11] I. Meric et
al., IEDM Digest 4796738(2008). [12] Y.-M. Lin et al., Nano. Lett.
9, 422 (2009). [13]
http://www.itrs.net/Links/2008ITRS/Home2008.htm
978-1-4244-6031-1/09/$26.00 2009 IEEE
