05 Bus Interface - 99 Slides

8/12/2019 05 Bus Interface - 99 Slides

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Buses and Interfacing

Buses: Data, Address and Control

Bus Cycles:

Read and Write Access, Handshaking (focus on Wait states)

Bus Arbiters

Bus Multiplexing


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Busses


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Bus Definition

A bus is simply a collection of wires carrying various signalsbetween all of the other major components on the embedded

board which include the I/O subsystems, memory subsystem,

and the master processor:

data, addresses

control signals, such as:

clock signals,

requests,

acknowledgements,

data type

On embedded boards, at least one bus interconnects the

other major components in the system


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General Bus Structure

On embedded boards, at least one bus interconnects theother major components in the system

Figure 1: General bus structure


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General Bus Structure

On more complex boards, multiple buses can be integrated on oneboard (see Figure 1).

For embedded boards with several buses connecting componentsthat need to inter-communicate, bridgeson the board connect thevarious buses and carry information from one bus to another.

In figure 2, the PowerManna PCI bridge is one such example. A bridge can automatically provide a transparent mapping of

address information when data is transferred from one bus toanother, implement different control signal requirements for variousbusesacknowledgment cycles, for exampleas well as modify thedata being transmitted if any transfer protocols differ bus to bus.

For instance, if the byte ordering differs, the bridge can handle the byteswapping.


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PowerManna PCI Bridge

Figure 2: MPC620 board with bridge


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Bus Types

Board buses typically fall under one of three main categories: system buses,

backplane buses

I/O buses.


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System buses

System buses (also referred to as main, local, orprocessor-memory buses) interconnect external main

memory and cache to the master CPU and/or any bridges to

the other buses.

System buses are typically shorter, higher speed, custom buses.

Depending of the system architecture, the system bus can be

Internal

External

With respect to the main CPU IC.


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Backplane buses

Backplane buses are also typically faster buses thatinterconnect memory, the master processor, and I/O, all on

one bus.

Usually backplane buses are external


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System Buses vs. I/O buses

The major difference between system buses and I/O buses is thepossible presence of IRQ(interrupt request) control signals on anI/O bus.

There are a variety of ways I/O and the master processor cancommunicate, and interrupts are one of the most common methods. An IRQ line allows for I/O devices on a bus to indicate to the master

processor that an event has taken place or an operation has beencompleted by a signal on that IRQ bus line.

Different I/O buses can have different impacts on interrupt schemes. An ISA bus, for example, requires that each card that generates

interrupts must be assigned its own unique IRQ value (via setting

switches or jumpers on the card). The PCI bus, on the other hand, allows two or more I/O cards to share

the same IRQ value.


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Expandable and Non-expandable Buses

Within each bus category, buses can be further divided into whetherthe bus is expandable or non-expandable. An expandable bus (PCMCIA, PCI, IDE, SCSI, USB) is one in which

additional components can be plugged into the board on-the-fly,

whereas a non-expandablebus (DIB, VME, I2C) is one in whichadditional components cannot be simply plugged into the board and

then communicate over that bus to the other components. systems implementing expandable buses are more flexible because

components can be added ad-hoc to the bus and work out of thebox,

expandable buses tend to be more expensiveto implement.

If the board is not initially designed with all of the possible types ofcomponents that could be added in the future in mind, performance canbe negatively impacted by the addition of too many draining or poorlydesigned components onto the expandable bus.


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Bus Arbitration

Associated with every bus is The type of protocol that defines how devices gain access to the bus

(arbitration),

the rules attached devices must follow to communicate over the bus(handshaking), and

the signalsassociated with the various bus lines.

Board devices obtain access to a bus using a bus arbitrationscheme.

Bus arbitration is based upon devices being classified as

either masterdevices(devices that can initiate a bus transaction) or

slavedevices(devices which can only gain access to a bus inresponse to a master devices request).


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No arbitrationMaster Device Used

The simplestarbitration scheme is for only one device on theboardthe master processorto be allowed to be master,

while all other components are slave devices.

In this case, no arbitration is necessary when there can only

be one master.


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Common Bus Arbitration Schemes

For buses that allow for multiple masters, some have anarbitrator(separate hardware circuitry) that determines under

what circumstances a master gets control of the bus.

the most common bus arbitration schemes are

dynamic central parallel,

centralized serial (daisy-chain), and

distributed self-selection.


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Dynamic Central Parallel Arbitration

Dynamic central parallel arbitration (Figure 3) is a scheme inwhich the arbitrator is centrally located.

All bus masters connect to the central arbitrator.

In this scheme, masters are then granted access to the bus

via a FIFO (Figure 4) or

priority-based system (see Figure 5).

Figure 3Dynamic central parallel arbitration


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The FIFO algorithm implements some type of FIFO queue thatstores a list of master devices ready to use the bus in the

order of bus requests.

Master devices are added at the end of the queue, and are

allowed access to the bus from the start of the queue.

Figure 4 FIFO-based arbitration


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One main drawback is the possibility of the arbitrator notintervening if a single master at the front of the queue

maintains control of the bus, never completing and not

allowing other masters to access the bus.


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Priority-based arbitration

The priority arbitration scheme differentiates between mastersbased upon their relative importance to each other and the

system.

Basically, every master device is assigned a priority, which acts as an

indicator of order of precedence within the system. If the arbitrator implements apreemption priority-based

scheme, the master with the highest priority always can

preempt lower priority master devices when they want access

to the bus, meaning a master currently accessing the bus can

be forced to relinquish it by the arbitrator if a higher priority

master wants the bus.


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Priority-based arbitration

Figure 5 shows three master devices (1, 2, 3) where master 1 is the lowest priority device and master 3 is the

highest);

master 3 preempts master 2, and master 2 preempts master 1

for the bus.

Figure 5: Priority-based arbitration


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Central-serialized (daisy-chain) arbitration

Central-serialized arbitration, also referred to as daisy-chainarbitration, is a scheme in which the arbitrator is connected to

all masters, and the masters are connected in serial.

Regardless of which master makes the request for the bus,

the first master in the chain is granted the bus, and passes thebus grant on to the next master in the chain if/when the bus

is no longer needed (Figure 6).

Figure 6: Centralized serial/daisy-chain arbitration


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Distributed Arbitration Schemes

There are also distributed arbitration schemes, which meansthere is no central arbitrator and no additional circuitry, as

shown in Figure 7.

In these schemes, masters arbitrate themselves by trading

priority information to determine if a higher priority master ismaking a request for the bus, or even by removing all

arbitration lines and waiting to see if there is a collision on the

bus, which means that the bus is busy with more than one

master trying to use it.

Figure 7: Distributed arbitration

via self-selection


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Granting The Bus

Again, depending on the bus, bus arbitrators can grant a bus to a master atomically(until that master is finished with its transmission) or

allow for split transmissions, where the arbitrator can preempt devices in the middle of

transactions, switching between masters to allow other masters to have bus access.

Once a master device is granted the bus, only two devicesa master and

another device in slave modecommunicate over that bus at any giventime.

There are only two types of transactions that a bus device can doREAD (receive) and/or

WRITE (transmit).

These transactions can take place either between two processors (a master and I/O

controller, for example) or processor and memory (a master and memory, for example).

Within each type of transaction, whether READ or WRITE, there can also be several

specific rules that each device needs to follow in order to complete a transaction.

These rules can vary widely between the types of devices communicating, as well as from

bus to bus.

These sets of rules, commonly referred to as the bus handshake, form the basis of any

bus protocol.


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Buses Timing Schemes

The basis of any bus handshake is ultimately determined by abuss timing scheme.

Buses are based upon one or some combination of

synchronous

asynchronous

bus timing schemes, which allow for components attached to

the bus to synchronize their transmissions.


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The Synchronous Bus

A synchronousbus (such as that shown in Figure 8) includes a clock signal

other signals, such as data, address and other control information.

Components using a synchronous bus all are run at the same clock rate asthe bus

data is transmitted either on the rising edge or falling edge of a clock cycle(depending on the bus).

In order for this scheme to work,

components either must be in rather close proximity for a faster clock rate,

or the clock rate must be slowed for a longer bus.

A bus that is too long with a clock rate that is too fast (or even too many

components attached to the bus) will cause a skew in the synchronizationof transmissions, because transmissions in such systems wont be in syncwith the clock.

faster buses typically use a synchronous bus timing scheme.


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The Asynchronous Bus

An asynchronous bus, such as the one shown in Figure 9,transmits no clock signal,

but transmits other (non-clock based) handshaking signals instead,

such as request and acknowledgment signals.

the asynchronous scheme is more complex for devices havingto coordinate request commands, reply commands, and so on,

an asynchronous bus has no problem with the length of the

bus or a larger number of components communicating over

the bus, because a clock is not the basis for synchronizingcommunication.

An asynchronous bus, however, does need some other

synchronizer to manage the exchange of information, and to

interlock the communication.


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THE SCSI Bus

Figure 9: SCSI bus


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Bus Handshaking

handshaking protocols vary with different buses. For example, where one bus requires the transmission of enquiries

and/or acknowledgments with every transmission, other buses may

simply allow the broadcast of master transmissions to all bus (slave)

devices, and only the slave device related to the transaction transmits

data back to the sender.

Another example of differences between handshaking protocols might

be that, instead of a complex exchange of control signal information

being required, a clock could be the basis of all handshaking.


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Buses Transferring Mode Schemes

Buses can also incorporate a variety of transferring modeschemes, which dictate how the bus transfers the data.

The most common schemes are

single, where an address transmission precedes every word

transmission of data, and blocked, where the address is transmitted only once for multiple words

of data.


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Block Transferring Scheme

A blocked transferring scheme can increase the bandwidth of a bus(without the added space and time for retransmitting the sameaddress), and is sometimes referred to as burst transfer scheme.

It is commonly used in certain types of memory transactions, suchas cache transactions.

A blocked scheme, however, can negatively impact bus performancein that other devices may have to wait longer to access the bus.

Some of the strengths of the single transmission scheme include notrequiring slave devices to have buffers to store addresses and themultiple words of data associated with the address, as well as nothaving to handle any problems that could arise with multiple words

of data either arriving out of order or not directly associated with anaddress.


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Classical Bottleneck Problem

Figure 10: Bottleneck Problem


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A Possible Solution

Content Figure 11: A possible solution


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Non-Expandable Bus: I2C Bus Example

The I2C (Inter IC) bus interconnects processors that haveincorporated an I2C on-chip interface, allowing direct

communication between these processors over the bus.

A master/slave relationship between these processors exists

at all times, with the master acting as a master transmitter ormaster receiver.

As shown in Figure 12, the I2C bus is a two-wire bus with

one serial data line (SDA) and

one serial clock line (SCL).


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Figure 12:

Sample analog TV board


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The processors connected via I2C are each addressable by aunique address that is part of the data stream transmitted

between devices.

The I2C master initiates data transfer and generates the clock

signals to permit the transfer. Basically, the SCL just cycles between HIGH and LOW (see

Figure 13).

Figure 13: SCL cycles


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The master then uses the SDA line (as SCL is cycling) totransmit data to a slave.

A session is started and terminated as shown in Figure 14,

where a START is initiated when the master pulls the SDA

port (pin) LOW while the SCL signal is HIGH, whereas aSTOP condition is initiated when the master pulls the SDA

port HIGH when SCL is HIGH.

Figure 14: I2C START and STOP conditionsSTART condition STOP condition


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I2C Features

With regard to the transmission of data, the I2C bus isa serial, 8-bit bus.

This means that, while there is no limit on the numberof bytes that can be transmitted in a session, only one

byte (8 bits) of data will be moved at any one time, 1 bitat a time (serially).

How this translates into using the SDA and SCL signalsis that a data bit is read whenever the SCL signal

moves from HIGH to LOW, edge to edge. If the SDA signal is HIGH at the point of an edge, then

the data bit is read as a 1. If the SDA signal is LOW,the data bit read is a 0.


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A Sample Byte Transfer

An example of byte 00000001 transfer is shown in Figure 15

Figure 15: I2C data transfer example


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A Complete Transfer Session

Figure 16 shows an example of a complete transfer session.

Figure 16: I2C complete transfer diagram


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PCI Bus Example: Expandable

The referred PCI specification,defines requirements (mechanical,electrical, timing, protocols, etc.) of a PCI bus implementation.

PCI is a synchronous bus, meaning that it synchronizescommunication using a clock.

The original standard defines a PCI bus design with

at least a 33 MHz clock (up to 66 MHz) and a bus width of at least 32 bits (up to 64 bits),

giving a possible minimum throughput of approximately 132 Mbytes/sec((33 MHz * 32 bits) / 8)

and up to 528 Mbytes/sec maximum with 64-bit transfers given a 66-MHz clock.

PCI runs at either of these clock speeds, regardless of the clockspeeds at which the components attached to it are running.


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PCI Connection Interfaces

The PCI bus has two connection interfaces (Figure 15): aninternal PCI interface that connects it to the main board (to bridges,

processors, etc.) via EIDE channels, and

the expansion PCI interface, which consists of the slots into which PCI

adaptor cards (audio, video, etc.) plug.

The expansion interface is what makes PCI an expandable

bus; it allows for hardware to be plugged into the bus, and for

the entire system to automatically adjust and operate correctly.


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The PCI Bus

Under the 32-bit implementation, the PCI bus is made up of 49lines carrying (see the table in Figure 17):

multiplexed data and address signals (32 pins)

control signals (17 pins).

Figure 17: PCI bus


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PCI Arbitration Scheme

Because the PCI bus allows for multiple bus masters (initiatorsof a bus transaction), it implements a dynamic centralized,

parallel arbitration scheme(see Figure 18).

Figure 18: PCI arbitration scheme


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PCI Arbitration Scheme

PCIs arbitration scheme basically uses the REQ# and GNT#signals to facilitate communication between initiators and bus

arbitrators.

Every master has its own REQ# and GNT# pin, allowing the

arbitrator to implement a fair arbitration scheme, as well asdetermining the next target to be granted the bus while the

current initiator is transmitting data.


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A PCI transaction

In general, a PCI transaction is made up of five steps:1. An initiator makes a bus request by asserting a REQ# signal to the

central arbitrator.

2. The central arbitrator does a bus grant to the initiator by asserting GNT#signal.

3. The address phase which begins when the initiator activates the

FRAME# signal, and then sets the C/BE[3:0]# signals to define the typeof data transfer (memory or I/O read or write). The initiator then transmitsthe address via the AD[31:0] signals at the next clock edge.

4. After the transmission of the address, the next clock edge starts the oneor more data phases (the transmission of data). Data is also transferredvia the AD[31:0] signals. The C/BE[3:0], along with IRDY# and #TRDY

signals, indicate if transmitted data is valid.5. Either the initiator or target can terminate a bus transfer through the

deassertion of the #FRAME signal at the last data phase transmission.The STOP# signal also acts to terminate all bus transactions


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PCI read example

Figure 19: PCI read example


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PCI write example

Figure 20: PCI write example


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Integrating the Bus with Other Board Components

Buses vary in their physical characteristics, and thesecharacteristics are reflected in the components with which the

bus interconnects, mainly the pinouts of processors and

memory chips which reflect the signals a bus can transmit

(shown in Figure 21).

Figure 21:

PCI compliant IC


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Integrating the Bus with Other Board Components

Within an architecture, there may also be logic that supports busprotocol functionality. As an example, the MPC860 shown in Figure22 includes an integrated I2C bus controller.

As discussed earlier, the I2C bus is a bus with two signals: SDA(serial data) and SCL (serial clock), both of which are shown in theinternal block diagram of the PowerPC I2C controller in Figure 20.

Because I2C is a synchronous bus, a baud rate generator within thecontroller supplies a clock signal if the PowerPC is acting as amaster, along with two units (receiver and transmitter) covering theprocessing and management of bus transactions.

In this I2C integrated controller, address and data information is

transmitted over the bus via the transmit data register and out theshift register.

When the MPC860 receives data, data is transmitted into thereceive data register via a shift register.


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Bus Performance

A buss performance is typically measured by its bandwidth,the amount of data a bus can transfer for a given length of

time.

A buss designboth physical design and its associated

protocolswill impact its performance. In terms of protocols, for example, the simpler the handshaking scheme

the higher the bandwidth (fewer send enquiry, wait for

acknowledgment, etc., steps).

The actual physical design of the bus (its length, the number

of lines, the number of supported devices, and so on) limits orenhances its performance.

The shorter the bus, the fewer connected devices, and the more data

lines, typically the faster the bus and the higher its bandwidth.


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Bus Performance

The number of bus lines and how the bus lines are usedforexample, whether there are separate lines for each signal orwhether multiple signals multiplex over fewer shared linesareadditional factors that impact bus bandwidth. The more bus lines (wires), the more data that can be physically

transmitted at any one time, in parallel.

Fewer lines mean more data has to share access to these lines fortransmission, resulting in less data being transmitted at any one time.

Relative to cost, note that an increase in conducting material on theboard, in this case the wires of the bus, increases the cost of theboard.

Note, however, that multiplexinglines will introduce delayson eitherend of the transmission, because of the logic required on either endof the bus to multiplex and demultiplex signals that are made up ofdifferent kinds of information.


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Bus Width

Another contributing factor to a buss bandwidth is the numberof data bits a bus can transmit in a given bus cycle

(transaction); this is the bus width.

Buses typically have a bandwidth of some binary power of 2such as 1

(20) for buses with a serial bus width, 8 (23) bit, 16 (24) bit, 32 (25) bit,

and so on.

As an example, given 32 bits of data that needs to be

transmitted,

if a particular bus has a width of 8 bits, then the data is divided and sent

in four separate transmissions; if the bus width is 16 bits, then there are two separate packets to

transmit;

a 32-bit data bus transmits one packet, and serial means that only 1

packet at any one time can be transmitted.


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Bus Width

The bus width limits the bandwidth of a bus because it limitsthe number of data bits that can be transmitted in any onetransaction.

Delays can occur in each transmission session, because of

handshaking (acknowledgment sequences),

bus traffic, and

different clock frequencies of the communicating components, that putcomponents in the system in delayingsituations, such as a wait state (atime-out period).

These delays increase as the number of data packets thatneed to be transmitted increases.

Thus, the bigger the bus width, the fewer the delays, and thegreater the bandwidth(throughput).


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Bus Performance

For buses with more complex handshaking protocols, thetransferring scheme implemented can greatly impact

performance.

A block transfer scheme allows for greater bandwidth over the

single transfer scheme, because of the fewer handshakingexchanges per blocks versus single words, bytes (or

whatever) of data.

On the flip side, block transfers can add to the latency due to

devices waiting longer for bus access, since a block transfer-based transaction lasts longer than a single transfer-based

transaction.


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Bus Performance

A common solution for this type of latency is a bus that allowsfor split transactions, where the bus is released during the

handshaking, such as while waiting for a reply to

acknowledgement.

This allows for other transactions to take place, and allows thebus not to have to remain idle waiting for devices of one

transaction.

However, it does add to the latency of the original transaction

by requiring that the bus be acquired more than once for asingle transaction.


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Buses

The main elements of a basic computer system are a central processing unit (or microprocessor),

memory,

I/O interfacing circuitry.

These connect by means of three main buses: the address bus, the control bus and

the data bus.

A bus is a collection of common electrical connectionsgrouped by a single name.

External devices such as a keyboard, display, disk drives canconnect directly onto the data, address and control buses or

through the I/O interface circuitry.


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A simple computer system

Figure 23: Block diagram of a simple computer system


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Control Bus, Address Bus, Data Bus

Pentium CPU Host Bus (Frontside Bus)

Memory

ALUControl

Logic

Registers

I/O

Controller (C/P) Single lines

Groups of lines

Address

Bus

Data

Bus

Control

Bus

Outside

world


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Bus specification

Data rate (in bytes per second or bits per second). This defines the maximum amount of data that can be transferred, at a

time.

ISA bus has a maximum data rate of 16MB/s, Gigabit Ethernet has a maximum data

rate of 125MB/s, PCI - homework.

Maximum number of devices which connect to the bus. Standard SCSI only allows a maximum of 7devices to be connected to

the bus,

Ethernet can allow thousands of devices to connect to the bus.

Bus reliability. defines how well the bus copes with any errors which occur on the bus


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Bus specification

Data robustness. Busses such as the CAN bus can isolate incorrectly operating devices.

Electrical/physical robustness.

This is the ability of the bus to cope with electrical faults, especially due

to short-circuits and power surges. Ease-of-connection.

This includes the availability of cables and connectors, and how easy it

is to add and remove devices from the bus.

Bus controller topology. This relates to the method that is used to control the flow of data around the bus.


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Bus specification

Communications overhead. a measure of the amount of data that is added to the original data, so

that it can be sent in a reliable way.

Local, fast busses normally have a minimum of overhead,

remote, networked busses have a relatively large overhead on the

transmitted data.

Software interfacing

Cable and connectors

Standardization of the bus

Power supply modes.


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Bus components

Devices connect to each other within a computer using a bus. The bus can either be

an internal bus

the IDE bus which connects to hard disks and CD-ROM drives within a PC

an external bus the USB which can connect to a number of external devices

Busses typically have a number of basic components:

a data bus

an optional address bus

control lines and

handshaking lines


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Model of a computer bus

Figure 25: Computer Bus Model


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Data bus - Parallel

is normally faster can transmit more bits in a single operation

require many more lines

thus requiring more wires in the cable

normally requires extra data handshaking lines to synchronizethe flow of data between devices

Are typically used

for local busses,

or where there are no problems with cables with a relatively largenumber of wires.

Examples: PCI, SCSI and IDE


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Data bus - serial

normally uses a start and end bit sequence to define the startand end of transmission.

typical serial busses are RS-232, and the USB.

can operate at very high transmission rates;

the main limiting factor is the transmission channel and thetransmitter/receiver electronics.

Gigabit Ethernet, for example, uses a transmission rate of 1Gbps(125MB/s) over high-quality twisted-pair copper cables, or over fibreoptic cables.

For a 32-bit parallel bus, this would require a clocking rate ofonly 31.25MHz which requires much lower quality connectors and cables than the

equivalent serial interface.


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Data transfer rates

The amount of data that a system can transfer at a time is normally defined either in

bits per second (bps) or

bytes per second (B/s).

The transfer of the data occurs are regular intervals, which is

defined by the period of the transfer clock.

(s)operationperimeTransfer t

(bits)operationperedtransmittbitsofNumber(bps)ratetransferData


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Address bus The address bus is responsible for identifying the location into which the

data is to be passed into. Each location in memory typically contains a single byte (8 bits),

but could also be arranged as words (16 bits), or long words (32 bits).

Byte-oriented memory is the most flexible as it also enables access to anymultiple of eight bits.

The size of the address bus thus indicates the maximum addressablenumber of bytes. The number of addressable bytes is given by:

Addressable locations = 2nbytes where n is the number of bits in the address bus.

For example:

A 1-bit address bus can address up to two locations

A 2-bit address bus can address 22or 4 locations A 20-bit address bus can address up to 220 addresses (1MB)

A 32-bit address bus can address up to 232 addresses (4GB)


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Addressable memory vs. address bus size

Address

bus size

Addressable

memory

(bytes)

Address

bus size

Addressable

memory

(bytes)

Address

bus size

Addressable

memory

(bytes)

1 2 11 2K 21 2M

2 4 12 4K 22 4M

3 8 13 8K 23 8M

4 16 14 16K 24 16M

5 32 15 32K 25 32M

6 64 16 64K 26 64M

7 128 17 128K 32 4G

8 256 18 256K 64 16GG

9 512 19 512K 128 Homework

10 1K 20 1M 256 Homework


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Address bus - Implementation

Early processors used a wire for each bit of theaddress width.

For example, a 16-bit address bus had 16 physical wires

making up the bus.

As the bus becomes wider, this approach becomes lessconvenient and more expensive to implement.

some modern processors make the address bus

faster than the data bus, and send the address in two

parts.

For example a 32-bit address bus can be implemented by

using 16 wires and sending the first half of the memory

address, immediately followed by the second half.


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Address bus - Interesting examples

Accessing an individual byte frequently requiresreading or writing the full bus width (a word) at once.

In these instances the least significant bits of the

address bus may not even be implemented - it is

instead the responsibility of the controlling device to

isolate the individual byte required from the complete

word transmitted.

This is the case, for instance, with the VESA LocalBus which lacks the two least significant bits, limiting

this bus to aligned 32-bit transfers.


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Data handshaking

a bridgeprovides conversion between one type of bus andanother.

Sometimes devices connect directly onto the processors bus;

this is called a local bus, and is used to provide a fast

interface with direct access without any conversions. The most basic type of handshaking has two lines:

Sending identification linethis identifies that a device is ready to

send data.

Receiving identification linethis identifies that device is a device is

ready to receive data, or not.


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Computer bus connections

Figure 27: Computer bus connections


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Main types of communication

Simplex communication. Only one device can communicate with the other,

requires handshaking lines for one direction.

Half-duplex communication. allows communications from one device to the other, in any

direction, requires handshaking lines for either direction.

Full-duplex communications. allows communication from one device to another, in either

direction, at the same time.

A good example of this is in a telephone system, where a callercan send and receive at the same time.

requires separate transmit and receive data lines,

Requires separate handshaking lines for either direction.

Si l h d h ki f d


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Simple handshaking of data

Figure 28: Simple handshaking of data

C t l li


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Control lines

define the operation of the data transaction, such as: Data flow direction

identifies that data is either being read or written from / to a device.

Memory addressing type this is typically either by identifying that the address access is direct

memory accessing or indirect memory access.

This identifies that the address on the bus is either a real memorylocation or is an address tag.

Device arbitration this identifies which device has control of the bus,

is typically used when there are many devices connected to acommon bus, and any of the devices are allowed to communicatewith any other of the devices on the bus.


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M R d


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Memory Read

1. The CPU selects the memory location by driving theaddress on the address bus.

2. Control lines are driven by the CPU to indicate theaddress space to use, such as program memory,data memory, I/O, or special cycles such as

interrupts.3. Read is activated on the control bus by the CPU to

indicate that the memory can drive the data bus withthe contents of the selected location.

4. The memory drives the contents of the selectedlocation on the data bus.

5. The CPU deactivates the address and control lines,turning off the memory drivers.

M R d C l


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Memory Read Cycles

Figure 30: Generic CPU reading instructions and data from memory

M W it


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Memory Write

1. The CPU selects the memory location by driving theaddress on the address bus.

2. Control lines are driven by the CPU to indicate the address

space to use.

3. The CPU drives the data to be written on the data bus.4. Write is activated on the control bus by the CPU to indicate

that the data on the data bus should be written into the

selected location.

5. The CPU deactivates the address, data, and control lines.

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Memory Write

Content

Figure 31: Generic CPU writing data to memory

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Bus contention

is an undesirable state of the bus in which more than onedevice on the bus attempts to place values on the bus at the

same time

Most bus architectures require their devices follow an

arbitration protocol Contention can lead to erroneous operation, and in unusual

cases, damage to the hardware

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Bus Multiplexing

In the case of a processor with a multiplexed addressand data bus, some or all of the data bus is multiplexedor shared with the address bus.

An additional signal is provided on the control bus to

enable an address storage latch to hold the addressinformation at the beginning of a transfer cycle.

Bus cycles on a multiplexed address/data bus system,are identical to those illustrated previously except forthe addition of address information on the data bus atthe beginning of a cycle, and an address latch controlsignal.

The 8051 has a multiplexed bus cycle.

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Multiplexed address/data bus cycles

Figure 32: Multiplexed address/data bus cycles

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Bus demultiplexing - implementation

As soon as the address latch enable (ALE) is high, theaddress latch allows the multiplexed address from theaddress/data bus through to the latch output.

When the ALE signal goes low, the address remains frozenon the latch output, and the CPU can remove the address

lines from the bus and begin a data transfer. The address latch must be a transparent latch with active

high enable, such as the 74xx373 device. If the ALE signal was inverted, the 374 latch would sample and

hold the address at the end of the ALE pulse.

While this could function correctly, it would delay the availability ofthe address to the memory devices, leaving less time for them toaccess the addressed location.

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Address demultiplexing with a latch

Figure 33: Address demultiplexing with a latch

Address Spaces and Decoding


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Address Spaces and Decoding

Processors, depending upon the particular architecture, mayhave several separate address spaces:

program memory address space

data memory address space

input/output device address space

stack address space

Depending on the processor, these may be

completely separate,

overlapping, or

all-in-one address space.

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Supplementary Reading


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Supplementary Reading

Ken Arnold, Embedded Controller Hardware Design, LLHTechnology Publishing, 2000

Chapter 5 CPU Bus Interface and Timing

Documents

05 Bus Interface - 99 Slides